5T9955BFGI8

IDT5T9955 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK™ W FEATURES: IDT5T9955 DESCRIPTION: • Ref input is 3.3V tolerant • 8 pairs of programmable skew outputs • Low skew: 185ps same pair, 250ps same bank, 350ps both banks • Selectable positive or negative edge synchronization on each bank: excellent for DSP applications • Synchronous output enable on each bank • Input frequency: 2MHz to 160MHz • Output frequency: 6MHz to 160MHz • 3-level inputs for skew and PLL range control • 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4) • PLL bypass for DC testing • External feedback, internal loop filter • 12mA balanced drive outputs • Low Jitter: 3MHz) tCCJLA Cycle-to-Cycle Output Jitter (peak-to-peak) (divide by 1 output frequency, xFS = L, FREF < 3MHz) NOTES: 1. Refer to Input Timing Requirements table for more detail. 2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified load. 3. tSKEWPR is the skew between a pair of outputs (xnQ0 and xnQ1) when all sixteen outputs are selected for 0tU. 4. tSK(0) is the skew between outputs when they are selected for 0tU. 5. tSKEWB is the skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU. 6. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (x4Q0 and x4Q1 only with x4F0 = x4F1 = HIGH), and Divided (x3Q1:0 and x4Q1:0 only in Divideby-2 or Divide-by-4 mode). Test condition: xnF0:1=MM is set on unused outputs. 7. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) 8. tφ is measured with REF input rise and fall times (from 0.7V to 1.7V) of 0.5ns. Measured from 1.25V on REF to 1.25V on xFB. 9. Measured at 1.7V. 10. Measured at 0.7V. 11. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or xFB until tPD is within specified limits. 12. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter. 8 IDT5T9955 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE AC TEST LOADS AND WAVEFORMS VDDQ 150Ω Output Output 150Ω 20pF For LOCK output For all other outputs tOFALL tORISE tPWH 1.7V VTH = 1.25V tPWL 0.7V 2.5V Output Waveform ≤1ns 2.5V 1.7V VTH = 1.25V 0.7V 0V LVTTL Input Test Waveform 9 ≤1ns 20pF IDT5T9955 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE AC TIMING DIAGRAM tRPWL tREF tRPWH REF t(φ) tODCV tODCV FB tCCJ1-3, 4-6, 8-12 Q tSKEWPR, B tSKEW0, 1 tSKEWPR, B tSKEW0, 1 OTHER Q tSKEW2 tSKEW2 INVERTED Q tSKEW3, 4 tSKEW3, 4 tSKEW3, 4 REF DIVIDED BY 2 tSKEW1, 3, 4 tSKEW2, 4 REF DIVIDED BY 4 NOTES: PE: The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align. Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated with 75Ω to VDDQ/2. tSKEWPR: The skew between a pair of outputs (xnQ0 and xnQ1) when all eight outputs are selected for 0tU. tSKEWB: The skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0tU. tSKEW0: The skew between outputs when they are selected for 0tU. tDEV: The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.) tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. tPWH is measured at 1.7V. tPWL is measured at 0.7V. tORISE and tOFALL are measured between 0.7V and 1.7V. tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 10 IDT5T9955 2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX Device Type XX Package X Package I -40°C to +85°C (Industrial) BF BFG Fine Pitch Ball Grid Array FBGA - Green 5T9955 2.5V Programmable Skew Dual PLL Clock Driver TurboClock W CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 11 for Tech Support: clockhelp@idt.com