5V41065PGG8

DATASHEET IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Recommended Applications Features/Benefits 2 Output synthesizer for PCIe Gen1/2 and Ethernet • 16-pin TSSOP and QFN packages; small board footprint • Spread-spectrum capable; reduces EMI • Outputs can be terminated to LVDS; can drive a wider General Description variety of devices The IDT5V41065 is a PCIe Gen2 compliant spread spectrum capable clock generator. The device has 2 differential HCSL outputs and can be used in communication or embedded systems to substantially reduce electro-magnetic interference (EMI). The spread amount and output frequency are selectable via select pins. The IDT5V41065 can also supply 25 MHz, 125 MHz and 200 MHz outputs for applications such as Ethernet. • 25 MHz, 125 MHz and 200 MHz output frequencies; TSSOP only • 100MHz and 200MHz output frequencies; VFQFPN package • OE control pin; greater system power management • Spread% and frequency pin selection; no software required to configure device Output Features • Industrial temperature range available; supports • 2 - 0.7V current mode differential HCSL output pairs • For PCIe Gen3 applications, see the 5V41235 demanding embedded applications Key Specifications • Cycle-to-cycle jitter < 100 ps • Output-to-output skew < 50 ps • PCIe Gen2 phase jitter < 3.0ps RMS Block Diagram VDD 2 SS1:SS0 2 S1:S0 CLK0 Control Logic 2 X1/ICLK 25 MHz crystal or clock X2 Optional tuning crystal capacitors IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER CLK0 Phase Lock Loop CLK1 Clock Buffer/ Crystal Oscillator CLK1 2 GND 1 Rr(IREF) OE IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER CLK0 SS0 3 14 CLK0 CLK0# 15 16 15 14 13 S1 SS0 X1/CLK X2 1 2 3 4 X1/ICLK 4 13 GNDODA X2 5 12 VDDODA OE 6 11 CLK1 5 GNDXD 7 10 CLK1 SS1 8 9 IREF 12 11 10 9 5V41065 6 7 GNDODA VDDODA CLK1 CLK1# 8 IREF 2 CLK0 S1 SS1 VDDXD VDDXD 16 GNDXD 1 OE S0 S0 Pin Assignment 16-pin VFQFPN 16-pin (173 mil) TSSOP Output Select Table 1 (MHz)–TSSOP only Output/Spread Select Table 3 - VFQFPN Only S1 S0 CLK(1:0), CLK(1:0) S1 S0 SS1 SS0 Output Spread% 0 0 25M 0 0 0 0 100MHz -0.5 0 1 100M 0 0 0 1 200MHz -0.5 0 1 0 100MHz No spread 1 0 125M 0 1 1 200M 0 0 1 1 0 1 0 0 100MHz -1 0 1 0 1 200MHz -1 1 1 0 Reserved Reserved Spread Selection Table 2–TSSOP only Reserved SS1 SS0 Spread% 0 0 0 No Spread 0 1 1 1 0 1 Down -0.5 1 0 0 0 100MHz -1.5 1 0 Down -0.75 1 0 0 1 200MHz -1.5 No Spread 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 2 1 1 0 1 1 1 1 0 200MHz Reserved 1 1 1 1 Reserved IDT5V41065 No spread APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Pin Descriptions VFQFPN TSSOP Pin Pin Number Number Pin Name Pin Type Pin Description 16 1 S0 Input Select pin 0. See Table1. Internal pull-up resistor. 1 2 S1 Input Select pin 1. See Table 1. Internal pull-up resistor. 2 3 SS0 Input Spread Select pin 0. See Table 2. Internal pull-up resistor. 3 4 X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 4 5 X2 5 6 OE Input 6 7 GNDXD Power 7 8 SS1 Input 8 9 IREF Output Precision resistor attached to this pin is connected to the internal current reference. 9 10 CLK1 Output HCSL complementary clock output 1. Output HCSL true clock output 1. Output Crystal connection. Leave unconnected for clock input. Output enable. Tri-states outputs and device is not shut down. Internal pull-up resistor. Connect to ground. Spread Select pin 1. See Table 2. Internal pull-up resistor. 10 11 CLK1 11 12 VDDODA Power Connect to voltage supply +3.3 V for output driver and analog circuits 12 13 GNDODA Power Connect to ground. 13 14 CLK0 Output HCSL complementary clock output 0. Output HCSL true clock output 0. 14 15 CLK0 15 16 VDDXD IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit. 3 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Applications Information Output Structures External Components A minimum number of external components are required for proper operation. IREF =2.3 mA 6*IREF Decoupling Capacitors Decoupling capacitors of 0.01F should be connected between each VDD pin and the ground plane, as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin. Crystal A 25 MHz fundamental mode parallel resonant crystal should be used. This crystal must have less than 300 ppm of error across temperature in order for the IDT5V41065 to meet PCI Express specifications. R R 475 See Output Termination Sections - Pages 3 ~ 5 Crystal Capacitors General PCB Layout Recommendations Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01µF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. CL= Crystal’s load capacitance in pF Crystal Capacitors (pF) = (CL- 8) * 2 2. No vias should be used between decoupling capacitor and VDD pin. For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. Current Source (Iref) Reference Resistor - RR If board target trace impedance (Z) is 50, then RR = 475 (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the IDT5V41065.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Output Termination The PCI-Express differential clock outputs of the IDT5V41065 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The IDT5V41065 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 4 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Layout Guidelines SRC Reference Clock Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt D imension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch ohm ohm Figure 1 1 1 1 1 Down Device Differential Routing L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 2 min to 16 max 1.8 min to 14.4 max inch inch 1 1 Differential Routing to PCI Express Connector L4 length, route as coupled microstrip 100ohm differential trace L4 length, route as coupled stripline 100ohm differential trace 0.25 to 14 max 0.225 min to 12.6 max inch inch 2 2 Figure 1: Down Device Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' PCI Express Down Device REF_CLK Input L3 Figure 2: PCI Express Connector Routing L2 L1 Rs L4 L4' L2' L1' Rs Rt HCSL Output Buffer Rt L3' IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 5 PCI Express Add-in Board REF_CLK Input L3 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm R1 R2 R3 R4 Note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible 0.60 0.3 1.2 33 174 140 100 Standard LVDS R1a = R1b = R1 R2a = R2b = R2 Figure 3 L2 L1 R3 R1a R4 L4 L4' L2' L1' R1b R2a HCSL Output Buffer R2b L3' Down Device REF_CLK Input L3 Cable Connected AC Coupled Application (figure 4) Component Value Note R5a, R5b 8.2K 5% R6a, R6b 1K 5% Cc 0.1 µF Vcm 0.350 volts Figure 4 3.3 Volts R5a R5b R6a R6b Cc L4 L4' Cc IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 6 PCIe Device REF_CLK Input IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 500 ps 500 ps 0.525 V 0.175 V tOF 0.525 V 0.175 V Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps 1250 mV 1150 mV IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER tOF 1250 mV 1150 mV 7 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V41065. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDDXD, VDDODA 4.6 V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature (commercial) 0 to +70C Ambient Operating Temperature (industrial) -40 to +85C Storage Temperature -65 to +150C Junction Temperature 125C Soldering Temperature 260C ESD Protection (Input) 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85C Parameter Symbol Supply Voltage Conditions V Input High Voltage 1 Min. Typ. Max. Units 3.135 3.3 3.465 V VIH S0, S1, OE, ICLK, SS0, SS1 2.2 VDD +0.3 V VIL S0, S1, OE, ICLK, SS0, SS1 VSS-0.3 0.8 V Input Leakage Current IIL 0 < Vin < VDD 5 A Operating Supply Current @100 MHz IDD RS=33RP=50, CL=2 pF 63 85 mA OE =Low 42 50 mA 7 pF Input Low Voltage 1 2 Input Capacitance IDDOE CIN -5 Input pin capacitance Output Capacitance COUT 6 pF X1, X2 Capacitance CINX 5 pF Pin Inductance LPIN 5 nH Output Impedance Pull-up Resistor ZO RPU Output pin capacitance CLK outputs 3.0 S0, S1, OE, SS0, SS1 k 100 k 1. Single edge is monotonic when transitioning through region. 2. Inputs with pull-ups/-downs are not included. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 8 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1 Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85C Parameter Symbol Conditions Min. Typ. Input Frequency 25 200 MHz LVDS termination 25 100 MHz 850 mV VOH HCSL Voltage1,2 VOL HCSL -150 Absolute 250 Voltage1,2 Crossing Point Voltage1,2,4 mV Variation over all edges Jitter, Cycle-to-Cycle1,3 Frequency Synthesis Error All outputs Modulation Frequency Rise Time1,2 Fall Time1,2 Rise/Fall Time MHz HCSL termination Output High Voltage1,2 Crossing Point Units 25 Output Frequency Output Low Max. 550 mV 140 mV 100 ps 0 32.9 ppm Spread spectrum 30 33 kHz tOR From 0.175 V to 0.525 V 175 700 ps tOF From 0.525 V to 0.175 V 175 700 ps 125 ps Variation1,2 Output to Output Skew Duty Cycle1,3 45 50 ps 55 % Output Enable Time5 All outputs 50 100 ns Output Disable Time5 All outputs 50 100 ns Stabilization Time tSTABLE From power-up VDD=3.3 V Spread Spectrum Transition Time tSPREAD Stabilization time after spread spectrum changes 7 1.8 ms 30 ms Note 1: Test setup is RS=33RP=50 with CL=2 pF, Rr = 475 (1%). Note 2: Measurement taken from a single-ended waveform. Note 3: Measurement taken from a differential waveform. Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal. Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high. Electrical Characteristics - Differential Phase Jitter Parameter Jitter, Phase Symbol Conditions Min Typ Max Units Notes tjphasePLL PCIe Gen1 32 86 ps (p-p) 1,2,3 tjphaseLO PCIe Gen2, 10 kHz < f < 1.5 MHz 0.8 3 ps (RMS) 1,2,3 PCIe Gen2, 1.5 MHz < f < Nyquist (50 MHz) 2.3 3.1 ps (RMS) 1,2,3 tjphaseHIGH Note 1. Guaranteed by design and characterization, not 100% tested in production. Note 2. See http://www.pcisig.com for complete specs. Note 3: Applies to 100MHz, spread off and 0.5% down spread only. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 9 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Thermal Characteristics (16TSSOP) Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA Thermal Resistance Junction to Case Conditions Min. Still air 1 m/s air flow 3 m/s air flow JC Typ. Max. Units 78 C/W 70 C/W 68 C/W 37 C/W Thermal Characteristics(16VFQFPN) Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Symbol Conditions Min. Typ. Max. Units JA Still air 63.2 C/W JA 1 m/s air flow 55.9 C/W JA 3 m/s air flow 51.4 C/W 65.8 C/W JC 10 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Marking Diagram (5V41065PGG) 16 Marking Diagram (5V41065PGGI) 16 9 IDT5V410 65PGGI YYWW$ IDT5V410 65PGG YYWW$ 1 9 1 8 8 Notes: 1. Line 1 and 2: IDT part number. 2. Line 3: YYWW – Date code; $ – Assembly location. 3. “G” after the two-letter package code designates RoHS compliant package. 4. “I” at the end of part number indicates industrial temperature range. 5. Bottom marking: country of origin if not USA. Marking Diagram (5V41065NLGI) Marking Diagram (5V41065NLGI) XXX YWW$ 065G XXX YWW$ 065GI Notes: 1. Line 1: Lot number. 2. Line 2: YWW – Date code; $ – Assembly location. 3. “G” designates RoHS compliant package. 4. “I” at the end of part number indicates industrial temperature range. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 11 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 12 Package Outline and Package Dimensions (16-pin QFN) IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 13 Package Outline and Package Dimensions (16-pin QFN), cont. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 14 Package Outline and Package Dimensions (16-pin TSSOP) IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 15 Package Outline and Package Dimensions (16-pin TSSOP), cont. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 16 Package Outline and Package Dimensions (16-pin TSSOP), cont. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Ordering Information Part / Order Number Marking 5V41065PGG See Page 11 Shipping Packaging Package Temperature Tubes 16-pin TSSOP 0 to +70 C 5V41065PGG8 Tape and Reel 16-pin TSSOP 0 to +70 C 5V41065PGGI Tubes 16-pin TSSOP -40 to +85 C 5V41065PGGI8 Tape and Reel 16-pin TSSOP -40 to +85 C Trays 16-pin QFN 0 to +70 C 5V41065NLG8 5V41065NLG See Page 11 Tape and Reel 16-pin QFN 0 to +70 C 5V41065NLGI Trays 16-pin QFN -40 to +85 C 5V41065NLGI8 Tape and Reel 16-pin QFN -40 to +85 C “G” after the two-letter package code are the Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. Revision History Rev. Originator A Date Description of Change 07/15/08 New datasheet; Preliminary initial release. B RDW 01/13/10 Added Gen2 to title; update Electrical tables per char; added Differential Phase Jitter table. C RDW 04/27/10 Updated electrical tables per char; VDD is now 3.3 ±5%; released to final. D RDW 07/19/10 1. Updated title and general description 2. Updated cycle-to-cycle jitter spec from 125 to 100 ps. E RDW 11/21/11 1. Changed title to “2 Output PCIe GEN1/2 Synthesizer” 2. Added note to Features section: “For PCIe Gen3 applications, see 5V41235” 3. Updated Differential Phase Jitter table. F J, Chao 08/26/13 1. Added 16VFQFPN notes in Features section 2. Added pinout and “Output/Spread Selection” table for 16VFQFPN. 3. Updated Pin Description table to include VFQFPN pin descriptions. 4. Added Thermal Characteristics table for 16VFQFPN. 5. Added marking diagrams for 16VFQFPN. 6. Added Package Dimensions/Drawing for 16VFQFPN. 7. Updated Ordering Information to include 16VFQFPN. G C.P. 04/17/17 1. Replaced package outline drawings with latest NLG16 and PGG16 drawings. 2. Updated legal disclaimer. IDT® 2 OUTPUT PCIE GEN1/2 SYNTHESIZER 17 IDT5V41065 APRIL 17, 2017 IDT5V41065 2 OUTPUT PCIE GEN1/2 SYNTHESIZER Innovate with IDT and accelerate your future networks. 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