5V80001PGGI

DATASHEET MOST® CLOCK INTERFACE IDT5V80001 Description Features The IDT5V80001 is a high performance clock interface for use in MOST® (Media Oriented Systems Transport) enabled systems. It can be used in two modes: generating a master clock for the ring, or performing clock/data recovery in a slave node. • • • • • • • • Packaged in 20-pin TSSOP -40 to +85°C temperature range (industrial) Compliant to AEC Q100 Operating voltage of 3.3 V 5 volt tolerant input for FOT Low jitter generation Power-down tri-state mode Advanced, low-power CMOS process Block Diagram BYPASS FOT_IN 1 Retiming MOST_Din FOT_OUT 0 MUX 0 1 RESET CDR PLL INPUT_COPY RCLK X1 Crystal Oscillator Master PLL MCLK X2 S1 IDT™ MOST® CLOCK INTERFACE S0 1 OEM IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Pin Assignment Frequency Selection Tables S1 S0 X2 1 20 NC X1 2 19 MOST_Din RESET 3 18 INPUT_COPY VDD 4 17 VDD FOT_OUT 5 16 RCLK GND 6 15 GND S1 7 14 MCLK FOT_IN S0 8 13 OEM 9 12 BYPASS 10 11 LFR LF Operating Frequency (RCLK) Mode Sampling Frequency 0 0 45.1584 MHz MOST 25 44.1 kHz 0 1 49.152 MHz MOST 25 48 kHz 1 0 90.3168 MHz MOST 50 44.1 kHz 1 1 98.304 MHz MOST 50 48 kHz OEM MCLK Output Source for Retiming Block 0 LOW RCLK (slave node) 1 Running MCLK (master node) 20-pin TSSOP OEM Node Bypass FOT_OUT 0 Slave 0 Retimed (RCLK) MOST_Din* 1 FOT_IN 0 Retimed (MCLK) MOST_Din 1 FOT_IN 1 Master * FOT_IN must be present in order to generate RCLK and Retimed (RCLK) MOST_Din. Pin Descriptions Pin Name Type 1 X2 Input Connect to 21.504 MHz crystal. 2 X1 Input Connect to 21.504 MHz crystal. 3 RESET Input Low to reset CDR PLL. Internal pull-up resistor. 4 VDD Power Connect to 3.3 V supply. 5 FOT_OUT Output Output for fiber optic MOST transceiver. 3.3 V LVTTL levels. 6 GND Power Connect to ground. 7 S1 Input Frequency select input pin. See table above. No internal pull-up or pull-down resistor. 8 FOT_IN Input Input to device from fiber optic MOST transceiver. 3.3 V LVTTL levels, 5 V tolerant. 9 S0 Input Frequency select input pin. See table above. No internal pull-up or pull-down resistor. IDT™ MOST® CLOCK INTERFACE Pin Description 2 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Pin Name Type Pin Description 10 LF Input Loop filter connection for CDR PLL. 11 LFR Input Loop filter return. Connected to ground internally. 12 BYPASS Input MUX control to bypass CDR PLL. Active high. No internal pull-up or pull-down resistor. 13 OEM Input High to enable MCLK. See table above. No internal pull-up or pull-down resistor. 14 MCLK Output Master clock output. Clean clock derived from crystal. See table above. Weak pull-down when OEM = 0. 15 GND Power Connect to ground. 16 RCLK Output Recovered clock out. See table above. 17 VDD Power Connect to 3.3 V supply. 18 INPUT_COPY Output Retimed copy of FOT_IN input. 19 MOST_Din Input 20 NC — MOST data input. No Connect. Do not connect this pin to anything. Operation To recover the clock from the data stream, the two PLLs work together. The lock sequence from power on is: The IDT5V80001 performs clock generation and recovery for either a master or slave node in a MOST ring. It provides a interface between a controller (typically implemented in an ASIC or FPGA) and the fiber optic transceiver (FOT). 1. Crystal oscillator starts and stabilizes. 2. Master (frequency synthesis) PLL starts and locks to the crystal. 3. CDR PLL starts and locks to the master PLL to obtain a frequency operation point. 4. Activity is detected on FOT_IN. 5. CDR PLL phase-locks to incoming data. When used in a Master node (OEM = High), the Master PLL synthesizes a frequency of twice the MOST data rate as the MCLK output, and also reclocks the data from the controller that is input on the FOT_IN pin to the INPUT_COPY output. The output data on FOT_OUT is the MOST_Din data retimed to MCLK if BYPASS is driven low, or the FOT_IN data if BYPASS is driven high. Simultaneously, the device recovers the clock from data on the FOT_IN pin and outputs a 2x clock on RCLK. Extreme conditions, such as electrical transients, phase steps or brief dropouts on the FOT_IN pin may cause the CDR PLL to unlock. If this occurs and the controller begins to experience data errors, it should set RESET low for at least 50 ns to restart the data lock sequence from step 3. In a slave node, OEM is set low and the MCLK output is disabled. Data from the controller (FOT_IN) is retimed using the recovered clock and output on the INPUT_COPY. If BYPASS is driven high, the controller data (FOT_IN) is also transmitted on the FOT_OUT output but is not retimed to RCLK. If BYPASS is driven low, the MOST_Din data is retimed and transmitted on the FOT_OUT output. IDT™ MOST® CLOCK INTERFACE 3 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS External Components The nominal impedance of the clock output is 20 Ω. The IDT5V80001 requires a minimum number of external components for proper operation. PCB Layout Recommendations Decoupling Capacitor For optimum device performance and lowest output phase noise, the following guidelines should be observed. A decoupling capacitor of 0.01µF must be connected between each VDD pins and the ground plane, as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Crystal The IDT5V80001 requires a 21.504 MHz parallel resonant crystal. Recommended devices are: Manufacturer Package 2) The external crystal should be mounted just next to the device with short traces. Part # Abracon 5x7 mm ceramic AAH-363-21.504MHz NDK 3.2x5 mm ceramic EXS00A-CG00294 3) The external loop filter components should be mounted close to the IDT5V80001 and away from digital signals, switching power supply components, and other sources of noise. Crystal Load Capacitors The device crystal connections should include pads for capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. 4) To minimize EMI, 33 Ω series termination resistors should be placed close to the clock outputs. 5) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the IDT5V80001. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. The value (in pF) of these crystal caps should equal (CL -12 pF)*2. In this equation, CL= crystal load capacitance in pF. For the specified 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2 = 8]. External Loop Filter External Loop Filter An external loop filter is required for operation of the CDR PLL. Recommended components are: RS = 1210 Ω, 1% tolerance CS = 10 nF, use capacitor with a non-piezoelectric dielectric. Recommended type is Panasonic ECH-U01103GX5 or equivalent. LF 9 12 10 11 RS Series Termination Resistor LFR CS Termination should be used on the FOT_OUT, MCLK, RCLK, and INPUT_COPY output (pins 5, 14, 16, and 18 respectively). To series terminate a 50 Ω trace (a commonly used trace impedance) place a 33 Ω resistor in series with the clock line, as close to the clock output pin as possible. IDT™ MOST® CLOCK INTERFACE 4 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the IDT5V80001. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V Inputs and Outputs -0.5 V to VDD+0.5 V Input (FOT_IN only) 7V Storage Temperature -65 to +150° C Junction Temperature 125° C Soldering Temperature 260° C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature -40 Power Supply Voltage (measured with respect to GND) +3.0 Power Supply Ramp Time IDT™ MOST® CLOCK INTERFACE 5 Typ. +3.3V Max. Units +85 °C +3.6 V 4 ms IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C Parameter Operating Supply Current Symbol Conditions IDD No load, FRCLK = 49.152 MHz FOT_IN, MOST_Din High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIH VIL VOH Min. Typ. Max. 35 Units mA 2 5.5 RESET, BYPASS, OEM, S0, S1 2.0 VDD+0.3 FOT_IN, MOST_Din -0.3 0.8 RESET, BYPASS, OEM, S0, S1 -0.3 0.8 FOT_OUT only, IOH = -2 mA 2.4 MCLK, RCLK, INPUT_COPY IOH = -100 µA VDD-0.2 V V V FOT_OUT only, IOH = 2 mA 0.4 0.2 V Low Level Output Voltage VOL MCLK, RCLK, INPUT_COPY IOH = 100 µA Short Circuit Current IOS FOT_OUT 35 Input Capacitance CIN FOT_IN, MOST_Din, RESET, BYPASS, OEM, S0, S1 5 FOT_OUT, MCLK, RCLK, INPUT_COPY 20 Ω RESET 500 kΩ Nominal Output Impedance On-Chip Pull-up or Pull-down Resistor IDT™ MOST® CLOCK INTERFACE ZOUT RP 6 mA 10 IDT5V80001 pF REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Timing Requirements Parameter Crystal Frequency Input Rise Time Input Fall Time Input Pulse Width Variation (FOT_IN and MOST_Din) Average Input Pulse Width Distortion (FOT_IN and MOST_Din) One-Sigma Data Dependent Jitter (FOT_IN) One-Sigma Uncorrelated Jitter CDR Reset Time IDT™ MOST® CLOCK INTERFACE Symbol Conditions Min. FIN tR tF tPWV tAPWD tDDJ tUJ tRESET Typ. Max. 21.504 MHz S1=0, S0=0 (See Fig. 1) 10.0 S1=0, S0=1 (See Fig. 1) 9.2 S1=1, S0=0 (See Fig. 1) 5.0 S1=1, S0=1 (See Fig. 1) 4.6 S1=0, S0=0 (See Fig. 1) 10.0 S1=0, S0=1 (See Fig. 1) 9.2 S1=1, S0=0 (See Fig. 1) 5.0 S1=1, S0=1 (See Fig. 1) 4.6 ns ns S1=0, S0=0 (See Fig. 2) 16.4 31.1 S1=0, S0=1 (See Fig. 2) 15.1 28.5 S1=1, S0=0 (See Fig. 2) 8.2 15.6 S1=1, S0=1 (See Fig. 2) 7.5 14.3 S1=0, S0=0 (See Fig. 2) -3.4 +7.0 S1=0, S0=1 (See Fig. 2) -3.1 +6.5 S1=1, S0=0 (See Fig. 2) -1.7 +3.5 S1=1, S0=1 (See Fig. 2) -1.6 +3.3 S1=0, S0=0 (See Fig. 3) 0 3.4 S1=0, S0=1 (See Fig. 3) 0 3.1 S1=1, S0=0 (See Fig. 3) 0 1.7 S1=1, S0=1 (See Fig. 3) 0 1.6 S1=0, S0=0 (See Fig. 4) 0 1000 S1=0, S0=1 (See Fig. 4) 0 920 S1=1, S0=0 (See Fig. 4) 0 500 S1=1, S0=1 (See Fig. 4) 0 460 (see Fig. 5) 50 7 Units ns ns ns ps ns IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Timing Diagrams 2UI + tPWV(MAX) 2UI + tPWV(MIN) tF tR 1UI + tPWV(MAX) VDD 90% of VDD 1UI + tPWV(MIN) tPWV(MAX) tPWV(MIN) tAPWD 10% of VDD 0V Signal tAPWD tAPWD VOH 1.5 V VOL 1UI 2UI (bit period) Figure 1: Rise and Fall Time Definitions 3UI (occurs at preambles) Figure 2: Pulse Width Variation and Average Pulse Width Distortion tDDJ node n tUJ Tx (node n-1) node n Trigger Tx (node n-1) Figure 3: Data Dependent Jitter Trigger Figure 4: Uncorrelated Jitter VDD RESET 1.5 V 1.5 V 0V tRESET Output VDDs 0.1µF RCLK DUT C LOAD 10pF RCLK locked to MOST data RCLK locked to MCLK RLOAD 2 kOhm GND Figure 6: Test and Measurement Setup Figure 5: RESET Timing Definition IDT™ MOST® CLOCK INTERFACE 8 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Power Up Time t1 PLL Locked VDD t2 VDD 1.5 V Clock Output VCO Ramp Time 0V 0V t Duty Cycle, D= 2 t1 VDD RCLK Figure 7: Duty Cycle Definitions 0V 0 ms tCLOCK tDLOCK Note: FOT_IN must be running and stable during VCO ramp time. FOT_IN 1.5 V Figure 8: Power Up and PLL Lock Timing tPD FOT_OUT 1.5 V FOT_IN t CDR Note: RESET = H, BYPASS = H, OEM = L or H RCLK Figure 9: Propagation Delay t SK t JIT INPUT_COPY RESET OEM Figure 10: Clock Timing FOT_IN data FOT_IN 0 MOST_Din data MOST_Din BYPASS 1.5 V tBHL FOT_OUT FOT_IN data VDD MOST Input (retimed) 0V Recovered Clock 1.5 V tBLH MOST_Din data 0 1 1 Coding Violation 0 1 FOT_IN data Figure 12: MOST Data–Clock Example Figure 11: BYPASS Timing Definition IDT™ MOST® CLOCK INTERFACE 9 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±10%, Ambient Temperature -40 to +85° C Parameter Crystal Frequency Symbol Output Rise Time Output Fall Time Min. FIN Output Frequency Error Output Clock Duty Cycle Conditions Due to frequency synthesis D tR tF Figures 6 and 7 45 Typ. Max. Units 21.504 MHz 0 ppm 50 55 S1=0, S0=0 (See Fig. 1) 5.0 S1=0, S0=1 (See Fig. 1) 4.6 S1=1, S0=0 (See Fig. 1) 2.5 S1=1, S0=1 (See Fig. 1) 2.3 S1=0, S0=0 (See Fig. 1) 5.0 S1=0, S0=1 (See Fig. 1) 4.6 S1=1, S0=0 (See Fig. 1) 2.5 S1=1, S0=1 (See Fig. 1) Output Pulse Width Variation (FOT_OUT) Average Output Pulse Width Distortion (FOT_OUT) One-Sigma Data dependent Jitter (RCLK) One-Sigma Uncorrelated Jitter (RCLK) Power-up Time tPWV tAPWD tDDJ tUJ % ns ns 2.3 S1=0, S0=0 (See Fig. 2) 21.2 23.1 S1=0, S0=1 (See Fig. 2) 19.5 21.2 S1=1, S0=0 (See Fig. 2) 10.6 11.5 S1=1, S0=1 (See Fig. 2) 9.8 10.6 S1=0, S0=0 (See Fig. 2) -500 +500 S1=0, S0=1 (See Fig. 2) -460 +460 S1=1, S0=0 (See Fig. 2) -250 +250 S1=1, S0=1 (See Fig. 2) -230 +230 S1=0, S0=0 (See Fig. 3) 0 220 S1=0, S0=1 (See Fig. 3) 0 200 S1=1, S0=0 (See Fig. 3) 0 110 S1=1, S0=1 (See Fig. 3) 0 100 S1=0, S0=0 (See Fig. 4) 0 95 S1=0, S0=1 (See Fig. 4) 0 90 S1=1, S0=0 (See Fig. 4) 0 45 S1=1, S0=1 (See Fig. 4) 0 ns ps ps ps 45 tCLOCK PLL lock-time from 90% VDD to RCLK = MCLK, (see Fig. 8) 200 µs tDLOCK PLL lock-time from beginning of FOT_IN input to stable RCLK output, (see Fig. 8) 400 µs tPD (see Fig. 9) 3 4 5 ns Propagation Delay (FOT_IN to RCLK) tCDR (see Fig. 10) TBD TBD TBD ns Skew, recovered clock to retimed input tSK (see Fig. 10) -250 0 +250 ps 50 ps Propagation Delay (FOT_IN to FOT_OUT) One-Sigma Clock Period Jitter IDT™ MOST® CLOCK INTERFACE MCLK 10 0 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE Parameter SYNTHESIZERS Symbol Conditions RCLK Peak-to-peak Jitter with respect to FOT_IN tJIT BYPASS High-to-Low to FOT_OUT tBHL (see Fig. 11) BYPASS Low-to-High to FOT_OUT tBLH (see Fig. 11) Min. Typ. -500 0 Max. Units +500 ps TBD TBD ns TBD TBD ns Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case IDT™ MOST® CLOCK INTERFACE Symbol Conditions Min. Typ. Max. Units θJA Still air 93 ° C/W θJA 1 m/s air flow 78 ° C/W θJA 3 m/s air flow 65 ° C/W 20 ° C/W θJC 11 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Marking Diagrams 20 11 IDT5V800 01PGGI ZYYWW$ 1 10 20 11 IDT5V800 01PGGIW3 ZYYWW$ 1 10 Notes: 1. “Z” is the device step (1 to 2 characters). 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “$” is the assembly mark code. 4. “G” after the two-letter package code designates RoHS compliant package. 5. “I” at the end of part number indicates industrial temperature range. 6. ‘W3’ denotes automotive grade. 7. Bottom marking: country of origin if not USA. IDT™ MOST® CLOCK INTERFACE 12 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Package Outline and Package Dimensions (20-pin TSSOP, 4.4mm Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Symbol E1 INDEX AREA A A1 A2 b C D E E1 e L α aaa E 1 2 D Max Min -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 *For reference only. Controlling dimensions in mm. A A2 Min Inches* A1 c - Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package 5V80001PGGI 5V80001PGGI8 5V80001PGGW3 5V80001PGGW38 see page 8 Tubes Tape and Reel Tubes Tape and Reel 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP see page 8 Temperature -40 to +85° -40 to +85° -40 to +85° -40 to +85° C C C C Parts that are ordered with a “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant. ‘W3’ denotes automotive grade. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ MOST® CLOCK INTERFACE 13 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Revision History Rev. Originator Date A J. Gazda 08/29/06 Preliminary datasheet. B J. Gazda 09/19/06 Changed block diagram and pinout; C J. Gazda 09/25/06 Changed from 16-pin TSSOP to 20-pin TSSOP; added timing diagrams; changed pinout and block diagrams. D J. Gazda 09/27/06 New block diagram; changed pinout; added Propagation Delay, Skew, and Clock Jitter specs; changed High/Low Input/Output level specs. E J. Gazda 11/02/06 Changed temperature rating from -40/+85 to -40/+105 °C; added “Mode” and “Sampling Frequency” to Frequency Selection Table. F J. Gazda 12/14/06 Added “Operation” section; added “External Loop Filter” diagram; added RESET# pin; various modifications to “External Components” text. G J. Gazda 02/15/07 Added Feature bullet of “5 V tolerant input for FOT”; add crystal caps and ground to block diagram; added “Weak pull-down when OEM=0” statement to MCLK pin description. H J. Gazda 03/22/07 Added NDK crystal part number; changed “MCLK” to “RCLK” in the conditions for “Data to clock jitter” spec. J J. Gazda 05/31/07 Removed CP reference on External Loop Filter descriptions; removed one capacitor from “CDR PLL” in Block Diagram. K J. Gazda 06/22/07 Reversed ’1’ and ‘0’ on the MUX in the block diagram; removed the bar from “BYPASS”; added the text “No pull-up” to pin descriptions 7, 9, 12, and 13; removed “Data to clock jitter” spec from AC char table. L J. Gazda 10/09/07 Removed “Lock” pin. M T. Nana 12/17/07 Updates to timing diagrams; added “Timing Requiremnets” table; updates to pin descriptions; multiple updates to AC/DC char tables; added Figure 7. N T. Nana 12/26/07 Updates to Block Diagram and Timing diagrams; added new “Operation” information; added another OEM table for BYPASS and FOT_OUT; updates to AC/DC char tables and “Timing Requirementts” table; added “Reset Timing Definition” (Fig. 8) and “BYPASS Timing Definition” (Fig. 9) diagrams. P T. Nana 01/08/08 Updates to DC Electrical Char table; One-Sigma Jitter specs added to “Timing Requirements” table; updates to Timing Diagrams; added jitter and propagation delay timing diagrams; added One-Sigma Jitter specs to AC Electrical Char table; Q T. Nana 02/06/08 Removed OEM and MUX from Block Diagram; updates to "Operation" text; updated "Propagation Delay" diagram; added additional “Propagation Delay” spec to AC char table. 11/14/08 Moved from Preliminary to Released. 08/31/09 Added automotive grade ordering info and marking diagram R S D.L. IDT™ MOST® CLOCK INTERFACE Description of Change 14 IDT5V80001 REV S 083109 IDT5V80001 MOST® CLOCK INTERFACE SYNTHESIZERS Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. www.idt.com © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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