Programmable LVCMOS/LVTTL
Clock Generator
IDT5V925BI
DATA SHEET
General Description
Features
The IDT5V925BI is a high-performance, low skew, low jitter
phase-locked loop (PLL) clock driver. It provides precise phase and
frequency alignment of its clock outputs to an externally applied
clock input or internal crystal oscillator. The IDT5V925BI has been
specially designed to interface with Gigabit Ethernet and Fast
Ethernet applications by providing a 125MHz clock from 25MHz
input. It can also be programmed to provide output frequencies
ranging from 3.125MHz to 160MHz with input frequencies ranging
from 3.125MHz to 80MHz.
•
•
•
•
•
•
•
3V to 3.6V operating voltage
The IDT5V925BI includes an internal RC filter that provides
excellent jitter characteristics and eliminates the need for external
components. When using the optional crystal input, the chip accepts
a 10-30MHz fundamental mode crystal with a maximum equivalent
series resistance of 50. The on-chip crystal oscillator includes the
feedback resistor and crystal capacitors (nominal load capacitance
is 18pF).
•
•
•
•
•
5V tolerant inputs
Low output skew/jitter
External PLL feedback, internal loop filter
3.125MHz to 160MHz output frequency range
Four programmable frequency LVCMOS/LVTTL outputs
Input from fundamental crystal oscillator or external source
Balanced drive outputs ±12mA
PLL disable mode for low frequency testing
Select inputs (S[1:0]) for divide selection (multiply ratio of 2, 3, 4,
5, 6, 7 and 8)
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Pin Assignment
Applications
•
•
•
•
•
S1
1
16
VDD
S0
2
15
GND
GNDQ
3
14
Q2
VDDQ
4
13
Q1
SAN
X1
5
12
Q0
Instrumentation
X2
6
11
Q/N
CLKIN
7
10
GND
FB
8
9
Ethernet/fast ethernet
Router
Network switches
OE
IDT5V925BI
16 LEAD QSOP
0.194” x 0.236” x 0.058” package body
Q Package
Top View
Block Diagram
S0
S1
SELECT
MODE
FB
PHASE
DETECTOR
CLKIN
LOOP
FILTER
VCO
0
1
VCO
DIVIDE
1/N
Q/N
Q0
X2
XTAL
OSC
Q1
X1
OPTIONAL
CRYSTAL
Q2
OE
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
1, 2
S1, S0
Input
3
GNDQ
Power
Ground supply for PLL.
4
VDDQ
Power
Power supply for PLL.
5
(1)
Input
Crystal oscillator input. Connected to GND if oscillator not required.
(1)
Output
6
X1
X2
Type
Pullup/
Pulldown
Description
Three level divider/mode select pins. Float to MID.
Crystal oscillator output. Leave unconnected for clock input.
7
CLKIN
Input
Clock input.
8
FB
Input
PLL feedback input which should be connected to Q/N output pin only. PLL locks
onto positive edge of FB signal.
9
OE
Input
High-Impedance output enable. When asserted HIGH, clock outputs are high
impedance.
10, 15
GND
Power
Ground supply for output buffers.
11
Q/N
Output
Programmable divide-by-N clock output.
12, 13, 14
Q0, Q1, Q2
Output
Output at N*CLKIN frequency.
16
VDD
Power
Power supply for output buffers.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
NOTE 1: For best accuracy, use parallel resonant crystal specified for a load capacitance of 18pF.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
Test Conditions
Minimum
Typical
Maximum
Units
CLKIN, FB, OE
4
pF
VDD = 3.6V
15
pF
Input Pullup Resistor
47
k
RPULLDOWN
Input Pulldown Resistor
47
k
ROUT
Output Impedance
16
IDT5V925BQGI REVISION C JANUARY 07, 2013
VDD = 3.3V±0.3V
2
©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Function Tables
Table 3A. Function Table
Allowable CLKIN Range (MHz) (1, 2)
Output Frequency Relationships
Output Used for Feedback
Minimum
Maximum
Q/N
Q[2:0]
Q/N
25/N
160/N
CLKIN
CLKIN x N
NOTE 1: Operation in the specified CLKIN frequency range guarantees that the VCO will operate in the optimal range of 25MHz to 160MHz.
Operation with CLKIN outside specified frequency ranges may result in invalid or out-of-lock outputs.
NOTE 2: Q[2:0] are not allowed to be used as feedback.
Table 3B. Divide Selection Table (1)
S1
S0
L
L
Divide-by-N Value
Mode
L
M
2
PLL
Factory Test (2)
L
H
3
PLL
M
L
4
PLL
M
M
5(3) (default)
PLL
M
H
6
PLL
H
L
7
PLL
H
M
8
PLL
H
H
16
TEST(4)
NOTE 1: H = HIGH, M = MEDIUM, L = LOW.
NOTE 2: Factory Test Mode: operation not specified.
NOTE 3: Ethernet mode (use a 25MHz input frequency and Q/N as feedback).
NOTE 4: Test mode for low frequency testing. In this mode, CLKIN bypasses the VCO (VCO powered down). Frequency must be > 1MHz due
to dynamic circuits in the frequency dividers. Q[2:0] outputs are divided by 2 in test mode.
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage to Ground, VTERM
-0.5V to +4.6V
DC Input Voltage, VIN
-0.5V to +4.6V
DC Output Voltage, VOUT
-0.5 to VDD +0.5V
Maximum Power Dissipation, TA = 85C
0.55W
Storage Temperature, TSTG
-65C to +150C
Package Thermal Impedance, JA
72.3C/W
Operating Conditions
Symbol
Description
Minimum
Typical
Maximum
Units
VDD / VDDQ
Power Supply Voltage
3.0
3.3
3.6
V
TA
Operating Temperature
-40
+25
+85
C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
IDDQ
Quiescent Supply Current
Static Supply Current
IDD
Dynamic Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
VDD = VDDQ = 3.6V; CLKIN = 2.5MHz;
S[1:0] = MM, OE = H,
All Outputs Unloaded
2
4
mA
VDD = VDDQ = 3.6V;
S[1:0] = MM, OE = H,
All Outputs Unloaded
83
102
mA
VDD = VDDQ = 3.6V, fOUT = 70MHz;
S[1:0] = LM, OE = GND,
All Outputs Loaded with 50 to GND
80
160
mA
NOTE: H = HIGH, M = MEDIUM, L = LOW
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VIL
Input Low Voltage
VIH
Input High Voltage
VIHH
Input High Voltage
S[1:0]
VIMM
Input Mid Voltage
VILL
IIN
(1)
(1)
Typical
I3
Units
0.8
V
2
V
3-Level Input Only
VDD - 0.6
V
S[1:0]
3-Level Input Only
VDD/2 - 0.3
Input Low Voltage
S[1:0]
3-Level Input Only
Input Leakage Current
CLKIN, FB
VIN = VDD or GND, VDD = Max.
-5
VIN = VDD, HIGH Level
(1)
Maximum
3-Level Input
DC Current
S[1:0]
VIN = VDD/2, MID Level
-50
VIN = GND, LOW Level
-200
VIN = VDD
-5
IIH
Input High Current
VOL
Output Low Voltage
IOL = 12mA
VOH
Output High Voltage
IOH = -12mA
2.4
VDD/2 + 0.3
V
0.6
V
+5
µA
200
µA
+50
µA
µA
0.07
±5
µA
0.15
0.55
V
2.8
V
NOTE: Conditions apply unless otherwise specified.
NOTE 1: These inputs are normally wired to VDD, GND, or unconnected. If the inputs are switched in real time, the function and timing of the
outputs may glitch, and the PLL may require an additional lock time before all the datasheet limits are achieved.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Maximum
Units
30
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7
pF
Mode of Oscillation
Typical
Fundamental
Frequency
10
NOTE: Characterized using an 18pF parallel resonant crystal.
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
AC Electrical Characteristics
Table 6A. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
tR / tF
Rise and Fall Time; NOTE 1
odc
Output Duty Cycle; NOTE 1, 2
tPD
Propagation Delay;
NOTE 1, 2
tsk(o)
Output-to-Output Skew;
NOTE 1, 3, 4
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
fOUT
Output Frequency
Minimum
Typical
Maximum
Units
0.7
1.8
ns
44
56
%
50
450
ps
Q[2:0]
110
ps
Q/N - Q[2:0]
450
ps
300
ps
160
MHz
0.8V to 2V
CLKIN to FB
25
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: JEDEC Standard 65.
NOTE 1: Guaranteed by design but not production tested.
NOTE 2: Measured from VDD/2 of the input crossing point to the output at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
Table 6B. Input Timing Requirements, TA = -40°C to 85°C
Symbol
Parameter
fosc
Crystal Oscillator Frequency
fIN
Input Frequency
IDT5V925BQGI REVISION C JANUARY 07, 2013
Test Conditions
6
Minimum
Maximum
Units
10
30
MHz
25/N
160/N
MHz
©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Parameter Measurement Information
1.65V ± 0.15V
SCOPE
VDD,
VDDQ
VDD
2
Qx
Qx
VDD
2
Qy
GND
tsk(b)
-1.65V ± 0.15V
LVCMOS Output Load AC Test Circuit
Output Skew
3V
2V
V
Q/N,
Q[2:0]
V
DD
V
DD
2
DD
2
VT H
2
/2
C /2
= VVCDD
0.8
➤
➤
tcycle n
➤
tcycle n+1
➤
0V
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
1ns
1ns
Cycle-to-Cycle Jitter
C
VVCDD
2V
VT H
C /2
= VVCDD
/2
0.8
VDD
2
CLKIN
0V
tR
VDD
2
Q/N,
Q[2:0]
t
tF
Input and Output Test Waveforms
PD
Propagation Delay
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Parameter Measurement Information, continued
V
DD
2
Q[2:0]
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLKIN Input
LVCMOS Outputs
For applications not requiring the use of a clock input, but using the
crystal interface, the CLKIN input has to be connected to X2 (output
of the crystal oscillator). See Figure 3.
All unused LVCMOS output can be left floating. There should be no
trace attached.
Crystal Inputs
For applications not requiring the use of the crystal oscillator, X2
should be left floating and X1 and should be tied to ground. See
Figure 2.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
How to Use the IDT5V925BI
The IDT5V925BI is a general-purpose phase-locked loop (PLL) that
can be used as a zero delay buffer or a clock multiplier. It generates
three outputs at the VCO frequency and one output at the VCO
frequency divided by n, where n is determined by the Mode/
Frequency Select input pins S0 and S1. The PLL will adjust the VCO
frequency (within the limits of the Function Table) to ensure that the
input frequency equals the Q/N frequency.
By connecting one of the 49FCT3505 outputs to the FB input of the
IDT5V925BI, the propagation delay from CLKIN to the output of the
49FCT3505 will be nearly zero. To ensure PLL stability, only one
49FCT3505 should be included between Q/N and FB.
The second way to drive the input of the IDT5V925BI is via an
external crystal. When connecting an external crystal to pins 5 and 6,
the X2 pin must be shorted to the CLKIN (pin 7) as shown in Figure
3. To reduce the parasitic between the external crystal and the
IDT5V925BI, it is recommended to connect the crystal as close as
possible to the X1 and X2 pins.
The IDT5V925BI can accept two types of input signals. The first is a
reference clock generated by another device on the board which
needs to be reproduced with a minimal delay between the incoming
clock and output. The second is an external crystal. When used in the
first mode, the crystal input (X1) should be tied to ground and the
crystal output (X2) should be left unconnected.
FB
By connecting Q/N to FB (see Figure 1), the IDT5V925BI not only
becomes a zero delay buffer, but also a clock multiplier. With proper
selection of S0 and S1, the Q0–Q2 outputs will generate two, three,
or up to eight times the input clock frequency. Make sure that the
input and output frequency specifications are not violated (refer to
Function Table). There are some applications where higher fan-out
is required. These kinds of applications could be addressed by using
the IDT5V925BI in conjunction with a clock buffer such as the
49FCT3805. Figure 2 shows how higher fan-out with different clock
rates can be generated.
CLKIN
5V925
Q /N
Q0
X2
XTAL
Q1
OSC
Q2
X1
S0
S1
Figure 3
One of the questions often asked is what is the accuracy of our clock
generators? In applications where clock synthesizers are used, the
terms frequency accuracy and frequency error are used
interchangeably. Here, frequency accuracy (or error) is based on two
factors. One is the input frequency and the other is the multiplication
factor. Clock multipliers (or synthesizers) are governed by the
equation:
FB
Q /N
CLKIN
Q0
5V925
X2
Q1
X1
Q2
M
FOUT = ----- FIN
N
S0
S1
Where “M” is the feedback divide and “N” is the reference divide. If
the ratio of M/N is not an integer, then the output frequency will not
be an exact multiple of the input. On the other hand, if the ratio is a
whole number, the output clock would be an exact multiple of the
input. In the case of IDT5V925BI, since the reference divide (“N”) is
“1”, the equation is a strong function of the feedback divide (“M”). In
addition, since the feedback is an integer, the output frequency error
(or accuracy) is merely a function of how accurate the input is. For
instance, IDT5V925BI could accept two forms of input, one from a
crystal oscillator (see Figure 1) and the other from a crystal (see
Figure 3). By using a 20MHz clock with a multiplication factor of 5
(with an accuracy of ±30 parts per million), one can easily have three
copies of 100MHz of clock with ±30ppm of accuracy. Frequency
accuracy is defined by the following equation:
Figure 1
FB
INA
Q/N
5 C O PIES
OF Q/N
CLKIN
5V925
49FC T3805
X2
X1
Q [2:0]
INB
5 C O PIES
OF Q
Accuracy = Measured Frequency – Nominal Frequency x 106
Nominary Frequency
S0
S1
Where measured frequency is the average frequency over certain
number of cycles (typically 10,000) and the nominal frequency is the
desired frequency.
Figure 2
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Schematic Examples
Figures 4A and 4B show an examples of IDT5V925BI application
schematic. In Figure 4A example, the device is operated at VDD =
VDDQ = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The
load capacitance, C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. Depending on the parasitics of the printed circuit
board layout, these values might require a slight adjustment to
optimize the frequency accuracy. Crystals with other load
capacitance specifications can be used. This will required adjusting
C1 and C2. In Figure 4B example, the LVCMOS clock reference input
is used.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The IDT5V925BI provides separate
power supplies to isolate from coupling into the internal PLL.
BLM18BB221SN1
VDD
3.3V
BLM18BB221SN2
1
C7
2
2
Ferrite Bead
C8
0.1uF
VDDQ
Ferrite Bead C5
C4
0.1uF
1
3.3V
C3
0.1uF
10uF
C6
R1
33
10uF 0.1uF
Zo = 50 Ohm
Q2
U1
S1
S2
XTAL_IN
XTAL_OUT
1
2
3
4
5
6
7
8
S1
S0
GNDQ
VDDQ
X1
X2
CLKIN
FB
VDD
GND
Q2
Q1
Q0
Q/N
GND
/OE
16
15
14
13
12
11
10
9
LVCMOS
VDD=3.3V
VDDQ=3.3V
Q1
Q0
R2
33
/OE
VDDQ
X1
R3
100
25MHz
F
p
8
1
C2
27pF
Zo = 50 Ohm
Q/N
C1
27pF
R4
100
LVCMOS
Please short the
CLKIN pin and X2
pin for the
crystal input
option.
Logic Control Input Examples
Set Logic
Input to
'1'
VDD
RU1
1K
Set Logic
Input to
'0'
VDD
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
Optional Termination
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
To Logic
Input
pins
RD2
1K
Figure 4A. IDT5V925BI Application Schematic with Crystal Input Reference
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Schematic Examples, continued
3.3V
BLM18BB221SN1
VDD
3.3V
BLM18BB221SN2
1
2
2
Ferrite Bead
C8
0.1uF
VDDQ
Ferrite Bead C5
C4
0.1uF
1
C7
C3
0.1uF
10uF
C6
R1
33
10uF 0.1uF
Zo = 50 Ohm
Q2
U1
S1
S2
1
2
3
4
5
6
7
8
S1
S0
GNDQ
VDDQ
X1
X2
CLKIN
FB
VDD
GND
Q2
Q1
Q0
Q/N
GND
/OE
16
15
14
13
12
11
10
9
LVCMOS
VDD=3.3V
VDDQ=3.3V
Q1
Q0
R2
33
/OE
VDDQ
R3
100
Zo = 50 Ohm
Q/N
R4
100
VDD
LVCMOS
Q1
Ro ~ 7 Ohm
R5
Zo = 50 Ohm
Logic Control Input Examples
Optional Termination
43
Driv er_LVCMOS
Set Logic
Input to
'1'
VDD
Set Logic
Input to
'0'
VDD
RU1
1K
RU2
Not Install
To Logic
Input
pins
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
To Logic
Input
pins
RD1
Not Install
RD2
1K
Figure 4B. IDT5V925BI Application Schematic with LVCMOS Reference Clock Input
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT5V925BI.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT5V925BI is the sum of the core power plus the power dissipation in the load(s). The following is the power
dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
The maximum current at 85°C is as follows:
IDD_MAX(Static) = 102mA
IDDQ_MAX = 4mA
CL = 5pF
N = number of outputs
CPD = 15pF
Core Output Power Dissipation
•
Power (core)MAX = VDD_MAX * (IDD _MAX(Static) + IDDQ_MAX) = 3.6V *(102mA + 4mA) = 382mW
LVCMOS Output Power Dissipation
•
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 16)] = 27.3mA
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 16 * (27.3mA)2 = 11.9mW per output
•
Total Power Dissipation on the ROUT
Total Power (ROUT) = 11.9mW * 3 = 35.7mW
Dynamic Power Dissipation
•
Dynamic Power Dissipation at 160MHz
Total Power (160MHz) = [(CPD + CL) * N) * Frequency * (VDD)2] = [(15pF + 5pF) * 3) * 160MHz * (3.6V)2] = 124.4mW
Total Power Dissipation
•
Total Power
= Power (core) + Total Power (ROUT) + Total Power (160MHz)
= 382mW + 35.7mW + 124.4mW
= 542mW
IDT5V925BQGI REVISION C JANUARY 07, 2013
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©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 72.3°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.542W * 72.3°C/W = 124.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 16-lead QSOP, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT5V925BQGI REVISION C JANUARY 07, 2013
0
1
2.5
72.3°C/W
64.4°C/W
60.0°C/W
13
©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Reliability Information
Table 8. JA vs. Air Flow Table for a Q Suffix, 16-lead QSOP
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT5V925BQGI REVISION C JANUARY 07, 2013
0
1
2.5
72.3°C/W
64.4°C/W
60.0°C/W
14
©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Package Outline and Package Dimensions
Package Outline - Q Suffix for 16 Lead QSOP
Table 9. Package Dimensions
Symbol
N
A
A1
A2
D
E
E1
P
P1
P2
e
x
JEDEC Variation: AB
All Dimensions in Inches
Minimum
Nominal
16
0.061
0.064
0.004
0.006
0.055
0.058
0.189
0.194
0.230
0.236
0.150
0.155
0.274
0.142
0.175 Basic
0.025 Basic
0.010
Maximum
.068
0.010
0.061
0.196
0.244
0.157
0.282
0.150
0.018
Ref. Document: IDT PC/PCG Package Outline, Dwg# PSC-4040
IDT5V925BQGI REVISION C JANUARY 07, 2013
15
©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Ordering Information
Table 10. Ordering Information
Part/Order Number
5V925BQGI
5V925BQGI8
Marking
IDT5V925BQGI
IDT5V925BQGI
Package
“Lead-Free” 16 Lead QSOP
“Lead-Free” 16 Lead QSOP
Shipping Packaging
Tube
3000 Tape & Reel
Temperature
-40C to 85C
-40C to 85C
NOTE: Parts that are ordered with an "G" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
IDT5V925BQGI REVISION C JANUARY 07, 2013
16
©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
Revision History Sheet
Rev
Table
B
C
10
Page
Description of Change
Date
8
10
Applications for Unused I/O Pins application note - corrected Input descriptions.
Deleted Overdriving the XTAL Interface application note.
1/21/11
16
Removed leaded parts from ordering information table
01/07/13
IDT5V925BQGI REVISION C JANUARY 07, 2013
17
©2013 Integrated Device Technology, Inc.
IDT5V925BI Data Sheet
PROGRAMMABLE LVCMOS/LVTTL CLOCK GENERATOR
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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