601G-21LF

DATASHEET ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER Description Features The ICS601-21 is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT’s lowest phase noise multiplier. Using IDT’s patented analog and digital Phase Locked Loop (PLL) techniques, the chip accepts a crystal or clock input, and produces output clocks up to 230 MHz at 3.3 V. • Fully integrated PLL, no external loop filter required • Differential 3.3 V LVPECL outputs • Uses fundamental crystal or clock This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined nor guaranteed. • • • • • • • • — Crystal input frequency: 10 to 27MHz — Clock input: 10 to 38MHz (mulitply by 6) 10 to 31MHz (all other multiply settings) Output clocks up to 230 MHz at 3.3 V Low phase noise: -122 dBc/Hz at 10 kHz Low jitter - 15 ps one sigma typ. Powerdown mode lowers power consumption Packaged in 16-pin TSSOP, Pb-free Advanced, low power, sub-micron CMOS process Operating voltage of 3.3 V Commercial temperature range available Block Diagram VDD Reference Divider Loop Filter Charge Pump Phase Comparator VCO CLK nCLK X1/ICLK Crystal or clock input VCO Divide Crystal Oscillator X2 ROM Based Multipliers 4 S2:0 IDT® LOW PHASE NOISE CLOCK MULTIPLIER GND 1 ICS601-21 REV J 121412 ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER Pin Assignment Multiplier Select Table X1 1 16 X2 VD D 2 15 GND VD D 3 14 C LK VD D 4 13 nC LK GND 5 12 VD D VD D 6 11 S0 GND 7 10 S1 GND 8 9 S2 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Multiplier x1 x2 x3 x4 x5 x6 x8 x16 16 Pin (173 m il) TSSOP 0 = connect directly to ground 1 = connect directly to VDD Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 X1 XI Crystal or clock input. Connect to a fundamental parallel mode crystal or clock input. See electrical tables for input frequenct ranges. 2-4 VDD Power Connect to +3.3 V. 5 GND Power Connect to ground. 6 VDD Power Connect to +3.3 V. 7-8 GND Power Connect to ground. 9 S2 Input Select pin 2. Internal pull-up resistor. 10 S1 Input Select pin 1. Internal pull-up resistor. 11 S0 Input Select pin 0. Internal pull-up resistor. 12 VDD Power Connect to +3.3 V. 13 nCLK Output Inverted differential clock output. 14 CLK Output Differential clock output. 15 GND Power Connect to ground. 16 X2 XO IDT® LOW PHASE NOISE CLOCK MULTIPLIER Crystal connection. Connect to a fundamental parallel mode crystal or leave unconnected for clock input. See electrical tables for input frequenct ranges. 2 ICS601-21 REV J 121412 ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER External Components The ICS601-21 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01F and 0.1 F should be connected between VDD and GND, as close to the part as possible. A 50  terminating resistor should be used on each clock output. (See termination diagram on page 5). The crystal must be connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground and X2 to ground. In general, the value of these capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF caps can be used. For any given board layout, IDT can measure the board capacitance and recommend the exact capacitance value to use. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS601-21. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature, Commercial version 0 to +70 C Storage Temperature -65 to +150 C Junction Temperature 125 C Soldering Temperature 260 C Recommended Operation Conditions Parameter Min. Max. Units 0 +70 C +3.0 +3.6 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. DC Electrical Characteristics VDD=3.3 V ±0.3V, Ambient temperature 0 to +70C Parameter Symbol Conditions Operating Voltage VDD Input High Voltage VIH X1/ICLK pin only Input Low Voltage VIL X1/ICLK pin only IDT® LOW PHASE NOISE CLOCK MULTIPLIER Min. 3.0 3 Typ. Max. Units 3.6 V VDD/2+1 V VDD/2-1 ICS601-21 V REV J 121412 ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER DC Electrical Characteristics (continued) Parameter Symbol Conditions Min. Typ. Units VDD V 0.8 V Input High Voltage VIH Input select pins Input Low Voltage VIL Input select pins Output High Voltage VOH Note 1 VDD-1.4 VDD-1.0 V Output Low Voltage VOL Note 1 VDD-2.0 VDD-1.7 V 0.6 0.95 V 45 mA Output Voltage Swing Vswing 2 Max. Peak to Peak Operating Supply Current IDD Note 1, 125 MHz 30 Input Capacitance CIN Input select pins 5 pF On Chip Pull-up Resistor RPU Input select pins 510 k Note 1: Outputs terminated with 50 to VDD-2V AC Electrical Characteristics VDD = 3.3 V ±0.3V, Ambient Temperature 0 to +70 C Parameter Symbol Conditions Min. Typ. Max. Units Crystal Input Frequency Fin Note 2 10 27 MHz Clock Input Frequency Fin Note 2, “Multiply by 6” setting 10 38 MHz Note 2, excluding “Multiply by 6” setting 10 31 MHz 10 230 MHz Output Frequency Output Rise Time tOR 20% to 80%, no load 600 900 ps Output Fall Time tOF 80% to 20%, no load 900 1200 ps 50 55 % Output Clock Duty Cycle at VDD/2 45 Maximum Absolute Jitter, short term, 125 MHz No load ±50 ±75 ps Maximum Jitter, one sigma, 125 MHz (x5) No load 12 20 ps Phase Noise, relative to carrier, 125 MHz (x5) 100 Hz offset -90 -94 dBc/Hz Phase Noise, relative to carrier, 125 MHz (x5) 1 kHz -116 -120 dBc/Hz Phase Noise, relative to carrier, 125 MHz (x5) 10 kHz offset -118 -122 dBc/Hz Phase Noise, relative to carrier, 125 MHz (x5) 100 kHz offset -115 -119 dBc/Hz Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x, maximum input frequency is 13.75 MHz). IDT® LOW PHASE NOISE CLOCK MULTIPLIER 4 ICS601-21 REV J 121412 ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER Parameter Measurement Information V D D = 3.3V V D D = 3.3V Z = 50  SCOPE Z = 50  Qx Qx 50  LV P E C L LV P E C L Z = 50  Z = 50  nQ x 50  nQ x 50  50  G N D =0V G N D =0V V D D-2V = 1.3V 3.3V O utput Load A C Test C ircuit 3.3V LV P E C L D river Term ination VOH nFOUT VREF VOL FOUT Reference Point tcycle(n) tcycle(n+1) HISTOGRAM Mean Period (First edge after trigger) tjit(cc) = tcycle(n) - tcycle(n+1) 1s contains 68.26% of all measurements 2s contains 95.4% of all measurements 3s contains 99.73% of all measurements 4s contains 99.99366% of all measurements 6s contains (100-1.973x10-7)% of all measurements 1000 Cycles Period Jitter CYCLE-TO-CYCLE JITTER nFOUT 80% 80% VSWING FOUT Clock Outputs Pulse Width tPERIOD ODC = 20% 20% tOR tPW tOF tPERIOD OUTPUT DUTY CYCLE AND tPERIOD IDT® LOW PHASE NOISE CLOCK MULTIPLIER OUTPUT RISE/FALL TIME 5 ICS601-21 REV J 121412 ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 E INDEX AREA 1 2 D Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 *For reference only. Controlling dimensions in mm. A A2 Min A A1 A2 b C D E E1 e L  aaa Inches* A1 c -Ce b SEATING PLANE  L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 601G-21LF 601G-21LFT 601G-21LF 601G-21LF Tubes Tape and Reel 16-pin TSSOP 16-pin TSSOP 0 to +70 C 0 to +70 C "LF" suffix to the part number denotes Pb-Free configuration, RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. IDT® LOW PHASE NOISE CLOCK MULTIPLIER 6 ICS601-21 REV J 121412 ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER Revision History Rev. Date Originator J 12/14/12 A. Tsui Description of Change 1. Updated Clock Input and Output frequencies in AC Char table and on front page of DS per characterization report. 2. Removed leaded parts from Orderables table. IDT® LOW PHASE NOISE CLOCK MULTIPLIER 7 ICS601-21 REV J 121412 ICS601-21 LOW PHASE NOISE CLOCK MULTIPLIER CLOCK MULTIPLIER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 www.idt.com/go/clockhelp Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States © 2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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