DATASHEET
ICS650-07C
NETWORKING CLOCK SOURCE
Description
Features
The ICS650-07C is a low cost, low jitter, high performance
clock synthesizer for networking applications. Using analog
Phase-Locked Loop (PLL) techniques, the device accepts a
12.5 MHz or 25.00 MHz clock or fundamental mode crystal
input to produce multiple output clocks for networking chips,
PCI devices, SDRAM, and ASICs. The ICS650-07C outputs
all have 0 ppm synthesis error.
• Packaged in 20-pin tiny SSOP (QSOP)
• Pb (lead) free package
• 12.5 MHz or 25.00 MHz fundamental crystal or clock
input
•
•
•
•
•
•
See the MK74CB214, ICS551, and ICS552-01 for non-PLL
buffer devices which produce multiple low-skew copies of
these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay buffers
that can synchronize outputs and other needed clocks.
Six output clocks with selectable frequencies
SDRAM frequencies of 67, 83, 100, and 133 MHz
Buffered crystal reference output
Zero ppm synthesis error in all clocks
Ideal for PMC-Sierra’s ATM switch chips
Full CMOS output swing with 25 mA output drive
capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 3.0 V to 5.5 V operating voltage
Block Diagram
VDD
2
CLKA1
CLKA2
/2
ACS1, 0
BCS1, 0
2
Clock
Synthesis
and Control
Circuitry
2
CCS
CLKB1
CLKB2
/2
CLKC1
12.5 MHz or 25.00 MHz
Crystal or Clock
X1/ICLK
X2
CLKC2
Clock
Buffer/
Crystal
Oscillator
REFOUT
2
Optional crystal capacitors are shown and
may be required for tuning of initial accuracy
IDT™ / ICS™ NETWORKING CLOCK SOURCE
GND
1
OE (all outputs)
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
ACS0
1
20
BCS1
X2
2
19
BCS0
X1/ICLK
3
18
REFOUT
VDD
4
17
CLKA1
ACS1
5
16
VDD
GND
6
15
OE
CLKC1
7
14
GND
CLKC2
8
13
CLKA2
CLKB2
9
12
DC
CLKB1
10
11
CCS
20 pin (150 mil) SSOP
Pin Descriptions
Pin
Name
Pin Type
Description
1
ACS0
2
X2
XO
Crystal connection. Connect to a crystal or leave unconnected for clock input.
3
X1/ICLK
XI
Crystal connection. Connect to fundamental crystal or clock input.
4
VDD
Power
Connect to 3.3 V or 5 V. Must be same value as other VDD.
5
ACS1
Input
A clock select 1. Selects outputs on CLKA1 and CLKA2. Internal pull-up
resistor. See table below.
6
GND
Power
Connect to ground.
7
CLKC1
Output
Clock C output 1. Depends on setting of CCS per table below.
8
CLKC2
Output
Clock C output 2. Depends on setting of CCS per table below. Same as CLKC1.
9
CLKB2
Output
Clock B output 2. Depends on setting of BCS1, 0 per table below.
10
CLKB1
Output
Clock B output 1. Depends on setting of BCS1, 0 per table below.
11
CCS
12
DC
—
13
CLKA2
Output
Clock A output 2. Depends on setting of ACS1, 0 per table below.
14
GND
Power
Connect to ground.
15
OE
Input
Output enable. Tri-states all outputs when low. Internal pull-up resistor.
16
VDD
Power
Connect to VDD. Must be same value as other VDD.
17
CLKA1
Output
Clock A output 1. Depends on setting of ACS1, 0 per table below.
18
REFOUT
Output
Buffered reference clock output. Same frequency as crystal or clock input.
19
BCS0
20
BCS1
Tri-level Input A clock select 0. Selects outputs on CLKA1 and CLKA2. See table below.
Tri-level Input Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table below.
Don’t Connect. Do not connect anything to this pin.
Tri-level Input B clock select 0. Selects outputs on CLKB1 and CLKB2. See table below.
Input
B clock select 1. Selects outputs on CLKB1 and CLKB2. See table below.
IDT™ / ICS™ NETWORKING CLOCK SOURCE
2
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
For a 25 MHz Fundamental Crystal or Clock Input, use the following tables:
B Clocks Select Table (MHz)
A Clocks Select Table (MHz)
ACS1
ACS0
CLKA1
CLKA2
BCS1
BCS0
CLKB1
CLKB2
0
0
100
OFF (low)
0
0
TEST
TEST
0
M
TEST
TEST
0
M
66.6667
33.3333
0
1
75
OFF (low)
0
1
100
50
1
0
33.3333
16.6667
1
0
83.3333
41.6667
1
M
TEST
TEST
1
M
TEST
TEST
1
1
66.6667
33.3333
1
1
133.3333
66.6667
C Clocks Select Table (MHz)
CCS
CLKC1
CLKC2
0
125
125
M
TEST
TEST
1
75
75
REFOUT = 25 MHz
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (automatically self biases to VDD/2)
IDT™ / ICS™ NETWORKING CLOCK SOURCE
3
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
For a 12.5 MHz Crystal or Clock Input, use the following tables:
B Clocks Select Table (MHz)
A Clocks Select Table (MHz)
ACS1
ACS0
CLKA1
CLKA2
BCS1
BCS0
CLKB1
CLKB2
0
0
50
OFF (low)
0
0
TEST
TEST
0
M
TEST
TEST
0
M
33.3333
16.6667
0
1
37.5
OFF (low)
0
1
50
25
1
0
16.6667
8.3333
1
0
41.66667
20.8333
1
M
TEST
TEST
1
M
TEST
TEST
1
1
33.3333
16.6667
1
1
66.6667
33.3333
C Clocks Select Table (MHz)
CCS
CLKC1
CLKC2
0
62.5
62.5
M
TEST
TEST
1
37.5
37.5
REFOUT = 12.5 MHz
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (automatically self biases to VDD/2)
IDT™ / ICS™ NETWORKING CLOCK SOURCE
4
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
External Components
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
The ICS650-07C requires a minimum number of external
components for proper operation.
Crystal Information
Decoupling Capacitor
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (CL - 6) x 2
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
In the equation, CL is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 20 pF capacitors
should be used. If a clock input is used, drive it into X1 and
leave X2 unconnected.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-07C. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70° C
Ambient Operating Temperature (industrial)
-40 to +85° C
Storage Temperature
-65 to +150° C
Junction Temperature
125° C
Soldering Temperature (20 seconds max)
260° C
Recommended Operation Conditions
Parameter
Min.
Max.
Units
0
+70
°C
Ambient Operating Temperature (industrial)
-40
+85
°C
Power Supply Voltage (measured with respect to GND)
+3.0
+5.5
V
Ambient Operating Temperature (commercial)
IDT™ / ICS™ NETWORKING CLOCK SOURCE
5
Typ.
+3.3
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 5 V
Parameter
Symbol
Conditions
Min.
Typ.
3.0
Max.
Units
5.5
V
Operating Voltage
VDD
Supply Current
IDD
No load
Input High Voltage
VIH
X1 pin only, Clock input
Input Low Voltage
VIL
X1 pin only, Clock input
Input High Voltage
VIH
All tri-level inputs
Input Low Voltage
VIL
All tri-level inputs
Input High Voltage
VIH
Other inputs, except
tri-level
Input Low Voltage
VIL
Other inputs, except
tri-level
Output High Voltage
VOH
IOH = -25 mA
2.4
V
Output High Voltage
VOH
IOH = -8 mA
VDD-0.4
V
Output Low Voltage
VOL
IOL = 25 mA
Short Circuit Current
IOS
Each output
±100
mA
ACS1, BCS1, OE
200
kΩ
Internal Pull-up Resistor
VDD/2+1
60
mA
VDD/2
V
VDD/2
VDD/2-1
V
VDD-0.5
V
0.5
V
2
V
0.8
V
0.4
V
AC Electrical Characteristics
Unless stated otherwise, VDD = 5 V
Parameter
Symbol
Conditions
Input Frequency
Frequency Error
Min.
Typ.
10
12.5 or 25
All clocks
Max. Units
27
MHz
0
ppm
Output Rise Time
tOR
0.8 to 2.0 V
1.5
ns
Output Fall Time
tOF
2.0 to 0.8 V
1.5
ns
60
%
Output Clock Duty Cycle
At VDD/2
Absolute Jitter, short term
Variation from mean
IDT™ / ICS™ NETWORKING CLOCK SOURCE
6
40
50
150
ps
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Thermal Characteristics
Parameter
Symbol
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Conditions
Max. Units
Still air
135
° C/W
θ JA
1 m/s air flow
93
° C/W
θ JA
3 m/s air flow
78
° C/W
60
° C/W
θ JC
Marking Diagram—ICS650R-07ILF
11
20
650R-07LF
######
YYWW
1
Typ.
θ JA
Marking Diagram—ICS650R-07LF
20
Min.
11
650R-07ILF
######
YYWW
10
1
10
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” denotes Pb (lead) free package.
4. “I” denotes industrial grade device.
5. Bottom marking: (origin) = country of origin if not USA.
IDT™ / ICS™ NETWORKING CLOCK SOURCE
7
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
20
Millimeters
Symbol
E1
A
A1
A2
b
c
D
E
E1
e
L
α
E
INDEX
AREA
1 2
D
A
2
Min
Inches*
Max
Min
1.35
1.75
0.10
0.25
-1.50
0.20
0.30
0.18
0.25
8.55
8.75
5.80
6.20
3.80
4.00
.635 Basic
0.40
1.27
0°
8°
Max
0.053
0.069
0.004
0.010
-0.059
0.008
0.012
0.007
0.010
0.337
0.344
0.228
0.244
0.150
0.157
.025 Basic
0.016
0.050
0°
8°
*For reference only. Controlling dimensions in mm.
A
A
1
c
-Ce
b
SEATING
PLANE
L
.10 (.004)
C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
650R-07LF
650R-07LFT
650R-07ILF
650R-07ILFT
see page 7
Tubes
Tape and Reel
Tubes
Tape and Reel
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility
for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses
are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range,
high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to
change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ NETWORKING CLOCK SOURCE
8
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
www.idt.com/go/clockhelp
Corporate Headquarters
Integrated Device Technology, Inc.
www.idt.com
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.