DATASHEET
6P41302
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Description
Features
The 6P41302 is an 8-output very low power clock generator
for PCIe Gen1-2-3 applications with integrated output
terminations providing Zo = 100. The device has 8 output
enables for clock management and supports 2 different
spread spectrum levels in addition to spread off.
• Integrated terminations provide 100 differential Zo;
Typical Applications
•
•
PCIe Gen1–3 Clock Generator for Freescale designs
Output Features
•
• 8 0.7V low-power HCSL-compatible (LP-HCSL) DIF
•
pairs with Zo = 100
1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
•
•
•
•
•
•
•
•
•
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF phase jitter is PCIe Gen1–3 compliant
REF phase jitter is < 1.5ps RMS
•
•
•
•
•
reduced component count and board space
1.8V operation; reduced power consumption
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 6 x 6 mm 48-VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Block Diagram
vOE(7:0)#
8
REF1.8
XIN/CLKIN_25
X2
OSC
DIF7
DIF6
DIF5
SS Capable PLL
DIF4
DIF3
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
DIF2
CONTROL
LOGIC
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
DIF1
DIF0
1
6P41302
JANUARY 24, 2018
6P41302
8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
vOE5#
VDD1.8
VDDIO
GND
DIF6
DIF6#
vOE6#
DIF7
DIF7#
vOE7#
VDDIO
^CKPWRGD_PD#
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri
GNDXTAL
X1_25
X2
VDDXTAL1.8
VDDREF1.8
vSADR/REF1.8
GNDREF
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
6P41302
DIF5#
DIF5
vOE4#
DIF4#
DIF4
VDDIO
VDDA1.8
GNDA
vOE3#
DIF3#
DIF3
vOE2#
DIF2#
DIF2
GND
VDDIO
DIF1#
VDD1.8
DIF1
vOE1#
DIF0#
DIF0
vOE0#
VDDIO
13 14 15 16 17 18 19 20 21 22 23 24
48-VFQFPN, 6 x 6 mm, 0.4mm pitch
vv prefix indicates internal 60kOhm pull-down resistor
v prefix indicates internal 120kOhm pull-down resistor
^ prefix indicates internal 120kOhm pull-up resistor
Pins 5, 6 and 12 are the Suspend voltage rails.
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+
Read/Write Bit
x
x
Power Management Table
SMBus
DIFx
REF
OEx#
True O/P
Comp. O/P
OE bit
0
X
X
Low
Low
Hi-Z1
1
1
0
Running
Running Running
1
0
1
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
CKPWRGD_PD#
Power Connections
Pin Number
VDD
5
6
VDDIO
12
20,38
30
GND
2
8
9
13,21,31,39,
47
Description
XTAL OSC
REF Power
Digital (dirty)
Power
22,29,40
DIF outputs
29
PLL Analog
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Pin Descriptions
PIN #
PIN NAME
1
vSS_EN_tri
2
3
4
5
6
GNDXTAL
X1_25
X2
VDDXTAL1.8
VDDREF1.8
7
vSADR/REF1.8
TYPE
LATCHED
IN
GND
IN
OUT
PWR
PWR
LATCHED
I/O
GND
GND
IN
I/O
PWR
PWR
8
9
10
11
12
13
GNDREF
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
14
vOE0#
IN
15
16
DIF0
DIF0#
OUT
OUT
17
vOE1#
IN
18
19
20
21
22
23
24
DIF1
DIF1#
VDD1.8
VDDIO
GND
DIF2
DIF2#
OUT
OUT
PWR
PWR
GND
OUT
OUT
25
vOE2#
IN
26
27
DIF3
DIF3#
OUT
OUT
28
vOE3#
IN
29
30
31
32
33
GNDA
VDDA1.8
VDDIO
DIF4
DIF4#
34
vOE4#
IN
35
36
DIF5
DIF5#
OUT
OUT
37
vOE5#
IN
38
39
VDD1.8
VDDIO
PWR
PWR
GND
PWR
PWR
OUT
OUT
DESCRIPTION
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND for XTAL
Crystal input, Nominally 25.00MHz.
Crystal output.
Power supply for XTAL, nominal 1.8V
VDD for REF output. nominal 1.8V.
Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin
Ground pin for the REF outputs.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.8V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 1.8V
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
1.8V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 1.8V
Power supply for differential outputs
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Pin Descriptions (cont.)
PIN #
PIN NAME
40 GND
41 DIF6
42 DIF6#
TYPE
GND
OUT
OUT
43
vOE6#
IN
44
45
DIF7
DIF7#
OUT
OUT
46
vOE7#
IN
47
VDDIO
PWR
48
^CKPWRGD_PD#
IN
DESCRIPTION
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
Rs
2pF
Device
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
3.3V
Driving LVDS
Cc
R7a
R7b
R8a
R8b
Rs
Zo
Cc
Rs
Device
LVDS Clock
input
Driving LVDS inputs with the 6P41302
Value
Receiver has Receiver does not
Component
termination
have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 6P41302. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
1.8V Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
VDDxx
VIN
VIHSMB
Ts
Tj
ESD prot
Applies to VDD, VDDA and VDDIO
MIN
-0.5
-0.5
TYP
SMBus clock and data pins
-65
Human Body Model
UNITS NOTES
MAX
2.5
VDD+0.5V
3.6V
150
125
V
V
V
°C
°C
V
2000
1,2
1, 3
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Operating Supply
Current
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
1
2
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
I DDAOP
VDDA, All outputs active @100MHz
6
9
mA
I DDOP
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
12
16
mA
I DDIOOP
VDDIO, All outputs active @100MHz
28
35
mA
I DDAPD
VDDA, DIF outputs off, REF output running
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
VDDIO, DIF outputs off, REF output running
VDDA, all outputs off
All VDD, except VDDA and VDDIO, all outputs off
VDDIO, all outputs off
0.4
1
mA
2
5.3
8
mA
2
0.04
0.4
0.6
0.0005
0.1
1
1
0.1
mA
mA
mA
mA
2
I DDPD
I DDIOPD
I DDAPD
I DDPD
I DDIOPD
Guaranteed by design and characterization, not 100% tested in production.
This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Duty Cycle
Skew, Output to
Output
t DC
Measured differentially, PLL Mode
45
50
55
%
1,2
t sk3
Averaging on, VT = 50%
43
50
ps
1,2
14
50
ps
1,2
Jitter, Cycle to cycle
1
2
t jcyc-cyc
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform.
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Supply Voltage
VDDxx
Output Supply Voltage
VDDIO
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
TAMB
VIH
VIM
VIL
VIH
VIL
I IN
I INP
Fin
Lpin
CIN
COUT
Clk Stabilization
TSTAB
SS Modulation Frequency
f MOD
OE# Latency
tLATOE#
Tdrive_PD#
tDRVPD
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
I PULLUP
VDDSMB
tRSMB
t FSMB
f MAXSMB
CONDITIONS
Supply voltage for core, analog and single-ended
LVCMOS outputs
Supply voltage for differential Low Power Outputs
Commercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended outputs, except SMBus. I OH = -2mA
Single-ended outputs, except SMBus. IOL = -2mA
Single-ended inputs, VIN = GND, VIN = VDD
MIN
TYP
MAX
UNITS NOTES
1.7
1.8
1.9
0.9975
1.05-1.8
1.9
V
0
-40
0.75 VDD
0.4 VDD
-0.3
VDD-0.45
25
25
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
V
-5
0.45
5
°C
°C
V
V
V
V
V
uA
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
XTAL, or X1 input
23
Logic Inputs, except DIF_IN
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ I PULLUP
@ VOL
1.5
27
7
5
6
MHz
nH
pF
pF
1
1
1
0.6
1.8
ms
1,2
30
31.6
33
kHz
1
1
3
3
clocks
1,3
20
300
us
1,3
5
5
0.6
3.6
0.4
2
2
1
0.5 VDD
25
(Max VIL - 0.15V) to (Min VIH + 0.15V)
(Min VIH + 0.15V) to (Max VIL - 0.15V)
3.6
1000
300
ns
ns
V
V
V
mA
V
ns
ns
Maximum SMBus operating frequency
400
kHz
2.1
4
1.7
4
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are > 200 mV.
4
For VDDSMB < 3.3V, VIHSMB > = 0.65 x VDDSMB.
2
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Electrical Characteristics–DIF Low Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
Slew rate
Trf
Slew rate matching
ΔTrf
Voltage High
VHIGH
CONDITIONS
MIN
TYP
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
1.6
1.3
2.3
1.9
7
3.5
2.9
20
660
784
850
Voltage Low
VLOW
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Vcross_abs
Δ-Vcross
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
MAX UNITS NOTES
V/ns
V/ns
%
1,2,3
1,2,3
1,2,4
7
mV
-150
-33
150
816
-42
1634
427
12
1150
-300
300
250
550
140
7
mV
mV
mV
mV
7
7
1,2,7
1,5,7
1,6,7
1
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform.
2
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7
At default SMBus amplitude settings.
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common
Clocked (CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SYMBOL
PARAMETER
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
tjphPCIeG2-CC
PCIe Gen 2 High Band
Phase Jitter,
1.5MHz
< f < Nyquist (50MHz)
PLL Mode
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 3
tjphPCIeG3-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
PCIe Gen 4
tjphPCIeG4-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
Notes on PCIe Filtered Phase Jitter Table
1
Applies to all differential outputs, guaranteed by design and characterization.
2
Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.
tjphPCIeG1-CC
3
Specification
UNITS NOTES
Limit
86
ps (p-p) 1, 2, 3
MIN
TYP
MAX
21
25
35
0.9
0.9
1.1
3
ps
(rms)
1, 2
1.5
1.6
1.9
3.1
ps
(rms)
1, 2
0.3
0.37
0.44
1
0.3
0.37
0.44
0.5
ps
(rms)
ps
(rms)
1, 2
1, 2
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12.
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
Electrical Characteristics–REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
ppm
see Tperiod min-max values
Long Accuracy
Clock period
Tperiod
25MHz output
Rise/Fall Slew Rate
t rf1
Byte 3 = 1F, 20% to 80% of VDDREF
0.6
Byte 3 = 5F, 20% to 80% of VDDREF
0.9
Rise/Fall Slew Rate
t rf1
Byte 3 = 9F, 20% to 80% of VDDREF
1.1
Rise/Fall Slew Rate
t rf1
Byte 3 = DF, 20% to 80% of VDDREF
1.1
Rise/Fall Slew Rate
t rf1
VT = VDD/2 V
45
Duty Cycle
dt1X
Duty Cycle Distortion
dtcd
VT = VDD/2 V
0
VT = VDD/2 V
Jitter, cycle to cycle
tjcyc-cyc
1kHz offset
Noise floor
t jdBc1k
10kHz offset to Nyquist
Noise floor
t jdBc10k
Jitter, phase
t jphREF
12kHz to 5MHz
TYP
0
40
1
1.4
1.7
1.8
49.1
2
19.1
-129.8
-143.6
MAX
0.63
1.5
1.6
2.2
2.7
2.9
55
4
250
-105
-115
UNITS
ppm
ns
V/ns
V/ns
V/ns
V/ns
%
%
ps
dBc
dBc
ps
(rms)
Notes
1,2
2
1
1,3
1
1
1,4
1,5
1,4
1,4
1,4
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00MHz.
3
Default SMBus value.
4
When driven by a crystal.
5
When driven by an external oscillator via the X1 pin, X2 should be floating.
2
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Nominal
Min
Min
Min
Max
9.94900
9.99900
10.00000
10.00100
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.05100
ns
1,2
Clock Periods–Differential Outputs with Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
+ ppm
- ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
AbsPer
Period
Average
Average
Average
Min
Nominal
Min
Min
Max
9.94906
9.99906
10.02406
10.02506
10.02607
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.10107
ns
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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General SMBus Serial Interface Information
How to Write
How to Read
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
ACK
WR
WRite
ACK
Beginning Byte = N
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
RT
Slave Address
Beginning Byte N
ACK
X Byte
O
O
O
Repeat starT
RD
ReaD
ACK
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
X Byte
P
O
Note: Read/Write address is latched on SADR pin.
O
O
O
O
O
Byte N + X - 1
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
N
Not acknowledge
P
stoP bit
10
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SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
DIF OE7
Output Enable
RW
Low/Low
Bit 7
DIF OE6
Output Enable
RW
Low/Low
Bit 6
DIF OE5
Output Enable
RW
Low/Low
Bit 5
DIF OE4
Output Enable
RW
Low/Low
Bit 4
DIF OE3
Output Enable
RW
Low/Low
Bit 3
DIF OE2
Output Enable
RW
Low/Low
Bit 2
DIF OE1
Output Enable
RW
Low/Low
Bit 1
DIF OE0
Output Enable
RW
Low/Low
Bit 0
1. A low on these bits will override the OE# pin and force the differential output Low/Low
SMBus Table: SS Readback and Control Register
Byte 1
Name
Control Function
SSENRB1
SS Enable Readback Bit1
Bit 7
SSENRB1
SS Enable Readback Bit0
Bit 6
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
SSENSW1
SS Enable Software Ctl Bit1
Bit 4
SSENSW0
SS Enable Software Ctl Bit0
Bit 3
Reserved
Bit 2
AMPLITUDE 1
Bit 1
Controls Output Amplitude
AMPLITUDE 0
Bit 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
SLEWRATESEL DIF7
Adjust Slew Rate of DIF7
Bit 7
SLEWRATESEL DIF6
Adjust Slew Rate of DIF6
Bit 6
SLEWRATESEL DIF5
Adjust Slew Rate of DIF5
Bit 5
SLEWRATESEL DIF4
Adjust Slew Rate of DIF4
Bit 4
SLEWRATESEL DIF3
Adjust Slew Rate of DIF3
Bit 3
SLEWRATESEL DIF2
Adjust Slew Rate of DIF2
Bit 2
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 0
1
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Type
0
1
00' for SS_EN_tri = 0, '01' for SS_EN_tri
R
= 'M', '11 for SS_EN_tri = '1'
R
RW
Values in B1[7:6] Values in B1[4:3]
control SS amount control SS amount.
RW 1
RW 1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW
RW
00 = 0.6V
10= 0.8V
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Fast
Fast
Fast
Fast
Fast
Fast
Fast
Fast
REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Wake-on-Lan Enable for REF
REF Output Enable
Reserved
Reserved
Reserved
Reserved
Default
Latch
Latch
0
0
0
1
1
0
01 = 0.7V
11 = 0.9V
1
Setting
Setting
Setting
Setting
Setting
Setting
Setting
Setting
SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register
Byte 3
Name
Control Function
Type
RW
Bit 7
REF
Slew Rate Control
RW
Bit 6
Bit 5
Default
1
1
1
1
1
1
1
1
Default
1
1
1
1
1
1
1
1
0
1
00 = Slowest
01 = Slow
10 = Fast
11 = Faster
REF does not run in REF runs in Power
RW
Power Down
Down
RW
Low
Enabled
Default
0
1
0
1
1
1
1
1
Byte 4 is Reserved
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
RID3
Bit 7
RID2
Bit 6
Revision ID
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VENDOR ID
VID1
Bit 1
VID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Device Type/Device ID
Byte 6
Name
Device Type1
Bit 7
Device Type0
Bit 6
Device ID5
Bit 5
Device ID4
Bit 4
Device ID3
Bit 3
Device ID2
Bit 2
Device ID1
Bit 1
Device ID0
Bit 0
Type
R
R
R
R
R
R
R
R
SMBus Table: Byte Count Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
Control Function
Device Type
Device ID
Control Function
Reserved
Reserved
Reserved
Byte Count Programming
Type
RW
RW
RW
RW
RW
0
1
A rev = 0001
0001 = IDT
0
1
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
001000 binary or 08 hex
0
Default
0
0
0
1
0
0
0
1
Default
0
0
0
0
1
0
0
0
1
Default
0
0
0
0
1
Writing to this register will configure how
0
many bytes will be read back, default is
0
= 8 bytes.
0
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commercial)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
Load Capacitance (CL)
Drive Level
Aging per year
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
25
Fundamental
±20
MHz
PPM Max
1
1
1
±20
PPM Max
1
0~70
-40~85
50
7
8
0.3
±5
°C
°C
Ω Max
pF Max
pF Max
mW Max
PPM Max
1
2
1
1
1
1
1
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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Thermal Characteristics
PARAMETER
Thermal Resistance
SYMBOL
CONDITIONS
PKG
Junction to Case
θJC
Junction to Base
θJb
Junction to Air, still air
θJA0
NDG48
Junction to Air, 1 m/s air flow
θJA1
Junction to Air, 3 m/s air flow
θJA3
Junction to Air, 5 m/s air flow
θJA5
TYP.
33
2.1
37
30
27
26
UNITS
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
NOTES
1
1
1
1
1
1
1
ePad soldered to board
Marking Diagram
IDT6P413
02NDGI
YYWW$
LOT
Notes:
2. ‘G’ denotes RoHS compliant package.
3. ‘I’ denotes industrial temperature grade.
3. ‘$’ is the mark code.
4. ‘YYWW’ is the last two digits of the year and week that the part was assembled.
6. ‘LOT’ is the lot number.
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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Package Outline Drawings (NDG48P1)
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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Package Outline Drawings (NDG48P1), cont.
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
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Ordering Information
Part / Order Number Shipping Packaging
Package
6P41302NDGI
Trays
48-pin VFQFPN
6P41302NDGI8
Tape and Reel
48-pin VFQFPN
Temperature
-40 to +85° C
-40 to +85° C
“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Revision History
Issue Date Description
2/22/2013 Initial release - final
1. Updated block diagram to latest format.
2. Removed red highlighting of certain VDD pins.
3. Updated IDD tables to break out Idd Suspend current. Total current
7/7/2014
did not change.
4. General description updated to latest standard.
5. Byte 6 b(7:6) description updated.
1. Updated front page text and block diagram.
2. Updated pin out to remove references to VDD Suspend pins. Using
the part with collapsible power supplies did not save power and
9/29/2014 complicated board design. NO pins were changed.
3. Updated SMBus Descriptions
4. Simplified footnote 2 on PPM table.
5. Updated all electrical tables to latest format.
1/24/2018 1. Corrected Byte 5 bit 4 to be '1' instead of '0'
IDT® 8-OUTPUT SMALL FORM FACTOR PCIE GEN 1-3 CLOCK GENERATOR
16
Page #
Various
Various
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SYNTHESIZERS
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