7005L15JG

HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial:15/17/20/25/35ns (max.) – Industrial: 20ns (max.) – Military: 20/25/35/55/70ns (max.) Low-power operation – IDT7005S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7005L Active: 700mW (typ.) Standby: 1mW (typ.) IDT7005 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 7005S/L M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Devices are capable of withstanding greater than 2001V electrostatic discharge Battery backup operation—2V data retention TTL-compatible, single 5V (±10%) power supply Available in 68-pin PGA, PLCC and a 64-pin thin quad flatpack Industrial temperature range (-40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram OEL OER CEL R/WL CER R/WR I/O0L- I/O7L I/O0R-I/O7R I/O Control I/O Control (1,2) (1,2) BUSYL A12L A0L BUSYR Address Decoder MEMORY ARRAY 13 CEL OEL R/WL SEML (2) INTL A12R A0R 13 ARBITRATION INTERRUPT SEMAPHORE LOGIC M/S CER OER R/WR SEMR INTR(2) 2738 drw 01 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. 1 Feb.14.20 Address Decoder 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-ormore word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500µW from a 2V battery. The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military grade product is manufactured in compliance with MIL-PRF-38535 QML making it ideally suited to military temperature applications demanding the highest level of performance and reliability. 8 29 7 30 6 31 5 32 4 3 66 65 40 64 41 63 42 62 43 61 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A4R A3R A2R A6R A7R A10L 54 A10R A11L A12L 55 56 57 58 A8L A9L VCC N/C CEL SEML R/WL OEL I/O0L I/O1L 7005 PNG64(4) 64-Pin TQFP Top View 59 60 61 23 22 21 20 19 18 62 63 64 1 2 27 26 25 24 3 4 5 6 7 8 17 9 10 11 12 13 14 15 16 A5R A8R A9R A11R A12R GND N/C CER SEMR R/WR OER I/O7R I/O6R I/O2L I/O3L I/O4L I/O5L 2738 drw 03 6.42 2 Feb.14.20 A1R 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 50 31 51 30 52 29 28 53 A5L A6L A7L NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PLG68 package body is approximately .95 in x .95 in x .12 in. PNG64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. A0R A4L 2738 drw 02 INTR 39 67 M/S BUSYR 68-Pin PLCC Top View GND 38 GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R 37 1 68 BUSYL 36 2 VCC PLG68(4) I/O7L 35 A0L INTL 7005 A1L 34 GND I/O6L 33 I/O1L I/O0L N/C OEL R/WL SEML CEL N/C N/C VCC A12L A11L A10L A9L A8L A7L A6L 9 A2L 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 28 A3L 27 A4R A3R A2R A1R A0R INTR BUSYR M/S GND BUSYL INTL A0L A1L A2L A3L A4L A5L I/O7R N/C OER R/WR SEMR CER N/C N/C GND A12R A11R A10R A9R A8R A7R A6R A5R 26 I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O7L I/O6L GND I/O5L I/O4L I/O3L I/O2L Pin Configurations(1,2,3) 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) 11 51 50 A5L A4L 48 A2L 46 44 42 A0L BUSYL M/S 40 38 INTR A1R 36 A3R 47 A1L 45 43 41 39 37 INTL GND BUSYR A0R A2R 35 A4R 34 A5R 10 53 A7L 52 A6L 09 55 A9L 54 A8L 32 A7R 33 A6R 08 56 57 A11L A10L 30 A9R 31 A8R 07 58 59 VCC A12L 29 28 A11R A10R 61 06 N/C 49 A3L 7005 GU68(4,5) 60 N/C 27 26 GND A12R 05 62 63 SEML CEL 24 N/C 04 64 65 OEL R/WL 23 22 SEMR CER 03 67 66 I/O0L N/C 20 OER 02 1 3 5 7 9 18 19 68 11 13 15 I/O1L I/O2L I/O4L GND I/O7L GND I/O1R VCC I/O4R I/O7R N/C 2 4 I/O3L I/O5L 01 A B C 6 8 I/O6L VCC D E 25 N/C 21 R/WR 10 12 14 16 17 I/O0R I/O2R I/O3R I/O5R I/O6R F G H J K L INDEX 2738 drw 04 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.18in x 1.18in x .16in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking Pin Names Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A12L A0R - A12R Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 2738 tbl 01 6.42 3 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs CE R/W OE SEM I/O0-7 H X X H High-Z Deselected: Power-Down L L X H DATAIN Write to Memory L H L H DATAOUT X X H X High-Z Mode Read Memory Outputs Disabled 2738 tbl 02 NOTE: 1. A0L – A12L is not equal to A0R – A12R Truth Table II: Semaphore Read/Write Control(1) Inputs(1) Outputs CE R/W OE SEM I/O0-7 H H L L DATAOUT H ↑ X L DATAIN L X X L ____ Mode Read in Semaphore Flag Data Out Write I/Oo into Semaphore Flag Not Allowed 2738 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2. Absolute Maximum Ratings(1) Commercial & Industrial Military Unit Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V Temperature Under Bias -55 to +125 Storage Temperature -65 to +150 Symbol VTERM(2) TBIAS TSTG IOUT Rating Maximum Operating Temperature and Supply Voltage(1,2) Grade Military -65 to +135 Commercial C Industrial -65 to +150 50 DC Output Current o o 50 Ambient Temperature GND Vcc -55OC to+125OC 0V 5.0V + 10% 0OC to +70OC 0V 5.0V + 10% -40 C to +85 C OV 5.0V + 10% O O C 2738 tbl 05 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2 Industrial temperature: for specific speeds, packages and powers contact your sales office. mA 2738 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10% maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Capacitance (1) Symbol CIN COUT Recommended DC Operating Conditions Symbol (TA = +25°C, f = 1.0MHz) (2) Parameter Conditions Max. Unit Input Capacitance VIN = 3dV 9 pF VOUT = 3dV 10 pF Output Capacitance 2738 tbl 07 Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V V VCC Supply Voltage GND Ground VIH Input High Voltage 2.2 ____ 6.0(2) VIL Input Low Voltage -0.5(1) ____ 0.8 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. NOTES: 1. These parameters are determined by device characterization but are not production tested (TQFP Package only). 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 6.42 4 Feb.14.20 Parameter V 2738 tbl 06 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the 0perating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7005S Symbol Parameter Test Conditions 7005L Min. Max. Min. Max. Unit |ILI| Input Leakage Current(1) VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA |ILO| Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V 2738 tbl 08 NOTE: 1. At Vcc < 2.0V input leakages are undefined. Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V) Symbol Parameter Test Condition Min. Typ. (1) Max. Unit 2.0 ___ ___ V µA VDR VCC for Data Retention VCC = 2V ICCDR Data Retention Current CE > VHC Mil. & Ind. ___ 100 4000 VIN > VHC or < VLC Com'l. ___ 100 1500 0 ___ ___ ns ___ ___ ns tCDR(3) (3) tR Chip Deselect to Data Retention Time SEM > VHC (2) Operation Recovery Time tRC 2738 tbl 09 NOTES: 1. TA = +25°C, VCC = 2V, and are not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by characterization, but is not production tested. Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V tCDR 4.5V tR VDR CE VIH VIH 2738 drw 05 6.42 5 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%) 7005X15 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition Version 7005X17 Com'l Only 7005X20 Com'l, Ind & Military 7005X25 Com'l & Military Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit COM'L S L 170 160 310 260 170 160 310 260 160 150 290 240 155 145 265 220 mA MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 160 150 370 320 155 145 340 280 COM'L S L 20 10 60 60 20 10 60 50 20 10 60 50 16 10 60 50 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 20 10 90 70 16 10 80 65 COM'L S L 105 95 190 160 105 95 190 160 95 85 180 150 90 80 170 140 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 95 85 240 210 90 80 215 180 Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 100 90 170 140 100 90 170 140 90 80 155 130 85 75 145 120 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 90 80 225 200 85 75 200 170 CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(3) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled f=fMAX(3) SEMR = SEML = VIH mA mA mA mA 2738 tbl 10 7005X35 Com'l, Ind & Military Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Version 7005X55 Com'l, Ind & Military 7005X70 Military Only Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit ____ mA Dynamic Operating Current (Both Ports Active) CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) COM'L S L 150 140 250 210 150 140 250 210 ____ ____ ____ MIL & IND S L 150 140 300 250 150 140 300 250 140 130 300 250 Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(3) COM'L S L 13 10 60 50 13 10 60 50 ____ ____ ____ ____ MIL & IND S L 13 10 80 65 13 10 80 65 10 8 80 65 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled f=fMAX(3) SEMR = SEML = VIH COM'L S L 85 75 155 130 85 75 155 130 ____ ____ ____ ____ MIL & IND S L 85 75 190 160 85 75 190 160 80 70 190 160 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 ____ ____ ____ ____ MIL & IND S L 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 80 70 135 110 80 70 135 110 ____ ____ ____ ____ MIL & IND S L 80 70 175 150 80 70 175 150 75 65 175 150 NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VCC = 5V, TA = +25°C and are not production tested. ICC DC = 120mA (typ) 3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the port opposite port "A". 6.42 6 Feb.14.20 mA mA mA mA 2738 tbl 11 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Test Conditions 5V 5V GND to 3.0V Input Pulse Levels Input Timing Reference Levels 1.5V Output Reference Levels 1.5V 1250Ω 1250Ω 5ns Max. Input Rise/Fall Times DATAOUT BUSY INT DATAOUT 5pF* 775Ω 30pF 775Ω Figures 1 and 2 Output Load 2738 tbl 12 2738 drw 06 Figure 1. AC Output Test Load Figure 2. Output Test Load (For tLZ, tHZ, tWZ, tOW) *Including scope and jig AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 7005X15 Com'l Only Symbol Parameter 7005X17 Com'l Only 7005X25 Com'l & Military 7005X20 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 17 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 17 ____ 20 ____ 25 ns tACE Chip Enable Access Time (3) ____ 15 ____ 17 ____ 20 ____ 25 ns tAOE Output Enable Access Time ____ 10 ____ 10 ____ 12 ____ 13 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ 3 ____ ns ____ 10 ____ 10 ____ 12 ____ 15 ns (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) tPU Chip Enable to Power Up Time (2,5) (2,5) 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 15 ____ 17 ____ 20 ____ 25 ns 10 ____ 10 ____ 10 ____ ns ____ 17 ____ 20 ____ 25 ns tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ tSAA Semaphore Address Access Time ____ 15 2738 tbl 13a 7005X35 Com'l, Ind & Military Symbol Parameter 7005X55 Com'l, Ind & Military IDT7005X70 Military Only Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 ____ 55 ____ 70 ____ ns tAA Address Access Time ____ 35 ____ 55 ____ 70 ns tACE Chip Enable Access Time (3) ____ 35 ____ 55 ____ 70 ns tAOE Output Enable Access Time ____ 20 ____ 30 ____ 35 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ ns ____ 15 ____ 25 ____ 30 ns 0 ____ 0 ____ 0 ____ ns ____ 35 ____ 50 ____ 50 ns 15 ____ 15 ____ ns ____ 55 ____ 70 tLZ Output Low-Z Time (1,2) (1,2) tHZ Output High-Z Time tPU Chip Enab le to Power Up Time (2,5) (2,5) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) 15 ____ tSAA Semaphore Address Access Time ____ 35 NOTES: 1. Transition is measured 0mV from Low or High impedance voltage with load (Figures 1 and 2). 2. This parameter is guaranteed but not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. 'X' in part number indicates power rating (S or L). 6.42 7 Feb.14.20 ns 2738 tbl 13b 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) tRC ADDR tAA(4) tACE(4) CE tAOE(4) OE R/W tOH tLZ(1) (4) DATAOUT VALID DATA tHZ(2) BUSYOUT tBDD(3,4) 2738 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. Timing of Power-Up Power-Down CE ICC tPU tPD ISB 2738 drw 08 6.42 8 Feb.14.20 , 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7005X15 Com'l Only Symbol Parameter 7005X17 Com'l Only 7005X20 Com'l, Ind & Military 7005X25 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit 15 ____ 17 ____ 20 ____ 25 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 12 ____ 15 ____ 20 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns ns WRITE CYCLE tWC Write Cycle Time (3) tAS Address Set-up Time tWP Write Pulse Width 12 ____ 12 ____ 15 ____ 20 ____ tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 10 ____ 15 ____ 15 ____ ns ____ 10 ____ 10 ____ 12 ____ 15 ns 0 ____ 0 ____ 0 ____ ns 10 ____ 12 ____ 15 ns ns ns tHZ tDH tWZ tOW tSWRD tSPS Output High-Z Time Data Hold Time (1,2) (4) 0 ____ (1,2) ____ 10 ____ (1,2,4) 0 ____ 0 ____ 0 ____ 0 ____ SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ 5 ____ SEM Flag Contention Window 5 ____ 5 ____ 5 ____ 5 ____ Write Enable to Output in High-Z Output Active from End-of-Write ns 2738 tbl 14a 7005X35 Com'l, Ind & Military Symbol Parameter 7005X55 Com'l, Ind & Military 7005X70 Military Only Min. Max. Min. Max. Min. Max. Unit 35 ____ 55 ____ 70 ____ ns tEW Chip Enable to End-of-Write (3) 30 ____ 45 ____ 50 ____ ns tAW Address Valid to End-of-Write 30 ____ 45 ____ 50 ____ ns 0 ____ 0 ____ 0 ____ ns ns WRITE CYCLE tWC Write Cycle Time (3) tAS Address Set-up Time tWP Write Pulse Width 25 ____ 40 ____ 50 ____ tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 15 ____ 30 ____ 40 ____ ns ____ 15 ____ 25 ____ 30 ns ns tHZ Output High-Z Time (1,2) (4) tDH Data Hold Time 0 ____ 0 ____ 0 ____ tWZ Write Enable to Output in High-Z(1,2) ____ 15 ____ 25 ____ 30 ns tOW Output Active from End-of-Write (1,2,4) 0 ____ 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ 5 ____ ns 2738 tbl 14b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part number indicates power rating (S or L). 6.42 9 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ(7) OE tAW (9) CE or SEM tAS(6) tWR(3) tWP(2) R/W tWZ(7) tOW (4) DATAOUT (4) tDW tDH DATAIN 2738 drw 09 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM(9) tAS(6) tEW(2) tWR(3) R/W tDW tDH DATAIN 2738 drw 10 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 6.42 10 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW tOH VALID ADDRESS tWR tACE tEW SEM tDW DATA0 tSOP DATA OUT VALID DATAIN VALID tAS tWP tDH R/W tSWRD OE tAOE tSOP Write Cycle Read Cycle 2738 drw 11 NOTE: 1. CE = VIH for the duration of the above timing (both write and read cycle). Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE “A” MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE “B” MATCH R/W"B" SEM"B" 2738 drw 12 NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH. Semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port “A” may be either left or right port. “B” is the opposite from port “A”. 3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 6.42 11 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 7005X15 Com'l Only Symbol Parameter 7005X17 Com'l Only 7005X20 Com'l, Ind & Military 7005X25 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 17 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 17 ____ 20 ____ 20 ns tBAC BUSY Access Time from Chip Enable Low ____ 15 ____ 17 ____ 20 ____ 20 ns tBDC BUSY Access Time from Chip Enable High ____ 15 ____ 17 ____ 17 ____ 17 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ 5 ____ ns ____ 18 ____ 18 ____ 30 ____ 30 ns 12 ____ 13 ____ 15 ____ 17 ____ ns tBDD BUSY Disable to Valid Data tWH Write Hold After BUSY(5) (3) BUSY TIMING (M/S=VIL) tWB BUSY Input to Write (4) 0 ____ 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 13 ____ 15 ____ 17 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay (1) ____ 30 ____ 30 ____ 45 ____ 50 ns tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 25 ____ 35 ____ 35 ns 2738 tbl 15a 7005X35 Com'l, Ind & Military Symbol Parameter 7005X55 Com'l, Ind & Military 7005X70 Military Only Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 20 ____ 45 ____ 45 ns BUSY Disable Time from Address Not Matched ____ 20 ____ 40 ____ 40 ns BUSY Acce ss Time from Chip Enable Low ____ 20 ____ 40 ____ 40 ns BUSY Acce ss Time from Chip Enable High ____ 20 ____ 35 ____ 35 ns 5 ____ 5 ____ 5 ____ ns ____ 35 ____ 40 ____ 45 ns 25 ____ 25 ____ 25 ____ ns 0 ____ 0 ____ 0 ____ ns 25 ____ 25 ____ 25 ____ ns ____ 60 ____ 80 ____ 95 ns ____ 45 ____ 65 ____ 80 BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH Arbitration Priority Set-up Time BUSY Disable to Valid Date (2) (3) (5) Write Hold After BUSY BUSY TIMING (M/S=VIL ) tWB tWH BUSY Input to Write (4) (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention with port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part number indicates power rating (S or L). 6.42 12 Feb.14.20 ns 2738 tbl 15b 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read with BUSY(2,5) (M/S = VIH)(4) tWC MATCH ADDR"A" tWP R/W"A" tDW tDH VALID DATAIN "A" tAPS(1) MATCH ADDR"B" tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD(3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A". Timing Waveform of Write with BUSY tWP R/W"A" tWB(3) BUSY"B" tWH R/W"B" (1) (2) 2738 drw 14 NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH 3. tWB is only for the 'Slave' Version.. 6.42 13 Feb.14.20 2738 drw 13 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC tBDC BUSY"B" 2738 drw 15 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDRESS "N" ADDR"A" (2) tAPS MATCHING ADDRESS "N" ADDR"B" tBAA tBDA BUSY"B" 2738 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 7005X15 Com'l Only Symbol Parameter 7005X17 Com'l Only 7005X20 Com'l, Ind & Military 7005X25 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 15 ____ 15 ____ 20 ____ 20 ns tINR Interrupt Reset Time ____ 15 ____ 15 ____ 20 ____ 20 ns 2738 tbl 16a 7005X35 Com'l, Ind & Military Symbol Parameter 7005X55 Com'l, Ind & Military 7005X70 Military Only Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 40 ____ 50 ns tINR Interrupt Reset Time ____ 25 ____ 40 ____ 50 ns NOTE: 1. 'X' in part number indicates power rating (S or L). 2738 tbl 16b 6.42 14 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC INTERRUPT SET ADDRESS(2) ADDR"A" tAS(3) tWR(4) CE"A" R/W"A" tINS(3) INT"B" 2738 drw 17 tRC INTERRUPT CLEAR ADDRESS(2) ADDR"B" tAS(3) CE"B" OE"B" tINR(3) INT"B" 2738 drw 18 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R/W) asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. Truth Table III — Interrupt Flag(1,4) Left Port R/WL CEL OEL Right Port A12L-A0L INTL R/WR CER OER A12R-A0R L L X 1FFF X X X X X X X X X X X L L X X X X L(3) L L (2) X X X L L 1FFE H INTR (2) Function L Set Right INTR Flag 1FFF H(3) Reset Right INTR Flag X 1FFE X Set Left INTL Flag X X X Reset Left INTL Flag 2738 tbl 17 NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTR and INTL must be initialized at power-up. 6.42 15 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration Inputs Outputs CEL CER AOL-A12L AOR-A12R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 2738 tbl 18 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7005 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D7 Left D0 - D7 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7005. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2. 3. CE=VIH, SEM=VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table. Functional Description The IDT7005 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7005 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 1FFE (HEX), where a write is defined as CE = R/W= VIL per Truth Table III. The left port clears the interrupt through access of address location 1FFE when CE = OE = VIL. For this example, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 1FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 1FFF. The message (8 bits) at 1FFE or 1FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 1FFE and 1FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. 6.42 16 Feb.14.20 2738 tbl 19 7005S/L High-Speed 8K x 8 Dual-Port Static RAM BUSY (L) MASTER CE Dual Port RAM BUSY (L) BUSY (R) SLAVE CE Dual Port RAM BUSY (L) BUSY (R) MASTER CE Dual Port RAM BUSY (L) BUSY (R) SLAVE CE Dual Port RAM BUSY (L) BUSY (R) DECODER Military, Industrial and Commercial Temperature Ranges BUSY (R) , 2738 drw 19 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7005 RAMs. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7005 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT7005 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7005 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7005 is an extremely fast Dual-Port 8K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT7005 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7005's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying 6.42 17 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges configurations. The IDT7005 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7005 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7005’s Dual-Port RAM. Say the 8K x 8 RAM was to be divided into two 4K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and 6.42 18 Feb.14.20 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 4K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 4K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 4K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 4K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D SEMAPHORE REQUEST FLIP FLOP Q Q SEMAPHORE READ D0 WRITE SEMAPHORE READ Figure 4. IDT7005 Semaphore Logic 6.42 19 Feb.14.20 D 2738 drw 20 , 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Power Speed Package Type A A A Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38538 QML G(2) Green PF G J 64-pin TQFP (PNG64) 68-pin PGA (GU68) 68-pin PLCC (PLG68) 15 17 20 25 35 55 70 Commercial Only Commercial Only Commercial, Industrial & Military Commercial & Military Commercial & Military Military Only Military Only S L Standard Power Low Power Speed in nanoseconds 2738 drw 21 7005 64K (8K x 8) Dual-Port RAM NOTES: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office LEAD FINISH (SnPb) parts are Obsolete excluding PGA. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 15 Orderable Part ID 7005L15JG Pkg. Code Pkg. Type Temp. Grade PLG68 PLCC C 17 Speed (ns) 7005L15JG8 PLG68 PLCC C 20 7005L15PFG PNG64 TQFP C 25 7005L15PFG8 PNG64 TQFP C Pkg. Type Temp. Grade 7005S17G GU68 PGA C 7005S20G GU68 PGA C 7005S25G GU68 PGA C 7005S25GB GU68 PGA M 17 7005L17G GU68 PGA C 7005S35G GU68 PGA C 20 7005L20G GU68 PGA C 7005S35GB GU68 PGA M 7005S35PFG PNG64 TQFP C 7005S35PFG8 7005L20GB GU68 PGA M 7005L20JGI PLG68 PLCC I 35 Pkg. Code Orderable Part ID 7005L20JGI8 PLG68 PLCC I 55 7005L20PFGI PNG64 TQFP I 70 7005L20PFGI8 PNG64 TQFP I GU68 PGA C 25 7005L25G 7005L25GB GU68 PGA M 35 7005L35G GU68 PGA C 7005L35GB GU68 PGA M 55 7005L55GB GU68 PGA M 70 7005L70GB GU68 PGA M 6.42 20 Feb.14.20 PNG64 TQFP C 7005S55GB GU68 PGA M 7005S70GB GU68 PGA M 7005S/L High-Speed 8K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Datasheet Document History 12/21/98: Pages 2 & 3 06/03/99: 11/10/99: 08/07/00: Page 1 Page 4 Page 6 09/18/01: Page 2 & 3 Page 14 01/31/06: 10/21/08: 09/17/12: Page 1 Page 20 Page 20 Pages 6,7,9,12,& 14 06/10/16: Page 20 Pages 2 & 3 Pages 2 & 20 03/20/18: 02/14/20: Pages 1 - 22 Pages 1 & 20 Page 2 Pages 2 & 3 Page 20 Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Changed drawing format Replaced IDT logos Added copyright info Fixed overbar errors Increased storage temperature parameter Clarified TA Parameter DC Electrical parameters–changed wording from "open" to "disabled" Changed ±500mV to 0mV in notes Added date revision for pin configurations Replaced one copy of table 13b with 13a for 15, 17,20 & 25ns speeds for AC Electrical Characteristics INTERRUPT TIMING Added green availability to features Added green indicator to ordering information Removed "IDT" from orderable part number In all of the DC & AC Electrical tables the 7005X20 speed grade changed from 7005X20 Com'l & Military to include Ind making it Com'l, Ind & Military Added T& R indicator to ordering information Changed diagram for the PN64 pin configuration by rotating package pin labels and pin numbers 90 degrees counter clockwise to reflect pin 1 orientation & added pin 1 dot at pin 1 PN64 pin configuration: removed the PN64 chamfer, the arrow and the index indicator Added the IDT logo to all pin configurations and changed the text to be in alignment with new diagram marking specs Removed the date revision indicator from all pin configurations Updated footnote references for PN64 pin configuration The package codes PN64-1, G68-1 & J68-1 changed to PN64, G68 & J68 respectively to match standard package codes Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Rebranded as Renesas datasheet Deleted obsolete Industrial speed grades 35/55ns and Commercial speed grade 55ns Correction for previous 06/10/16 update. Removed F68 (FP68) pin configuration from the datasheet Updated package codes Added Orderable Part Information tables 6.42 21 Feb.14.20 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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