7007S35PF

HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT7007L Active: 850mW (typ.) Standby: 1mW (typ.) IDT7007 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 7007L M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in a 68-pin PLCC and a 80-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram OEL OER CEL R/WL CER R/WR I/O0L- I/O7L I/O0R-I/O7R I/O Control I/O Control (1,2) BUSYR BUSYL A14L A0L Address Decoder MEMORY ARRAY 15 CEL OEL R/WL SEML (2) INTL Address Decoder (1,2) A14R A0R 15 ARBITRATION INTERRUPT SEMAPHORE LOGIC M/S CER OER R/WR SEMR INTR(2) 2940 drw 01 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. SEPTEMBER 2019 1 DSC 2940/16 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very LOW standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 850mW of power. The IDT7007 is packaged in a 68-pin PLCC and an 80-pin thin quad flatpack TQFP. I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O7L I/O6L GND I/O5L I/O4L I/O3L I/O2L Pin Configurations(1,2,3) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 I/O7R N/C 27 9 28 8 OER R/WR SEMR CER 29 7 30 31 6 32 4 A14R A13R GND A12R A11R A10R A9R A8R A7R A6R A5R 33 5 3 7007 PLG68(4) 34 35 36 68-Pin PLCC Top View 37 2 1 68 67 38 66 39 65 40 64 41 63 42 62 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately .95 in x .95 in x .17 in. 4. This package code is used to reference the package diagram. 2 A0L A1L A2L A3L A4L A5L BUSYL INTL M/S GND INTR BUSYR A4R A3R A2R A1R A0R 61 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O1L I/O0L N/C OEL R/WL SEML CEL A14L A13L VCC A12L A11L A10L A9L A8L A7L A6L 2940 drw 02 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges N/C A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C Pin Configurations(1,2,3) (con't.) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 40 62 39 63 38 64 37 65 36 66 35 67 34 68 33 69 32 7007 70 31 PNG80(4) 71 30 72 29 80-Pin TQFP 73 28 Top View 74 27 75 26 76 25 77 24 78 23 79 22 80 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 N/C I/O2L I/O3L I/O4L I/O5L GND I/O6L I/O7L VCC N/C GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C A6L A7L A8L A9L A10L A11L A12L VCC A13L A14L N/C CEL SEML R/WL OEL N/C I/O0L I/O1L NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 3 N/C N/C A5R A6R A7R A8R A9R A10R A11R A12R GND A13R A14R N/C CER SEMR R/WR OER N/C I/O7R 2940 drw 03 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) 51 11 A5L 50 A4L 48 A2L 46 44 42 A0L BUSYL M/S 40 38 INTR A1R 36 A3R 49 A3L 47 A1L 45 43 41 39 37 INTL GND BUSYR A0R A2R 35 A4R 34 A5R 11/06/01 53 A7L 52 10 55 A9L 54 09 A8L 32 A7R 33 A6R 08 57 56 A11L A10L 30 A9R 31 A8R 07 59 58 VCC A12L 61 06 A6L 60 A14L 28 29 A11R A10R IDT7007G GU68(4) A13L 26 GND 68-Pin PGA Top View(5) 63 62 05 SEML CEL 27 A12R 24 25 A14R A13R 04 65 64 OEL R/WL 22 23 SEMR CER 03 67 66 I/O0L N/C 20 OER 02 1 3 68 I/O1L I/O2L I/O4L 2 4 I/O 5L I/O3L 01 A B C 21 R/WR 5 7 9 11 13 15 GND I/O7L GND I/O1R VCC I/O4R 18 19 I/O7R N/C 6 17 I/O6R 8 I/O6L D 10 12 14 16 VCC I/O0R I/O2R I/O3R I/O5R E F G H K J , L INDEX 2940 drw 04b NOTES: 1. All Vcc pins must be connected to power supply 2. All GND pins must be connected to ground. 3. Package body is approximately 1.8 in x 1.8 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking. Pin Names Left Port Right Port Names CEL CER Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A14L A0R - A14R Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 2940 tbl 01 4 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs CE R/W OE SEM I/O0-7 Mode H X X H High-Z Deselected: Power-Down L L X H DATAIN Write to Memory L H L H DATAOUT X X H X High-Z Read Memory Outputs Disabled 2940 tbl 02 NOTE: 1. A0L — A14L ≠ A0R — A14R Truth Table II: Semaphore Read/Write Control(1) Inputs Outputs CE R/W OE SEM I/O0-7 Mode H H L L DATAOUT H ↑ X L DATAIN L X X L ______ Read Semap hore Flag Data Out (I/O 0-I/O7) Write I/O0 into Semaphore Flag Not Allowed 2940 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all I/O's. These eight semaphores are addressed by A0 - A2. Maximum Operating Temperature and Supply Voltage(1) Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Commercial & Industrial Military Unit -0.5 to +7.0 -0.5 to +7.0 V Military TBIAS Temperature Under Bias -55 to +125 -65 to +135 o C TSTG Storage Temperature -65 to +150 -65 to +150 o C DC Output Current IOUT Grade 50 50 Commercial Ambient Temperature GND Vcc -55OC to+125OC 0V 5.0V + 10% 0 C to +70 C 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% O Industrial O NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. mA 2940 tbl 05 2940 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol Capacitance (TA = +25°C, f = 1.0Mhz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 Parameter pF NOTES: 1. This parameter is determined by device characterization but is not production tested. TQFP package only. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 5 Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V V VCC Supply Voltage GND Ground VIH Input High Voltage 2.2 ____ 6.0(2) VIL Input Low Voltage -0.5(1) ____ 0.8 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. 2940 tbl 07 Min. V 2940 tbl 06 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7007S Symbol Parameter Test Conditions 7007L Min. Max. Min. Max. Unit |ILI| Input Leakage Current(1) VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA |ILO| Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V 2940 tbl 08 NOTE: 1. At Vcc < 2.0V, input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%) 7007X15 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition Version 7007X20 Com'l & Ind 7007X25 Com'l, Ind & Military Typ.(2) Max. Typ.(2) Max. Typ. (2) Max. Unit 180 180 315 275 170 170 305 265 mA COM'L S L 190 190 325 285 MIL & IND S L ___ ___ ___ ___ ___ ___ 180 315 170 170 345 305 COM'L S L 35 35 85 60 30 30 85 60 25 25 85 60 MIL & IND S L ___ ___ ___ ___ ___ ___ 30 80 25 25 100 80 CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH COM'L S L 125 125 220 190 115 115 210 180 105 105 200 170 MIL & IND S L ___ ___ ___ ___ ___ ___ 115 210 105 105 230 200 Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L ___ ___ ___ ___ ___ ___ 0.2 10 1.0 0.2 30 10 CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 120 120 190 160 110 110 185 160 100 100 175 160 MIL & IND S L ___ ___ ___ ___ ___ ___ 110 185 100 100 200 175 CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(3) mA mA mA mA 2940 tbl 09 NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%) 7007X35 Com'l, Ind & Military Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Test Condition Version CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(3) Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) Typ.(2) Max. Typ.(2) Max. Unit mA COM'L S L 160 160 295 255 150 150 270 230 MIL & IND S L 160 160 335 295 150 150 310 270 COM'L S L 20 20 85 60 20 20 85 60 MIL & IND S L 20 20 100 80 13 13 100 80 COM'L S L 95 95 185 155 85 85 165 135 MIL & IND S L 95 95 215 185 85 85 195 165 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L 1.0 0.2 30 10 1.0 0.2 30 10 COM'L S L 90 90 160 135 80 80 135 110 MIL & IND S L 90 90 190 165 80 80 165 140 NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 7 7007X55 Com'l, Ind & Military mA mA mA mA 2940 tbl 10 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Test Conditions 5V GND to 3.0V Input Pulse Levels 893Ω 5ns Max. Input Rise/Fall Times Input Timing Reference Levels 1.5V Output Reference Levels 1.5V 5V DATAOUT BUSY INT 893Ω DATAOUT 30pF 347Ω 5pF* 347Ω Figures 1 and 2 Output Load 2940 tbl 11 2940 drw 05 2940 drw 06 Figure 2. Output Test Load Figure 1. AC Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 7007X15 Com'l Only Symbol Parameter Min. Max. 7007X20 Com'l & Ind Min. Max. 7007X25 Com'l, Ind & Military Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 20 ____ 25 ns tACE Chip Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tAOE Output Enable Access Time ____ 10 ____ 12 ____ 13 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ ns ____ 10 ____ 12 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) tPU Chip Enable to Power Up Time (2) (2) tPD Chip Disable to Power Down Time 15 ____ 20 ____ 25 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 10 ____ 12 ____ ns tSAA Semaphore Address Access Time ____ 15 ____ 20 ____ 25 ns 2940 tbl 12a 7007X35 Com'l, Ind & Military Symbol Parameter 7007X55 Com'l, Ind & Military Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 ____ 55 ____ ns 55 ns 55 ns tAA Address Access Time ____ 35 ____ tACE Chip Enable Access Time (3) ____ 35 ____ tAOE Output Enable Access Time ____ 20 ____ 30 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ ns ____ 15 ____ 25 ns ns tHZ Output High-Z Time (1,2) (2) tPU Chip Enab le to Power Up Time 0 ____ 0 ____ tPD Chip Disable to Power Down Time (2) ____ 35 ____ 50 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 15 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 35 ____ 55 NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). 8 ns 2940 tbl 12b 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) tRC ADDR (4) tAA (4) tACE CE tAOE (4) OE R/W tLZ tOH (1) DATAOUT VALID DATA (4) tHZ (2) BUSYOUT tBDD (3,4) 2940 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. Timing of Power-Up Power-Down CE ICC tPU tPD 50% 50% ISB , 2940 drw 08 9 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7007X15 Com'l Only Symbol Parameter 7007X20 Com'l & Ind 7007X25 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Unit 15 ____ 20 ____ 25 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns ns WRITE CYCLE tWC Write Cycle Time (3) tAS Address Set-up Time 0 ____ 0 ____ 0 ____ tWP Write Pulse Width 12 ____ 15 ____ 20 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 15 ____ 15 ____ ns ____ 10 ____ 12 ____ 15 ns 0 ____ 0 ____ ns 12 ____ 15 ns ns ns tHZ tDH tWZ tOW Output High-Z Time Data Hold Time (1,2) (4) 0 ____ (1,2) ____ 10 ____ (1,2,4) 0 ____ 0 ____ 0 ____ 5 ____ 5 ____ 5 ____ 5 ____ Write Enable to Output in High-Z Output Active from End-of-Write tSWRD SEM Flag Write to Read Time 5 ____ tSPS SEM Flag Contention Window 5 ____ ns 2940 tbl 13a 7007X35 Com'l, Ind & Military Symbol Parameter 7007X55 Com'l, Ind & Military Min. Max. Min. Max. Unit 35 ____ 55 ____ ns tEW Chip Enable to End-of-Write (3) 30 ____ 45 ____ ns tAW Address Valid to End-of-Write 30 ____ 45 ____ ns 0 ____ 0 ____ ns ns ns WRITE CYCLE tWC Write Cycle Time (3) tAS Address Set-up Time tWP Write Pulse Width 25 ____ 40 ____ tWR Write Recovery Time 0 ____ 0 ____ tDW Data Valid to End-of-Write 15 ____ 30 ____ ns tHZ Output High-Z Time (1,2) ____ 12 ____ 25 ns tDH Data Hold Time (4) tWZ tOW 0 ____ 0 ____ ns (1,2) ____ 12 ____ 25 ns (1,2,4) 0 ____ 0 ____ ns 5 ____ ns 5 ____ ns Write Enable to Output in High-Z Output Active from End-of-Write tSWRD SEM Flag Write to Read Time 5 ____ tSPS SEM Flag Contention Window 5 ____ 2940 tbl 13b NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). 10 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM (9) tWP (2) tAS (6) tWR (3) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 2940 drw 09 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9) (6) tAS tWR(3) tEW (2) R/W tDW tDH DATAIN 2940 drw 10 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 11 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW tOH VALID ADDRESS tWR tACE tEW SEM tSOP tDW DATAOUT VALID(2) DATAIN VALID DATA0 tAS tWP tDH R/W tSWRD OE tAOE tSOP Write Cycle Read Cycle 2940 drw 11 NOTE: 1. CE = VIH for the duration of the above timing (both write and read cycle). Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 2940 drw 12 NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 12 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 7007X15 Com'l Only Symbol Parameter 7007X20 Com'l & Ind 7007X25 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 15 ____ 20 ____ 20 ns tBDC BUSY Acce ss Time from Chip Enable High ____ 15 ____ 17 ____ 17 ns 5 ____ 5 ____ 5 ____ ns ____ 18 ____ 30 ____ 30 ns 12 ____ 15 ____ 17 ____ ns 0 ____ 0 ____ 0 ____ ns 12 ____ 15 ____ 17 ____ ns ____ 30 ____ 45 ____ 50 ns ____ 25 ____ 30 ____ 35 tAPS tBDD tWH Arbitration Priority Set-up Time (2) (3) BUSY Disable to Valid Data (5) Write Hold After BUSY BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write (4) (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) ns 2940 tbl 14a 7007X35 Com'l, Ind & Military Symbol Parameter 7007X55 Com'l, Ind & Military Min. Max. Min. Max. Unit BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 20 ____ 45 ns tBDA BUSY Disable Time from Address Not Matched ____ 20 ____ 40 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 20 ____ 40 ns tBDC BUSY Acce ss Time from Chip Enable High ____ 20 ____ 35 ns 5 ____ 5 ____ ns ____ 35 ____ 40 ns 25 ____ 25 ____ ns 0 ____ 0 ____ ns 25 ____ 25 ____ ns ____ 60 ____ 80 ns ____ 45 ____ 65 ns tAPS tBDD tWH Arbitration Priority Set-up Time (2) (3) BUSY Disable to Valid Data (5) Write Hold After BUSY BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write (4) (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) 2940 tbl 14b NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). 13 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4) tWC MATCH ADDR"A" tWP R/W"A" tDW tDH VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) 2940 drw 13 NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example). 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB BUSY"B" tWH (1) R/W"B" (2) , 2940 drw 14 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 14 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 2940 drw 15 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" ADDRESS "N" tAPS ADDR"B" (2) MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 2940 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2) 7007X15 Com'l Only Symbol Parameter 7007X20 Com'l & Ind 7007X25 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 15 ____ 20 ____ 20 ns tINR Interrupt Reset Time ____ 15 ____ 20 ____ 20 ns 2940 tbl 15a 7007X35 Com'l, Ind & Military Symbol Parameter 7007X55 Com'l, Ind & Military Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 40 ns tINR Interrupt Reset Time ____ 25 ____ 40 ns 2940 tbl 15b NOTES: 1. 'X' in part numbers indicates power rating (S or L). 15 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC INTERRUPT SET ADDRESS ADDR"A" tAS (3) (2) tWR (4) CE"A" R/W"A" tINS (3) INT"B" 2940 drw 17 tRC ADDR"B" INTERRUPT CLEAR ADDRESS (2) tAS (3) CE"B" OE"B" tINR (3) INT"B" 2940 drw 18 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. Truth Table III — Interrupt Flag(1) Left Port R/WL L X X X CEL L X X L OEL X X X L Right Port A14L-A0L 7FFF INTL X R/WR CER X X OER X A14R-A0R X INTR Function (2) Set Right INTR Flag (3) Reset Right INTR Flag L X X X L L 7FFF H X (3) L L X 7FFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag 7FFE L H 2940 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 16 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration Inputs Outputs CEL CER AOL-A14L AOR-A14R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 2940 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D7 Left D0 - D7 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007. 2. There are eight semaphore flags written to via I/O5(I/O0 - I/O7) and read from all I/O0. These eight semaphores are addressed by A0 - A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Functional Description 2940 tbl 18 when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFF. The message (8 bits) at 7FFE or 7FFF is userdefined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFE and 7FFF are not used as mail boxes, but as part of the random access memory. Refer to Table III for the interrupt operation. The IDT7007 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7007 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FFE (HEX), where a write is defined as CE = R/W = VIL per the Truth Table. The left port clears the interrupt through access of address location 7FFE Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is 17 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7007 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7007 is an extremely fast Dual-Port 16K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT7007 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7007 hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7007 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. BUSY (L) CE MASTER Dual Port RAM BUSY (L) BUSY (R) CE SLAVE Dual Port RAM BUSY (L) BUSY (R) MASTER CE Dual Port RAM BUSY (L) BUSY (R) CE SLAVE Dual Port RAM BUSY (L) BUSY (R) DECODER Width Expansion with Busy Logic BUSY (R) 2940 drw 19 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7007 RAMs. Master/Slave Arrays When expanding an IDT7007 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7007 RAM the BUSY pin is an output if the part is used as a master (M/S pin = H), and the BUSY pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, 18 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7007 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay low until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D SEMAPHORE READ Q SEMAPHORE REQUEST FLIP FLOP Q D D0 WRITE SEMAPHORE READ , 2940 drw 20 Figure 4. IDT7007 Semaphore Logic first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7007’s Dual-Port RAM. Say the 32K x 8 RAM was to be divided into two 16K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 16K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 16K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 16K section 19 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 16K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. 20 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Power Speed Package Type A A A Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I (1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green PF J 80-pin TQFP (PNG80) 68-pin PLCC (PLG68) 15 20 Commercial Industrial L Low Power 7007 256K (32K x 8) Dual-Port RAM Speed in nanoseconds 2940 drw 21 NOTES: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 15 20 Pkg. Code Pkg. Type Temp. Grade PLG68 PLCC C 7007L15JG8 PLG68 PLCC C 7007L15PFG PNG80 TQFP C 7007L20JGI PLG68 PLCC I 7007L20JGI8 PLG68 PLCC I 7007L20PFGI PNG80 TQFP I Orderable Part ID 7007L15JG 21 7007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Datasheet Document History 01/05/99: 06/03/99: 03/24/00: 05/08/00: 09/11/01: 01/31/06: 10/21/08: 08/12/14: 04/01/19: 09/04/19: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2, 3, 4 Added additional notes to pin configurations Changed drawing format Added Industrial Temperature Ranges and removed related notes Replaced IDT logo Changed ±200mV to 0mV in notes Page 1 Added copyright info Page 5 Fixed Absolute Maximum Ratings chart, corrected typos Page 9 Updated drawings Page 12 Corrected waveform drawing Page 5 Increased storage temperature parameter Clarified TA parameter Pages 6, 7 DC Electrical parameters–changed working from open to disabled Page 2 - 4 Added date revision for pin configurations Page 6 Removed standard power offering for Industrial temp for 20ns from DC Electrical Characteristics Page 1 Added green availability to features Page 21 Added green indicator to ordering information Page 21 Removed "IDT" from orderable part number Page 21 Added Tape and Reel to Ordering Information Page 2, 3, 4 & 21 The package codes PN80-1, G68-1 & J68-1 changed to PN80, G68 & J68 respectively to match standard package codes Page 1 Updated Features by removing all speed grade offerings except the Commercial 15ns and Industrial 20ns and by removing all of the Military speed and temp range offerings Page 2 Removed "IDT's" from the fabrication reference in the Description text Additionally, updated the Description text by removing the ceramic 68-pin PGA package offering Page 2, 3 & 21 The package codes J68 & PN80 changed to PLG68 & PNG80 respectively to match standard package codes Page 17 & 18 Format updates to "Interrupts" heading and third paragraph in "How the Semaphore Flags Work" Page 21 Updated Ordering Information by removing all of the Military temp range offerings and removing the Industrial temp range except for the 20ns Additionally, removed the GU68 package offering from the ordering information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 2 & 3 Rotated PLG68 PLCC and PNG80 TQFP pin configurations to accurately reflect pin 1 orientation Page 21 Added Orderable Part Information table CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 22 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.