7014S20PF8

7014S HIGH-SPEED 4K x 9DUAL-PORT STATIC RAM Description: Features: ◆ ◆ ◆ ◆ ◆ ◆ The IDT7014 is a high-speed 4K x 9 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to high-speed applications which do not rely on BUSY signals to manage simultaneous access. The IDT7014 provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. See functional description. The IDT7014 utilizes a 9-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/ reception error checking. Fabricated using a high-performance technology, these Dual-Ports typically operate on only 750mW of power at maximum access times as fast as 12ns. The IDT7014 is packaged in a 52-pin PLCC and a 64-pin thin quad flatpack, (TQFP). True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 12ns (max.) ◆ Standard-power operation – IDT7014S Active: 750mW (typ.) Fully asynchronous operation from either port TTL-compatible; single 5V (±10%) power supply Available in 52-pin PLCC and a 64-pin TQFP Green parts available, see ordering information Functional Block Diagram R/WL R/WR OEL OER A0L- A11L I/O CONTROL I/O CONTROL I/O0L- I/O8L ADDRESS DECODER MEMORY ARRAY I/O0R- I/O8R ADDRESS DECODER A0R- A11R 2528 drw 01 MAY 2019 1 DSC 2528/20 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range 20 19 18 17 16 15 14 13 12 11 10 9 8 21 7 22 6 5 23 4 24 3 25 7014 2 26 (4) PLG52 27 1 28 52-Pin 52 PLCC 29 51 Top View 30 50 31 49 32 48 33 47 34 35 36 37 38 39 40 41 42 43 44 45 46 A5L A4L A3L A2L A1L A0L A0R A1R A2R A3R A4R A5R A6R 2528 drw 02 A6R A7R A8R A9R A10R A11R OER N/C GND N/C R/WR N/C GND I/O8R I/O7R I/O6R I/O5R I/O6R I/O7R I/O8R GND R/WR GND OER A11R A10R A9R A8R A7R I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L I/O0R I/O1R I/O2R I/O3R VCC I/O4R A11L A10L A9L A8L A7L A6L I/O6L I/O7L I/O8L GND R/WL VCC OEL Pin Configuration(1,2,3) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 7014 26 55 PNG64(4) 56 25 24 57 64-Pin 23 58 TQFP 59 22 Top View 60 21 61 20 19 62 18 63 17 64 1 2 3 4 5 6 7 8 9 10 11 12 131415 16 A5R A4R A3R A2R A1R A0R N/C N/C N/C N/C A0L A1L A2L A3L A4L A5L I/O5R I/O4R VCC I/O3R I/O2R I/O1R I/O0R GND GND I/O0L I/O1L I/O2L I/O3L I/O4L VCC I/O5L A6L A7L A8L A9L A10L A11L OEL N/C VCC N/C R/WL N/C GND I/O8L I/O7L I/O6L 2528 drw 03 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PLG52 package body is approximately .75 in x .75 in. x .17 in. PNG64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 2 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range Absolute Maximum Ratings (1) Symbol Rating Commercial & Industrial Unit Terminal Voltage with Respect to GND -0.5 to +7.0 V VTERM(2) Terminal Voltage -0.5 to +VCC TBIAS Temperature Under Bias -55 to +125 TSTG Storage Temperature -65 to +150 IOUT DC Output Current VTERM(2) Maximum Operating Temperature and Supply Voltage(1,2) Grade Commercial 50 Ambient Temperature GND Vcc 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% V Industrial o C NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. o C 2528 tbl 02 mA 2528 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol Parameter VCC Supply Voltage GND Ground VIH Input High Voltage VIL Input Low Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ 6.0(2) V ____ 0.8 (1) -0.5 V 2528 tbl 03 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%) 7014S Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VCC = 5.5V, VIN = 0V to V CC ___ 10 µA |ILO| Output Leakage Current VOUT = 0V to V CC ___ 10 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ V 2528 tbl 04 NOTE: 1. At VCC < 2.0V input leakages are undefined. 3 6.42 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5V ± 10%) 7014S12 Com'l Only Symbol ICC Parameter Test Condition Dynamic Operating Current (Both Ports Active) Version Outputs Open f = fMAX(1) 7014S15 Com'l Only Typ. Max Typ. Max Unit mA COM'L S 160 250 160 250 IND S ____ ____ ____ ____ 2528 tbl 05a 7014S20 Com'l & Ind Symbol ICC Parameter Test Condition Dynamic Operating Current (Both Ports Active) Version Outputs Open f = fMAX(1) 7014S25 Com'l Only Typ. Max Typ. Max. Unit mA COM'L S 155 245 150 240 IND S 155 260 ____ ____ 2528 tbl 05b NOTES: 1. At f = fmax, address inputs are cycling at the maximum read cycle of 1/tRC using the "AC Test Conditions" input levels of GND to 3V. AC Test Conditions Input Pulse Levels 5V 5V GND to 3.0V Input Rise/Fall Times Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 893Ω 3ns Max. DATAOUT 893Ω DATAOUT 347Ω 30pF 5pF* 347Ω Figures 1,2 and 3 , 2528 tbl 06 2528 drw 04 Figure 1. AC Output Test Load. Capacitance(1) CIN COUT Parameter Input Capacitance Output Capacitance Figure 2. Output Test Load (for tHZ, tWZ, and tOW) *Including scope and jig. (TA = +25°C, f = 1.0MHz) TQFP Package Only Symbol 2528 drw 05 Conditions(2) Max. Unit VIN = 3dV 9 pF 7 VOUT = 3dV 10 pF 6 8 2528 tbl 07 NOTES: 1. This parameter is determined by device characteristics but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals swith from 0V to 3V or from 3V to 0V. tAA (Typical, ns) 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 2528 drw 06 Figure 3. Typical Output Derating (Lumped Capacitive Load). 4 , 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 7014S12 Com'l Only Symbol Parameter 7014S15 Com'l Only Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 ____ 15 ____ ns tAA Address Access Time ____ 12 ____ 15 ns tAOE Output Enable Access Time ____ 8 ____ 8 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns 3 ____ 3 ____ ns ____ 7 ____ 7 ns Output Low-Z Time tLZ (1,2) Output High-Z Time tHZ (1,2) 2528 tbl 08a 7014S20 Com'l & Ind Symbol Parameter 7014S25 Com'l Only Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ ns tAA Address Access Time ____ 20 ____ 25 ns tAOE Output Enable Access Time ____ 10 ____ 12 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns 3 ____ 3 ____ ns ____ 9 ____ 11 ns (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is determined by device characterization, but is not production tested. 5 6.42 2528 tbl 08b 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range Timing Waveform of Read Cycle No. 1, Either Side(1,2) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATA VALID DATA VALID 2528 drw 07 Timing Waveform of Read Cycle No. 2, Either Side(1, 3) tAOE OE tHZ tLZ VALID DATA DATAOUT NOTES: 1. R/W = VIH for Read Cycles. 2. OE = VIL. 3. Addresses valid prior to OE transition LOW. 2528 drw 08 Timing Waveform of Write with Port-to-Port Read(1,2) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tDH VALID ADDR"B" MATCH tWDD DATAOUT "B" VALID tDDD 2528 drw 09 NOTES: 1. R/W"B" = VIH, read cycle pass through. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is opposite from port "A". 6 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage 7014S12 Com'l Only Symbol Parameter 7014S15 Com'l Only Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 12 ____ 15 ____ ns tAW Address Valid to End-of-Write 10 ____ 14 ____ ns tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width 10 ____ 12 ____ ns tWR Write Recovery Time 1 ____ 1 ____ ns tDW Data Valid to End-of-Write 8 ____ 10 ____ ns ____ 7 ____ 7 ns 0 ____ 0 ____ ns Output High-Z Time tHZ (1,2) (3) tDH Data Hold Time tWZ Write Enable to Output in High-Z(1,2) ____ 7 ____ 7 ns tOW Output Active from End-of-Write (1,2,3) 0 ____ 0 ____ ns ____ 25 ____ 30 ns ____ 22 ____ 25 ns tWDD tDDD Write Pulse to Data Delay (4) Write Data Valid to Read Data Delay (4) 2528 tbl 09a 7014S20 Com'l & Ind Symbol Parameter 7014S25 Com'l Only Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 20 ____ 25 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ ns tAS Address Set-up Time 0 ____ 0 ____ ns tWP Write Pulse Width 15 ____ 20 ____ ns tWR Write Recovery Time 2 ____ 2 ____ ns tDW Data Valid to End-of-Write 12 ____ 15 ____ ns tHZ Output High-Z Time (1,2) ____ 9 ____ 11 ns tDH Data Hold Time (3) 0 ____ 0 ____ ns (1,2) ____ 9 ____ 11 ns (1,2,3) 0 ____ 0 ____ ns ____ 40 ____ 45 ns ____ 30 ____ 35 ns tWZ tOW Write Enable to Output in High-Z Output Active from End-of-Write (4) tWDD Write Pulse to Data Delay tDDD Write Data Valid to Read Data Delay (4) 2528 tbl 09b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”. 7 6.42 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range Timing Waveform of Write Cycle(1,2,3,4,5) ADDRESS OE tAW tWP (5) tAS tWR R/W tWZ (4) DATAOUT tOW (3) tHZ (4) (3) tDW tDH DATAIN 2528 drw 10 NOTES: 1. R/W must be HIGH during all address transitions. 2. tWR is measured from R/W going HIGH to the end of write cycle. 3. During this period, the I/O pins are in the output state, and input signals must not be applied. 4. Transition is measured 0mV from the Low or High-impedance voltage with the Output Test Load (Figure 2). 5. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Truth Table I – Read/Write Control Functional Description The IDT7014 provides two ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. It lacks the chip enable feature of CMOS Dual Ports, thus it operates in active mode as soon as power is applied. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. The user application should avoid simultaneous write operations to the same memory location. There is no on-chip arbitration circuitry to resolve write priority and partial data from both ports may be written. READ/WRITE conditions are illustrated in Table 1. Left or Right Port(1) R/W OE D0-8 L X DATAIN H L X H Function Data written into memory DATAOUT Data in memory output on port Z High-impedance outputs 2528 tbl 10 NOTE: 1. AOL - A11L is not equal to AOR - A11R. 'H' = HIGH,'L' = LOW, 'X' = Don’t Care, and 'Z' = HIGH Impedance. 8 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range Ordering Information XXXX Device Type A Power 999 Speed A Package A A Process/ Temperature Range A NOTES: Tube or Tray Tape and Reel Blank Commercial (0°C to +70°C) G(1) Green PF J 64-pin TQFP (PNG64) 52-pin PLCC (PLG52) 12 Commercial Only S Standard Power 7014 36K (4K x 9-Bit) Dual-Port RAM Speed in nanoseconds 2528 drw 11 1. Green parts avaliable. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 12 Blank 8 Pkg. Code Pkg. Type Temp. Grade 7014S12JG PLG52 PLCC C 7014S12JG8 PLG52 PLCC C 7014S12PFG PNG64 TQFP C 7014S12PFG8 PNG64 TQFP C Orderable Part ID Datasheet Document History 01/06/99: Page 2 06/03/99: Page 1 Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Changed drawing format Corrected DSC number 9 6.42 7014S High-Speed 4K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Range Datasheet Document History (con't) 03/10/00: Page 1 05/19/00: 10/16/01: Page 6 Page 3 Page 2 Pages 4, 5 & 7 Page 9 04/04/06: 12/11/08: 08/18/14: 03/16/16: Pages 1 & 9 Page 1 Page 9 Page 9 Page 9 Page 2 & 9 Page 2 Page 4 10/10/17: 05/14/19: Page 1 Page 2 Page 2 & 9 Page 9 Added Industrial Temperature Ranges and deleted corresponding notes Replaced IDT logo Made corrections to drawing Changed ±200mV to 0mV in notes Made changes to drawings Increased storage temperature parameter Clarified TA parameter Added date revision for pin configuration Removed Industrial temp values and column headings for 15 & 25ns speeds from DC and AC Electrical Characteristics Removed Industrial temp offering from 15 & 25ns ordering information Added Industrial temp footnote to ordering information Replaced TM logo with ® logo Added green availability to features Added green indicator to ordering information Removed "IDT" from orderable part number Added Tape and Reel to Ordering Information The package codes PN84-1 & J52-1 changed to PN84 & J52 respectively to match standard package codes Changed diagram for the PN64 pin configuration by rotating package pin labels and pin numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Removed the PN64 chamfer and aligned the top and bottom pin labels in the standard direction Added the IDT logo to the PN64 pin configurations and changed the text to be in alignment with new diagram marking specs Removed the date revision indicator for each pin configuration Updated footnote references for PN64 pin configuration Figure 3 Typical Output Derating Graph, corrected a typo Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Removed Industrial speed grade offering and updated Commercial speed grade offering in Features Changed diagram for the PLG52 pin configuration by rotating package pin labels and pin numbers 90 degrees clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Aligned the top and bottom pin labels in the standard direction Added the IDT logo to the PLG52 pin configuration and changed the text to be in alignment with new diagram marking specs Updated footnote references for PNG64 and PLG52 The package codes PN64 & J52 changed to PNG64 & PLG52 respectively to match standard package codes Removed Industrial speed grade offering and updated Commercial speed grade offering in Ordering Information Removed industrial temp footnote from ordering information Revised LEAD FINISH note to indicate Obsolete Added Orderable Part Information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 10 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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