7016L12PF8

HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM 7016L Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial:12ns (max.) Low-power operation – IDT7016L Active: 750mW (typ.) Standby: 1mW (typ.) IDT7016 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave Busy and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in a 68-pin PLCC Green parts available, see ordering information Functional Block Diagram OEL OER CEL R/WL CER R/WR I/O0L- I/O8L I/O0R-I/O8R I/O Control I/O Control (1,2) (1,2) BUSYL A13L A0L BUSYR Address Decoder MEMORY ARRAY 14 CEL OEL R/WL SEML (2) INTL A13R Address Decoder A0R 14 ARBITRATION INTERRUPT SEMAPHORE LOGIC CER OER R/WR SEMR (2) INTR M/S 3190 drw 01 NOTES: 1. In MASTER mode: BUSY is an output and is a push-pull driver In SLAVE mode: BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull drivers. MAY 2019 1 DSC 3190/13 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T Description address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7016 is packaged in a 64-pin PLCC. The IDT7016 is a high-speed 16K x 9 Dual-Port Static RAM. The IDT7016 is designed to be used as stand-alone Dual-Port RAMs or as a combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O7L I/O6L GND I/O5L I/O4L I/O3L I/O2L Pin Configurations(1,2,3) 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 27 9 28 8 29 7 30 31 6 33 34 4 3 7016 PLG68(4) 2 35 36 37 I/O1L I/O0L I/O8L OEL R/WL SEML CEL N/C A13L VCC A12L A11L A10L A9L A8L A7L A6L 5 32 1 68-Pin PLCC Top View 68 67 38 66 39 65 40 64 41 63 42 62 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 A4R A3R A2R A1R A0R INTR BUSYR M/S GND BUSYL INTL A0L A1L A2L A3L A4L A5L I/O7R I/O8R OER R/WR SEMR CER N/C A13R GND A12R A11R A10R A9R A8R A7R A6R A5R 3190 drw 02 Pin Names Left Port NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately .95 in x .95 in x .17 in. 4. This package code is used to reference the package diagram. Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O8L I/O0R - I/O8R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3190 tbl 01 2 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM NC NC VCC 70 69 A7L A6L NC A13L A9L A8L (con't.) 72 71 SEML CEL NC 79 78 77 76 OEL R/WL I/O1L I/O0L I/O8L 80 Military, Industrial and Commercial Temperature Range Commercial A12L A11L A10L Pin Configurations (1,2,3) 62 61 66 65 64 63 68 67 75 74 73 INDEX NC 1 60 NC I/O2L 2 59 I/O3L 3 58 A5L A4L I/O4L 4 57 A3L I/O5L 5 56 A2L GND 6 55 I/O6L 7 54 I/O7L 8 53 A1L A0L INTL VCC 9 52 BUSYL NC 10 51 GND GND 11 50 I/O0R 12 49 M/S BUSYR I/O1R 13 48 INTR I/O2R 14 47 VCC 15 46 A0R A1R I/O3R 16 45 A2R I/O4R 17 44 I/O5R 18 43 A3R A4R I/O6R 19 42 NC 20 41 IDT7016PF PN80(4) NC NC 40 39 37 38 36 35 33 34 32 30 31 29 27 28 26 24 25 22 23 21 80-Pin TQFP Top View(5) NC A6R A5R NC A7R A9R A8R A11R A10R A12R A13R GND NC NC CER R/WR SEMR I/O7R I/O8R OER , 3190 drw 03a 51 11 A5L 50 A4L 48 A2L 46 44 42 A0L BUSYL M/S 40 38 INTR A1R 36 A3R 49 A3L 47 A1L 45 43 41 39 37 INTL GND BUSYR A0R A2R 35 A4R 34 A5R 53 A7L 52 10 55 A9L 54 09 A8L 32 A7R 33 A6R 08 56 57 A11L A10L 30 A9R 31 A8R 07 58 59 VCC A12L IDT7016G G68(4) 29 28 A11R A10R 06 60 61 N/C A13L 68-Pin PGA Top View(5) 27 26 GND A12R 05 62 63 SEML CEL 24 N/C 04 64 65 OEL R/WL 23 22 SEMR CER 03 67 66 I/O0L I/O8L 20 OER 02 1 3 68 I/O1L I/O2L I/O4L NOTES: 01 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. A 3. PN80-1 package body is approximately INDEX 14mm x 14mm x 1.4mm. G68-1 package body is approximately 1.18 in x 1.18 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. A6L 2 4 I/O3L I/O5L 3 6.42 B C 25 A13R 21 R/WR 5 7 9 11 13 15 GND I/O7L GND I/O1R VCC I/O4R 18 19 I/O7R I/O8R 6 8 I/O6L VCC 17 I/O6R D E 10 12 14 16 I/O0R I/O2R I/O3R I/O5R F G H J K L 3190 drw 04a , 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs CE R/W OE SEM I/O0-8 H X X H High-Z Deselcted: Power-Down L L X H DATAIN Write to Memory L H L H DATAOUT X X H X High-Z Mode Read Memory Outputs Disabled 3190 tbl 02 NOTE: Condition: A0L — A13L ≠ A0R — A13R 1. Truth Table II: Semaphore Read/Write Control(1) Inputs Outputs CE R/W OE SEM I/O0-8 H H L L DATAOUT H ↑ X L DATAIN L X X L ____ Mode Read Semaphore Flag Data Out (I/O0 - I/O8) Write I/O0 into Semaphore Flag Not Allowed 3190 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2. Absolute Maximum Ratings(1) Symbol VTERM(2) TBIAS TSTG IOUT Rating Commercial & Industrial Military Unit Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V Temperature Under Bias -55 to +125 Storage Temperature -65 to +150 DC Output Current Maximum Operating Temperature and Supply Voltage(1) Grade Military 50 -65 to +135 -65 to +150 50 o o Commercial C Industrial C Ambient Temperature GND Vcc -55OC to +125OC 0V 5.0V + 10% 0OC to +70OC 0V 5.0V + 10% -40 C to +85 C 0V 5.0V + 10% O O NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. mA 3190 tbl 05 3190 tbl 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol Parameter VCC Supply Voltage GND Ground Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VIH Input High Voltage 2.2 ____ VIL Input Low Voltage -0.5(1) ____ NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. 4 6.42 Min. (2) 6.0 0.8 V V 3190 tbl 06 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial Capacitance (1) (TA = +25°C, f = 1.0mhz, for TQFP ONLY) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 3190 tbl 07 NOTES: 1. This parameter is determined by device characteristics but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V . DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7016S Symbol Parameter Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V |ILI| (1) Input Leakage Current |ILO| Test Conditions 7016L 3190 tbl 08 NOTE: 1. At Vcc < 2.0V, Input leakages are undefined. Output Loads and AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 3190 tbl 09 5V 5V 893Ω DATAOUT BUSY INT 893Ω DATAOUT 347Ω 30pF 5pF* 347Ω , 3190 drw 06 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig. 5 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%) 7016X12 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Typ.(2) Max. Typ. (2) Max. Unit COM'L S L 170 170 325 275 170 170 310 260 mA MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 25 25 70 60 25 25 60 50 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH COM'L S L 105 105 200 170 105 105 190 160 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ COM'L S L 100 100 180 150 100 100 170 140 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ Parameter Dynamic Operating Current (Both Ports Active) 7016X15 Com'l Only Test Condition Version CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CER = CEL = VIH SEMR = SEML = VIH f = fMAX(3) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) mA mA mA mA 3190 tbl 10 7016X20 Com'l, Ind & Military Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Test Condition Version 7016X25 Com'l & Military 7016X35 Com'l & Military Typ.(2) Max. Typ. (2) Max. Typ.(2) Max. Unit mA CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) COM'L S L 160 160 290 240 155 155 265 220 150 150 250 210 MIL & IND S L 160 160 380 310 155 155 340 280 150 150 300 250 Standby Current (Both Ports - TTL Level Inputs) CER = CEL = VIH SEMR = SEML = VIH f = fMAX(3) COM'L S L 20 20 60 50 16 16 60 50 13 13 60 50 MIL & IND S L 20 20 80 65 16 16 80 65 13 13 80 65 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH COM'L S L 95 95 180 150 90 90 170 140 85 85 155 130 MIL & IND S L 95 95 240 210 90 90 215 180 85 85 190 160 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 90 90 155 130 85 85 145 120 80 80 135 110 MIL & IND S L 90 90 230 200 85 85 200 170 80 80 175 150 NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA(typ.) 3. At f = fMAX, address and I/Os are cycling at the maximum frequency read cycle of 1/tRC. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". 6 6.42 mA mA mA mA 3190 tbl 11 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 7016X12 Com'l Only Symbol Parameter 7016X15 Com'l Only Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 ____ 15 ____ ns tAA Address Access Time ____ 12 ____ 15 ns tACE Chip Enable Access Time (3) ____ 12 ____ 15 ns tAOE Output Enable Access Time ____ 8 ____ 10 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ ns tHZ Output High-Z Time (1,2) ____ 10 ____ 10 ns 0 ____ 0 ____ ns (2) tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time (2) ____ 12 ____ 15 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 10 ____ ns tSAA Semaphore Address Access Time ____ 12 ____ 15 ns 3190 tbl 12a Symbol Parameter 7016X35 Com'l & Military 7016X25 Com'l & Military 7016X20 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time (3) ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 12 ____ 13 ____ 20 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ ns ____ 12 ____ 15 ____ 20 ns 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 25 ____ 35 ns (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) tPU Chip Enable to Power Up Time (2) (2) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 10 ____ 10 ____ ns tSAA Semaphore Address Access Time ____ 20 ____ 25 ____ 35 ns NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). 7 6.42 3190 tbl 12b 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T Waveform of Read Cycles(5) tRC ADDR (4) tAA (4) tACE CE tAOE (4) OE R/W tLZ tOH (1) (4) DATAOUT VALID DATA tHZ (2) BUSYOUT tBDD (3,4) 3190 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD. 5. SEM = VIH. Timing of Power-Up / Power-Down CE tPU tPD ICC 50% 50% ISB , 3190 drw 08 8 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7016X12 Com'l Only Symbol Parameter 7016X15 Com'l Only Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 12 ____ 15 ____ ns tEW Chip Enable to End-of-Write (3) 10 ____ 12 ____ ns tAW Address Valid to End-of-Write 10 ____ 12 ____ ns 0 ____ 0 ____ ns ns (3) tAS Address Set-up Time tWP Write Pulse Width 10 ____ 12 ____ tWR Write Recovery Time 2 ____ 2 ____ ns tDW Data Valid to End-of-Write 10 ____ 10 ____ ns tHZ Output High-Z Time (1,2) ____ 10 ____ 10 ns tDH Data Hold Time (4) 0 ____ 0 ____ ns (1,2) ____ 10 ____ 10 ns (1,2,4) 3 ____ 3 ____ ns 5 ____ ns 5 ____ ns tWZ Write Enable to Output in High-Z tOW Output Active from End-of-Write tSWRD SEM Flag Write to Read Time 5 ____ tSPS SEM Flag Contention Window 5 ____ 3190 tbl 13a 7016X20 Com'l, Ind & Military Symbol Parameter 7016X25 Com'l & Military 7016X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 20 ____ 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write (3) 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns 0 ____ 0 ____ 0 ____ ns ns (3) tAS Address Set-up Time tWP Write Pulse Width 15 ____ 20 ____ 25 ____ tWR Write Recovery Time 2 ____ 2 ____ 2 ____ ns tDW Data Valid to End-of-Write 15 ____ 15 ____ 15 ____ ns ____ 12 ____ 15 ____ 20 ns 0 ____ 0 ____ 0 ____ ns ____ 12 ____ 15 ____ 20 ns 3 ____ 3 ____ 3 ____ ns SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns SEM Flag Contention Window 5 ____ 5 ____ 5 ____ ns (1,2) tHZ Output High-Z Time tDH Data Hold Time (4) tWZ Write Enable to Output in High-Z(1,2) tOW (1,2,4) tSWRD tSPS Output Active from End-of-Write 3190 tbl 13b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). 9 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW (9) CE or SEM tWP (2) tAS (6) tWR (3) R/W tLZ DATAOUT tWZ (7) tOW (4) (4) tDW tDH DATAIN 3190 drw 09 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9) (6) tAS tEW (2) tWR (3) R/W tDW tDH DATAIN 3190 drw 10 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 10 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA VALID ADDRESS VALID ADDRESS A0-A2 tWR tAW tACE tEW SEM tOH tDW DATAIN VALID I/O tAS tWP tSOP DATAOUT VALID(2) tDH R/W tAOE tSWRD OE Read Cycle Write Cycle 3190 drw 11 NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value. Timing Waveform of Semaphore Write Condition(1,3,4) A0"A"-A2 "A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2 "B" (2) SIDE "B" MATCH R/W"B" SEM"B" 3190 drw 12 NOTES: 1. DOR = DOL =VIH, CER = CEL =VIH. 2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”. 3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. 11 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 7016X12 Com'l Only Symbol Parameter 7016X15 Com'l Only Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 12 ____ 15 ns BUSY Disable Time from Address Not Matched ____ 12 ____ 15 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 12 ____ 15 ns tBDC BUSY Disab le Time from Chip Enable High ____ 12 ____ 15 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 15 ____ 18 ns 11 ____ 13 ____ ns 0 ____ 0 ____ ns 11 ____ 13 ____ ns ns BUSY TIMING (M/S = VIH) tBAA tBDA tWH (5) Write Hold After BUSY BUSY INPUT TIMING (M/S = VIL) BUSY Input to Write (4) tWB tWH (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 25 ____ 30 tDDD Write Data Valid to Read Data Delay (1) ____ 20 ____ 25 ns 3190 tbl 14a 7016X20 Com'l, Ind & Military Symbol Parameter 7016X25 Com'l & Military 7016X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S = VIH) tBAA BUSY Access Time from Address Match ____ 20 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 20 ____ 20 ____ 20 ns BUSY Acce ss Time from Chip Enable Low ____ 20 ____ 20 ____ 20 ns tBDC BUSY Disab le Time from Chip Enable High ____ 17 ____ 17 ____ 20 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data(3) ____ 30 ____ 30 ____ 35 ns 15 ____ 17 ____ 25 ____ ns 0 ____ 0 ____ 0 ____ ns 15 ____ 17 ____ 25 ____ ns tBAC tWH (5) Write Hold After BUSY BUSY INPUT TIMING (M/S = VIL) tWB tWH BUSY Input to Write (4) (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 45 ____ 50 ____ 60 ns tDDD Write Data Valid to Read Data Delay (1) ____ 30 ____ 35 ____ 45 ns 3190 tbl 14b NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A". 5. To ensure that a write cycle is completed on Port "B" after contention on Port "A". 6. 'X' in part numbers indicates power rating (S or L). 12 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) tWC MATCH ADDR"A" tWP R/W"A" tDH tDW VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL. 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". Timing Waveform of Write with BUSY(3) tWP R/W"A" tWB BUSY"B" tWH R/W"B" (1) (2) 3190 drw 14 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". 13 6.42 3190 drw 13 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 3190 drw 15 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDRESS "N" ADDR"A" tAPS (2) MATCHING ADDRESS "N" ADDR"B" tBAA tBDA BUSY"B" 3190 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 7016X12 Com'l Only Symbol Parameter 7016X15 Com'l Only Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 12 ____ 15 ns tINR Interrupt Reset Time ____ 12 ____ 15 ns 3190 tbl 15a 7016X20 Com'l, Ind & Military Symbol Parameter 7016X25 Com'l & Military 7016X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 20 ____ 20 ____ 25 ns tINR Interrupt Reset Time ____ 20 ____ 20 ____ 25 ns 3190 tbl 15b NOTES: 1. 'X' in part numbers indicates power rating (S or L). 14 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial Waveform of Interrupt Timing(1) tWC ADDR"A" INTERRUPT SET ADDRESS tAS (2) (3) tWR (4) CE"A" R/W"A" tINS (3) INT"B" 3190 drw 17 tRC ADDR"B" INTERRUPT CLEAR ADDRESS tAS (2) (3) CE"B" OE"B" tINR (3) INT"B" 3190 drw 18 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt truth table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. Truth Table III — Interrupt Flag(1) Left Port R/WL L X X X CEL L X X L OEL X X X L Right Port A13L-A0L 3FFF X X 3FFE INTL X R/WR X CER X OER X A13R-A0R X INTR Function (2) Set Right INTR Flag (3) L X L L 3FFF H Reset Right INTR Flag (3) L L X 3FFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag X L H 3190 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 15 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T Truth Table IV — Address BUSY Arbitration Inputs Outputs CEL CER AOL-A13L AOR-A13R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 3190 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7016 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D8 Left D0 - D8 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7016. 2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2. e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table. Functional Description The IDT7016 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7016 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FFE 3190 tbl 18 where a write is defined as the CE = R/W = VIL per Truth Table III. The left port clears the interrupt by an address location 3FFE access when CER =OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFF and to clear the interrupt flag (INTR), the right port must access memory location 3FFF. The message (9 bits) at 3FFE or 3FFF is user-defined since it is in an addressable SRAM location. If the interrupt function is not used, address locations 3FFE and 3FFF are not used as mail boxes but are still part of the random access memory. Refer to Truth Table III for the interrupt operation. 16 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7016 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion Busy Logic Master/Slave Arrays When expanding an IDT7016 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT7016 RAM the BUSY pin is an output if the part is used as a master (M/S pin = H), and the BUSY pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7016 are extremely fast Dual-Port 16Kx9 Static RAMs with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the BUSY (L) CE MASTER Dual Port RAM BUSY (L) BUSY (R) CE SLAVE Dual Port RAM BUSY (L) BUSY (R) MASTER CE Dual Port RAM BUSY (L) BUSY (R) SLAVE CE Dual Port RAM BUSY (L) BUSY (R) DECODER Military, Industrial and Commercial Temperature Range Commercial BUSY (R) 3190 drw 19 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7016 RAMs. left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT7016 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7016's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7016 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to 17 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7016 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7016’s Dual-Port RAM. Say the 16K x 9 RAM was to be divided into two 8K x 9 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 8K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 8K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 8K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 8K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the 18 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D SEMAPHORE REQUEST FLIP FLOP Q Q D WRITE D0 WRITE SEMAPHORE READ SEMAPHORE READ 3190 drw 20 Figure 4. IDT7016 Semaphore Logic 19 6.42 , 7016L High-Speed 16K x 9 Dual-Port Static RAM Commercial Military, Industrial and Commercial Temperature RangeT T Ordering Information A XXXXX A 999 A Device Type Power Speed Package A A Process/ Temperature Range Blank 8 Tube Tape and Reel Blank Commercial (0°C to +70°C) G(1) Green J 68-pin PLG68 12 Commercial L Low Power 7016 144K (16K x 9) Dual-Port RAM Speed in Nanoseconds 3190 drw 21b NOTES: 1. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 12 Pkg. Code Pkg. Type Temp. Grade 7016L12JG PLG68 PLCC C 7016L12JG8 PLG68 PLCC C Orderable Part ID 20 6.42 7016L High-Speed 16K x 9 Dual-Port Static RAM Military, Industrial and Commercial Temperature Range Commercial Datasheet Document History 01/11/99: Pages 2 and 3 06/03/99 Page 1 11/10/99: 05/19/00: Page 4 Page 6 01/10/02: 04/04/06: 01/09/09: 10/03/14: Pages 2 & 3 Pages 4, 6, 7, 9 & 12 Pages 6, 7, 9, 12 & 14 Page 20 Pages 1 & 20 Page 1 Page 20 Page 20 Page 20 Page 2, 3, 4 & 20 10/10/14: Page 20 Page 1 04/05/19: Page 2 Page 20 05/28/19: Page 1 & 20 Page 2 Page 20 Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Changed drawing format Corrected DSC number Replaced IDT logo Increased storage temperature parameter Clarified TA parameter DC Electrical parameters–changed wording from open to disabled Changed ±200mV to 0mV in notes Added date revision for pin configurations Removed Industrial temp footnote from all tables Added Industrial temp for 20ns speed to DC and AC Electrical Characteristics Added Industrial temp offering to 20ns ordering information Replaced TM logo with ® logo Added green availability to features Added indicator to ordering information Removed "IDT" from orderable part number Added Tape and Reel to Ordering Information The package codes PN80-1, G68-1 & J68-1 changed to PN80, G68 & J68 respectively to match standard package codes Corrected two typos Updated Features by removing all speed grades offerings except the commercial 12ns and by removing the Industrial & Military temp range offerings Description updated the text by removing "IDT's" from the fabricating high-performance technology Additionally updated the Description text by removing the ceramic 68-pin PGA and the 80-pin TQFP and package offerings The package code J68 for the 68-Pin PLCC Pin Configuration changed to PLG68 in order to match that of the standard green package code Ordering Information updated by removing the Industrial & Military temp range offerings and by removing the PN80 and the G68 package offerings Ordering Information footnotes updated by removing the Industrial temp sales information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Removed Standard power offering from Features and Ordering Information Changed diagram for the J68 pin configuration by rotating package pin labels and pin numbers 90 degrees clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1 Removed J68 chamfer and aligned the top and bottom pin labels in the standard direction The package code J68 changed to PLG68 to match standard package code Revised LEAD FINISH note by removing the "excluding BGA and Hermetic packages" Added Orderable Part Information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 21 6.42 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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