7024L15JG8

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/17/20/25/35/55ns (max.) – Industrial: 20ns (max.) – Military: 20/25/35/55/70ns (max.) Low-power operation – IDT7024S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7024L Active: 750mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 7024S/L IDT7024 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Battery backup operation—2V data retention TTL-compatible, single 5V (±10%) power supply Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin Quad Flatpack Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram R/WL UBL R/WR UBR LBL CEL OEL LBR CER OER I/O8L-I/O15L I/O8R-I/O15R I/O Control I/O0L-I/O7L I/O Control I/O0R-I/O7R (1,2) (1,2) BUSYL A11L A0L BUSYR Address Decoder MEMORY ARRAY 12 CEL OEL R/WL SEML (2) INTL A11R A0R 12 ARBITRATION INTERRUPT SEMAPHORE LOGIC M/S NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. CER OER R/WR SEMR INTR(2) 2740 drw 01 1 Feb.20.20 Address Decoder 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7024 is a high-speed 4Kx 16 Dual-Port Static RAM. The IDT7024 is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by chip enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500µW from a 2V battery. The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack and PLCC, and a 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL A11L 77 A10L A9L A5R A6R A4R A3R A2R A1R A0R INTR M/S BUSYR GND A1L A0L A2L A11R 80 UBL CEL 48 N/C 81 82 SEML R/WL 47 46 LBR UBR 83 84 45 CER SEMR VCC OEL 1 2 I/O0L I/O1L 3 GND I/O2L A10L A11L N/C LBL 7024 FP84(4) 44 43 42 84-Pin Flatpack Top View 4 41 A7R A8R A9R A10R GND R/WR OER 40 I/O15R 5 6 39 GND I/O3L I/O4L 7 8 38 I/O14R 37 I/O5L 9 I/O13R I/O12R 36 6.42 2 I/O7R I/O8R I/O5R I/O6R I/O4R I/O3R VCC I/O1R I/O2R GND I/O0R I/O15L VCC I/O14L I/O13L GND I/O12L I/O11L I/O8L 35 10 34 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 I/O10L I/O6L I/O7L Feb.20.20 A4L A3L 7574 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 5453 76 52 77 51 78 50 79 49 A8L A9L NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. PLG84 package body is approximately 1.15 in x 1.15 in x .17 in. FP84 package body is approximately 1.17 in x 1.17 in x .11 in. 4. This package code is used to reference the package diagram. A5L A7L A6L 2740 drw 02J INTL BUSYL A8L I/O9L I/O9L I/O10L I/O12L I/O11L I/O14L GND I/O13L VCC I/O15L GND I/O0R VCC I/O2R I/O1R I/O3R I/O4R I/O5R I/O8L I/O4L 78 A6L A7L A5L I/O5L LBL N/C 76 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 7475 A4L I/O7L I/O6L 80 79 52 A6R A7R 51 A3L A8R 49 50 A2L A10R A9R 48 A1L N/C A11R INTL A0L CER UBR LBR BUSYL SEMR M/S R/WR GND GND OER INTR BUSYR GND I/O15R A1R A0R I/O14R A3R A2R I/O12R I/O13R 3332 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 34 10 35 9 36 8 37 7 38 6 39 5 40 4 41 3 7024 42 2 PLG84(4) 43 1 44 84 84-Pin PLCC 45 83 Top View 46 82 47 81 A5R A4R I/O9R I/O10R I/O11R I/O7R I/O6R I/O8R Pin Configurations(1,2,3) I/O11R I/O10R I/O9R 2740 drw 02F 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges (con't.) N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C Pin Configurations (1,2,3) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 78 79 81 46 45 82 83 44 43 84 42 41 80 85 40 86 7024 PNG100(4) 87 88 89 90 91 39 38 37 36 100-Pin TQFP Top View 92 35 34 93 33 32 94 95 96 31 97 98 29 28 99 100 1 2 A5R A6R A7R A8R A9R A10R A11R N/C LBR UBR CER SEMR GND R/WR OER I/O15R GND I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O8R I/O7R 48 47 30 3 4 5 6 7 8 27 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 63 11 61 I/O7L 66 10 I/O10L 67 09 08 2740 drw 03 06 I/O13L I/O15L 49 I/O1L 50 46 LBL 47 CEL UBL 53 GND 48 SEML 45 A11L 44 N/C A9L VCC I/O2R 32 GND VCC 28 A0R 7 GND I/O7R 1 2 I/O9R 3 I/O11R A B 11 5 8 INTR I/O10R I/O13R I/O15R 6 9 C I/O14R D 14 OER E UBR R/WR 15 13 22 20 A11R 16 A8R 18 LBR CER N/C F G H J A3R 24 A6R 19 A10R A1R 25 A5R 17 BUSYR 27 23 SEMR GND 10 4 I/O12R 12 A1L 30 A2R 83 I/O8R M/S 26 I/O4R I/O6R 36 29 80 I/O5R INTL A0L 31 GND 84-Pin PGA Top View(5) 78 A2L 34 35 BUSYL 7024 GU84(4) 74 GND I/O3R A4L 37 A3L 33 A5L 39 A6L 73 I/O14L I/O1R A8L 41 R/WL A7L 40 43 52 VCC 42 A10L 38 77 84 01 51 OEL I/O12L I/O0R 82 02 I/O3L I/O9L 70 81 03 56 57 71 79 04 I/O6L 54 I/O0L 68 76 05 55 I/O2L 59 62 I/O8L I/O11L 75 NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. PNG100 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 58 I/O4L 65 72 07 60 I/O5L 64 69 N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C A6L A7L A8L A9L A10L A11L N/C LBL UBL CEL SEML R/WL VCC OEL I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L I/O9L A4R 21 A9R K A7R L 2740 drw 04 Index NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. GU84 package body is approximately 1.12 in x 1.12 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Pin Names Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A11L A0R - A11R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground Maximum Operating Temperature and Supply Voltage(1) Grade Military Commercial Industrial GND Vcc -55OC to +125OC 0V 5.0V + 10% 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% 2740 tbl 02 NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. 2740 tbl 01 6.42 3 Feb.20.20 Ambient Temperature , 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs CE R/W OE UB LB SEM I/O8-15 I/O0-7 Mode H X X X X H High-Z High-Z Deselcted: Power-Down X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H High-Z DATA OUT Read Lower Byte Only L H L L L H DATAOUT DATA OUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled 2740 tbl 03 NOTE: 1. A0L — A11L ≠ A0R — A11R Truth Table II: Semaphore Read/Write Control(1) Inputs(1) (2) Outputs R/W OE UB LB SEM I/O8-15 I/O0-7 H H L X X L DATAOUT DATAOUT Read Semaphore Flag Data Out X H L H H L DATAOUT DATAOUT Read Semaphore Flag Data Out H ↑ X X X L DATAIN DATAIN Write I/O0 into Semaphore Flag X ↑ X H H L DATAIN DATAIN Write I/O0 into Semaphore Flag L X X L X L ____ ____ Not Allowed L X X X L L ____ ____ Not Allowed CE Mode 2740 tbl 04 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all of the I/O's (I/O0 - I/O15). These eight semaphores are addressed by A0 - A2. Recommended DC Operating Conditions Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Military Unit Symbol VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 -65 to +135 o C TSTG Storage Temperature -65 to +150 -65 to +150 o C IOUT DC Output Current 50 50 2740 tbl 05 6.42 4 Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V V VCC Supply Voltage GND Ground VIH Input High Voltage 2.2 ____ 6.0(2) VIL Input Low Voltage -0.5(1) ____ 0.8 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc +10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period over VTERM > Vcc + 10%. Feb.20.20 Parameter V 2740 tbl 06 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance (1) Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 2740 tbl 07 NOTES: 1. This parameter are determined by device characterization, but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7024S Symbol Parameter Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ |ILI| (1) Input Leakage Current |ILO| Test Conditions 7024L V 2740 tbl 08 NOTE: 1. At Vcc < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%) 7024X15 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition Version 7024X17 Com'l Only 7024X20 Com'l, Ind & Military 7024X25 Com'l & Military Typ. (2) Max. Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit mA CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) COM'L S L 170 170 310 260 170 170 310 260 160 160 290 240 155 155 265 220 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 160 160 370 320 155 155 340 280 CER = CEL = VIH SEMR = SEML = VIH f = fMAX(3) COM'L S L 20 20 60 50 20 20 60 50 20 20 60 50 16 16 60 50 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 20 20 90 70 16 16 80 65 COM'L S L 105 105 190 160 105 105 190 160 95 95 180 150 90 90 170 140 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 95 95 240 210 90 90 215 180 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 COM'L S L 100 100 170 140 100 100 170 140 90 90 155 130 85 85 145 120 MIL & IND S L ____ ____ ____ ____ ____ ____ ____ ____ 90 90 225 200 85 85 200 170 CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(3) mA mA mA mA 2740 tbl 09a NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VCC = 5V, TA = +25°C, and are not production tested. ICC DC = 120mA (TYP.) 3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.42 5 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (con’t.) (VCC = 5.0V ± 10%) 7024X35 Com'l & Military Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Dynamic Operating Current (Both Ports Active) CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) Standby Current (Both Ports - TTL Level Inputs) CER = CEL = VIH SEMR = SEML = VIH f = fMAX(3) Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH Full Standby Current (Both Ports CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V Full Standby Current (One Port CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(3) Version 7024X55 Com'l, Ind & Military 7024X70 Military Only Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit ____ mA COM'L S L 150 150 250 210 150 150 250 210 ____ ____ ____ MIL & IND S L 150 150 300 250 150 150 300 250 140 140 300 250 COM'L S L 13 13 60 50 13 13 60 50 ____ ____ ____ ____ MIL & IND S L 13 13 80 65 13 13 80 65 10 10 80 65 COM'L S L 85 85 155 130 95 95 155 130 ____ ____ ____ ____ MIL & IND S L 85 85 190 160 95 95 190 160 80 80 190 160 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 ____ ____ ____ ____ MIL & IND S L 1.0 0.2 30 10 1.0 0.2 30 10 1.0 0.2 30 10 COM'L S L 80 80 135 110 80 80 135 110 ____ ____ ____ ____ MIL & IND S L 80 80 175 150 80 80 175 150 75 75 175 150 NOTES: 1. 'X' in part number indicates power rating (S or L) 2. VCC = 5V, TA = +25°C, and are not production tested. 3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". mA mA mA mA 2740 tbl 09b Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)(4) Symbol Parameter Test Condition Min. Typ.(1) Max. Unit 2.0 ___ ___ V µA VDR VCC for Data Retention VCC = 2V ICCDR Data Retention Current CE > VHC MIL. & IND. ___ 100 4000 VIN > VHC or < VLC COM'L. ___ 100 1500 0 ___ ___ ns tRC(2) ___ ___ ns tCDR (3) tR(3) Chip Deselect to Data Retention Time SEM > VHC Operation Recovery Time NOTES: 1. TA = +25°C, VCC = 2V, and are by device characterization but are not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not tested. 4. At Vcc < 2.0V, input leakages are not defined. 6.42 6 Feb.20.20 2740 tbl 10 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Data Retention Waveform DATA RETENTION MODE VDR ≥ 2V 4.5V VCC 4.5V tCDR tR VDR VIH CE VIH 2740 drw 05 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2740 tbl 11 5V 5V 1250Ω DATAOUT BUSY INT 1250Ω DATAOUT 775Ω 30pF 775Ω 5pF* 2740 drw 06 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and Jig 6.42 7 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 7024X15 Com'l Only Symbol Parameter 7024X17 Com'l Only 7024X20 Com'l, Ind & Military 7024X25 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 17 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 17 ____ 20 ____ 25 ns Chip Enable Access Time (3) ____ 15 ____ 17 ____ 20 ____ 25 ns tABE Byte Enable Access Time (3) ____ 15 ____ 17 ____ 20 ____ 25 ns tAOE Output Enable Access Time ____ 10 ____ 10 ____ 12 ____ 13 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ 3 ____ ns ____ 10 ____ 10 ____ 12 ____ 15 ns 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 15 ____ 17 ____ 20 ____ 25 ns 10 ____ 10 ____ 10 ____ 10 ____ ns ____ 15 ____ 17 ____ 20 ____ 25 ns tACE tLZ Output Low-Z Time tHZ (1,2) Output High-Z Time (1,2) (1,2) tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time (1,2) tSOP Semaphore Flag Update Pulse (OE or SEM) tSAA Semaphore Address Access (3) 2740 tbl 12a 7024X35 Com'l & Military Symbol Parameter 7024X55 Com'l, Ind & Military 7024X70 Military Only Min. Max. Min. Max. Min. Max. Unit 35 ____ 55 ____ 70 ____ ns READ CYCLE tRC Read Cycle Time tAA Address Access Time ____ 35 ____ 55 ____ 70 ns Chip Enable Access Time (3) ____ 35 ____ 55 ____ 70 ns tABE Byte Enable Access Time (3) ____ 35 ____ 55 ____ 70 ns tAOE Output Enable Access Time ____ 20 ____ 30 ____ 35 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ 3 ____ ns tHZ (1,2) ____ 15 ____ 25 ____ 30 ns 0 ____ 0 ____ 0 ____ ns ____ 35 ____ 50 ____ 50 ns 15 ____ 15 ____ 15 ____ ns ____ 35 ____ 55 ____ 70 tACE tPU Output High-Z Time Chip Enab le to Power Up Time (1,2) (1,2) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) tSAA Semaphore Address Access (3) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM =VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM =VIL. 4. 'X' in part number indicates power rating (S or L). 6.42 8 Feb.20.20 ns 2740 tbl 12b 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Read Cycles (5) tRC ADDR (4) tAA (4) tACE CE tAOE (4) OE tABE (4) UB, LB R/W tOH tLZ (1) (4) DATAOUT VALID DATA tHZ (2) BUSYOUT tBDD (3,4) 2740 drw 07 NOTES: 1. Timing depends on which signal is asserted last, CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. tBDD delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH. Timing of Power-Up Power-Down CE ICC tPU tPD ISB , 2740 drw 08 6.42 9 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7024X15 Com'l Only Symbol Parameter 7024X17 Com'l Only 7024X25 Com'l & Military 7024X20 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 15 ____ 17 ____ 20 ____ 25 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 12 ____ 15 ____ 20 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns ns (3) tAS Address Set-up Time tWP Write Pulse Width 12 ____ 12 ____ 15 ____ 20 ____ tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 10 ____ 15 ____ 15 ____ ns ____ 10 ____ 10 ____ 12 ____ 15 ns 0 ____ 0 ____ 0 ____ 0 ____ ns ____ Output High-Z Time tHZ Data Hold Time tDH (1,2) (4) (1,2) tWZ Write Enab le to Output in High-Z 10 ____ 10 ____ 12 ____ 15 ns tOW Output Active from End-of-Write (1,2,4) 0 ____ 0 ____ 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ 5 ____ 5 ____ ns 2740 tbl 13a 7024X35 Com'l & Military Symbol Parameter 7024X55 Com'l, Ind & Military 7024X70 Military Only Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 35 ____ 55 ____ 70 ____ ns tEW Chip Enable to End-of-Write (3) 30 ____ 45 ____ 50 ____ ns tAW Address Valid to End-of-Write 30 ____ 45 ____ 50 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 25 ____ 40 ____ 50 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 15 ____ 30 ____ 40 ____ ns ____ 15 ____ 25 ____ 30 ns 0 ____ 0 ____ 0 ____ ns (1,2) ____ 15 ____ 25 ____ 30 ns (1,2,4) 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ ns 5 ____ 5 ____ tHZ Output High-Z Time tDH Data Hold Time (4) tWZ (1,2) Write Enab le to Output in High-Z tOW Output Active from End-of-Write tSWRD SEM Flag Write to Read Time 5 ____ SEM Flag Contention Window 5 ____ tSPS NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part number indicates power rating (S or L). 6.42 10 Feb.20.20 ns 2740 tbl 13b 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW (9) CE or SEM (9) UB or LB tWP (2) tAS (6) tWR (3) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 2740 drw 09 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS tAW (9) CE or SEM tAS(6) tWR (3) tEW (2) (9) UB or LB R/W tDW tDH DATAIN 2740 drw 10 NOTES: 1. R/W or CE or UB & LB = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH = VIL to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP for (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met for either condition. 6.42 11 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tOH tSAA A0-A2 VALID ADDRESS tWR tAW tEW VALID ADDRESS tACE SEM tSOP tDW DATAIN VALID I/O0 tAS tWP DATAOUT VALID(2) tDH R/W tSWRD tAOE OE Write Cycle Read Cycle 2740 drw 11 NOTES: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. “DATAOUT VALID” represents all I/O's (I/O0-I/O15) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 2740 drw 12 NOTES: 1. D0R = D0L = VIL, CER = CEL = VIH, or both UB & LB = VIH, semaphore flag is released from both sides (reads as ones from both sides) at cycle start. 2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. 6.42 12 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 7024X15 Com'l Only Symbol Parameter 7024X17 Com'l Only 7024X20 Com'l, Ind & Military 7024X25 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 15 ____ 17 ____ 20 ____ 20 ns BUSY Disable Time from Address Not Match ____ 15 ____ 17 ____ 20 ____ 20 ns BUSY Access Time from Chip Enable Low ____ 15 ____ 17 ____ 20 ____ 20 ns BUSY Disable Time from Chip Enable High ____ 15 ____ 17 ____ 17 ____ 17 ns 5 ____ 5 ____ 5 ____ 5 ____ ns BUSY TIMING (M/S = VIH) tBAA tBDA tBAC tBDC tAPS Arbitration Priority Set-up Time (2) (3) tBDD BUSY Disable to Valid Data ____ 18 ____ 18 ____ 30 ____ 30 ns tWH Write Hold After BUSY(5) 12 ____ 13 ____ 15 ____ 17 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 12 ____ 13 ____ 15 ____ 17 ____ ns BUSY INPUT TIMING (M/S = VIH) BUSY Input to Write (4) tWB tWH (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 30 ____ 30 ____ 45 ____ 50 ns tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 25 ____ 35 ____ 35 ns 2740 tbl 14a 7024X35 Com'l & Military Symbol Parameter 7024X55 Com'l, Ind & Military 7024X70 Military Only Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 20 ____ 45 ____ 45 ns BUSY TIMING (M/S = VIH) tBAA BUSY Disable Time from Address Not Match ____ 20 ____ 40 ____ 40 ns tBAC BUSY Access Time from Chip Enable Low ____ 20 ____ 40 ____ 40 ns tBDC BUSY Disable Time from Chip Enable High ____ 20 ____ 35 ____ 35 ns tAPS Arbitration Priority Set-up Time (2) tBDD BUSY Disable to Valid Data(3) tBDA tWH (5) Write Hold After BUSY 5 ____ 5 ____ 5 ____ ns ____ 35 ____ 40 ____ 45 ns 25 ____ 25 ____ 25 ____ ns BUSY INPUT TIMING (M/S = VIH) tWB BUSY Input to Write (4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 25 ____ 25 ____ 25 ____ ns ____ 60 ____ 80 ____ 95 ns ____ 45 ____ 65 ____ 80 PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay(1) Write Data Valid to Read Data Delay (1) NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port 'B' during contention with port 'A'. 5. To ensure that a write cycle is completed on port 'B' after contention with port 'A'. 6. 'X' in part number indicates power rating (S or L). 6.42 13 Feb.20.20 ns 2740 tbl 14b 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5) (M/S = VIH) tWC MATCH ADDR"A" tWP R/W"A" tDH tDW VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave) then BUSY is an input BUSY"A" = VIL and BUSY"B" = don't care, for this example. 5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". Timing Waveform of Write with BUSY tWP R/W"A" tWB(3) BUSY"B" tWH R/W"B" (1) , (2) 2740 drw 14 NOTES: 1. tWH must be met for both BUSY input (slave) and output (master). 2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the 'Slave' Version. 6.42 14 Feb.20.20 2740 drw 13 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 2740 drw 15 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" ADDRESS "N" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 2740 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 7024X15 Com'l Only Symbol Parameter 7024X17 Com'l Only 7024X20 Com'l , Ind & Military 7024X25 Com'l & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit 0 ____ 0 ____ 0 ____ 0 ____ ns INTERRUPT TIMING tAS Address Set-up Time tWR Write Recovery Time tINS tINR 0 ____ 0 ____ 0 ____ 0 ____ ns Interrupt Set Time ____ 15 ____ 15 ____ 20 ____ 20 ns Interrupt Reset Time ____ 15 ____ 15 ____ 20 ____ 20 ns 2740 tbl 15a 7024X35 Com'l & Military Symbol Parameter 7024X55 Com'l, Ind & Military 7024X70 Military Only Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 40 ____ 50 ns tINR Interrupt Reset Time ____ 25 ____ 40 ____ 50 ns 2740 tbl 15b NOTES: 1. 'X' in part number indicates power rating (S or L). 6.42 15 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC ADDR"A" INTERRUPT SET ADDRESS (2) tAS (3) tWR (4) CE"A" R/W"A" tINS (3) INT"B" 2740 drw 17 tRC INTERRUPT CLEAR ADDRESS ADDR"B" tAS (2) (3) CE"B" OE"B" tINR(3) INT"B" 2740 drw 18 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. Truth Table III — Interrupt Flag(1,4) Left Port R/WL L X X X CEL L X X L OEL X X X L Right Port A11L-A0L FFF X X FFE INTL X R/WR X CER X X A11R-A0R X INTR Function (2) Set Right INTR Flag (3) L X L L FFF H Reset Right INTR Flag (3) L L X FFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag X L H 2740 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTR and INTL must be initialized at power-up. 6.42 16 Feb.20.20 OER 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration Inputs Outputs CEL CER A0L-A11L A0R-A11R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 2740 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7024 are push pull, not open drain outputs. On slaves, the BUSY asserted input internally inhibits write. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D15 Left D0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024. 2. There are eight semaphore flags written to via I/O0 and read from all the I/O's. These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL, to access the Semaphores. Refer to the Semaphore Read/Write Control Truth Table. 2740 tbl 18 Functional Description The IDT7024 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7024 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location FFE (HEX), where a write is defined as the CE = R/W = VIL per the Truth Table III. The left port clears the interrupt by access address location FFE access when CER = OER = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location FFF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location FFF. The message (16 bits) at FFE or FFF is userdefined, since it is an addressable SRAM location. If the interrupt function 6.42 17 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM is not used, address locations FFE and FFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7024 SRAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Width Expansion with BUSY Logic Master/Slave Arrays When expanding an IDT7024 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7024 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7024 is an extremely fast Dual-Port 4K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be BUSY (L) CE SLAVE Dual Port RAM BUSY (L) BUSY (R) MASTER CE Dual Port RAM BUSY (L) BUSY (R) SLAVE CE Dual Port RAM BUSY (L) BUSY (R) BUSY (R) 2740 drw 19 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7024 RAMs. used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM = VIH. Systems which can best use the IDT7024 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7024's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7024 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading 6.42 18 Feb.20.20 CE MASTER Dual Port RAM BUSY (L) BUSY (R) DECODER Military, Industrial and Commercial Temperature Ranges 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7024 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table III). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Truth Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7024’s Dual-Port RAM. Say the 4K x 16 RAM was to be divided into two 2K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 2K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 2K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then 6.42 19 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 2K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D SEMAPHORE REQUEST FLIP FLOP Q Q WRITE D D0 WRITE SEMAPHORE READ SEMAPHORE READ , 2740 drw 20 Figure 4. IDT7024 Semaphore Logic 6.42 20 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tube or Tray Tape & Reel Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML G(2) Green PF G J F 100-pin TQFP (PN100, PNG100) 84-pin PGA (GU84) 84-pin PLCC (PL84 / PLG84) 84-pin Flatpack (FP84) 15 17 20 25 35 55 70 Commercial Only Commercial Only Commercial, Industrial & Military Commercial & Military Commercial & Military Commercial & Military Military Only S L Standard Power Low Power 7024 64K (4K x 16) Dual-Port RAM Speed in nanoseconds 2740 drw 21 NOTE: 1. Industrial temperature range is available on selected PLCC packages in low power. For other speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are Obsolete excluding PGA & Flatpack. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 15 Pkg. Code Pkg. Type Temp. Grade 7024L15JG PLG84 PLCC C 17 7024L15JG8 PLG84 PLCC C 20 C 25 Orderable Part ID 7024L15PFG 7024L15PFG8 PNG100 TQFP Speed (ns) Pkg. Code Pkg. Type Temp. Grade 7024S17G GU84 PGA C 7024S20G GU84 PGA C 7024S25G GU84 PGA C 7024S25GB GU84 PGA M M Orderable Part ID PNG100 TQFP C 17 7024L17G GU84 PGA C 7024S35FB FP84 FPACK 20 7024L20FB FP84 FPACK M 7024S35G GU84 PGA C 7024L20G GU84 PGA C 7024S35GB GU84 PGA M 7024L20GB GU84 PGA M 7024S55FB FP84 FPACK M I 7024S55G GU84 PGA C 7024S55GB GU84 PGA M 7024S70FB FP84 FPACK M 7024S70GB GU84 PGA M 7024L20JGI PLG84 PLCC 7024L20JGI8 PLG84 PLCC I 7024L20PFGI PNG100 TQFP I 7024L20PFGI8 PNG100 TQFP I PGA C M 25 7024L25G GU84 7024L25GB GU84 PGA 35 7024L35FB FP84 FPACK M 7024L35G GU84 PGA C 55 70 7024L35GB GU84 PGA M 7024L55G GU84 PGA C 7024L55GB GU84 PGA M 7024L70GB GU84 PGA M 35 55 70 6.42 21 Feb.20.20 7024S/L High-Speed 4K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Datasheet Document History 01/13/99: 06/04/99: 04/04/00: 05/19/00: 09/12/01: 07/25/05: 10/29/08: 06/11/13: 05/23/18: 12/05/19: 02/20/20: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format Page 1 Corrected DSC number Replaced IDT logo Page 6 Corrected typo in Data Retention chart Changed ±500mV to 0mV in notes Page 3 Clarified TA parameter Page 4 Increased storage temperature parameter Pages 5 and 6 DC Electrical parameters–changed wording from "open" to "disabled" Page 2 & 3 Added date revision for pin configurations Page 5 Added Industrial temp to the column heading for 20ns to DC Electrical Characteristics Pages 8,10,13&15 Added Industrial temp to the column headings for 20ns to AC Electrical Characteristics Pages 3,5,6,8,10,13&15 Removed Industrial temp note from all tables footnotes Page 21 Added Industrial to 20ns ordering information Page 1 Added green availability to features Page 21 Added green indicator to ordering information Page 1 & 21 Replaced old IDT ® logo with the new IDTTM logo Page 21 Updated address and phone contact information Page 21 Removed "IDT" from orderable part number Page 21 Ordering Information. Added T&R Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Pages 1 & 21 Deleted obsolete Industrial 55ns speed grade and added Industrial 20ns speed grade Pages 2 & 3 Rotated PLG84 PLCC, FP84 Flatpack and PNG100 TQFP pin configurations to accurately reflect pin 1 orientation Page 21 Added Orderable Part Information tables Pages 1 - 23 Rebranded as Renesas datasheet 6.42 22 Feb.20.20 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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