7026L15J8

7026S/L HIGH-SPEED 16K X 16 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20/25/35ns (max.) – Industrial: 20ns (max.) – Military: 25/35ns (max.) Low-power operation – IDT7026S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7026L Active: 750mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slave On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in 84-pin PGA and 84-pin PLCC Industrial temperature range (-40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram R/WL UBL R/WR UBR LBL CEL OEL LBR CER OER I/O8L-I/O15L I/O Control I/O0L-I/O7L I/O8R-I/O15R I/O Control I/O0R-I/O7R (1,2) (1,2) BUSYR BUSYL A13L A0L Address Decoder MEMORY ARRAY 14 CEL Address Decoder A13R A0R 14 ARBITRATION SEMAPHORE LOGIC CER SEMR SEML M/S 2939 drw 01 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs are non-tri-stated push-pull. AUGUST 2019 1 DSC 2939/17 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7026 is a high-speed 16K x 16 Dual-Port Static RAM. The IDT7026 is designed to be used as a stand-alone Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7026 is packaged in a ceramic 84-pin PGA, and a 84-pin PLCC. Military grade product is manufactured in compliance with MILPRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R OER R/WR GND SEMR CER UBR LBR A13R A12R I/O8L I/O9L I/O10L I/O11L I/O12L GND I/O13L I/O14L VCC I/O15L GND I/O0R VCC I/O2R I/O1R I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R Pin Configurations(1,2,3) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 33 11 34 10 35 9 36 8 37 7 38 6 39 5 40 4 41 3 IDT7026 42 (4) 2 PLG84 43 1 84-Pin PLCC 44 84 Top View 45 83 46 82 47 81 48 80 I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL 6.42 2 A6L A7L A8L A5L A3L A4L A2L A7R NOTES: 1. All Vcc pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 1.15 in x 1.15 in x .17 in. 4. This package code is used to reference the package diagram. A1L A10L A9L A8R A0L 76 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 M/S A11L 52 GND BUSYL 77 A9R BUSYR A12L A0R 78 51 A1R 50 A2R A11R A10R A3R LBL A13L A4R 79 A6R A5R 49 2939 drw 02 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) 63 11 61 64 66 10 I/O10L I/O13L I/O15L I/O1L UBL CEL 53 GND 47 50 45 A10L 81 41 R/WL 33 IDT7026 GU84(4) GND 32 30 BUSYR A0R 5 I/O10R 4 I/O11R B 11 GND 2 I/O9R 27 A2R A3R I/O7R A A2L 29 A1R 7 3 I/O8R 36 M/S 28 VCC A0L 31 GND 84-Pin PGA Top View(5) 34 26 1 84 A3L A1L I/O4R I/O6R A5L 37 35 BUSYL 83 82 39 A7L VCC 78 I/O2R I/O5R A6L A4L 74 GND I/O3R 40 A9L 52 VCC A8L 43 44 A13L 42 A11L A12L 80 79 01 49 46 LBL 73 I/O14L I/O1R 02 I/O3L 48 SEML 38 77 76 03 56 51 OEL I/O12L I/O0R 04 I/O6L 54 I/O0L 57 70 75 05 59 I/O9L 71 72 06 55 I/O2L 68 69 07 62 I/O8L I/O11L 08 58 I/O4L 65 67 09 60 I/O5L I/O7L 8 I/O13R 6 I/O12R C D UBR OER E 16 CER F A4R A9R H 24 A7R 18 A13R G 22 20 A12R 13 LBR 25 A6R 17 14 R/WR 15 9 I/O14R SEMR GND 10 I/O15R 23 12 A5R 19 A11R 21 A10R J A8R K L 2939 drw 03 Index NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.12 in x 1.12 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Maximum Operating Temperature and Supply Voltage(1) Pin Names Grade Left Port CEL Right Port CER Military Names Chip Enable Commercial Industrial R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground Ambient Temperature GND Vcc -55 C to+125 C 0V 5.0V + 10% 0 C to +70 C 0V 5.0V + 10% -40 C to +85 C 0V 5.0V + 10% O O O O O O 2939 tbl 02a NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Capacitance(1) (TA = +25°C, f = 1.0mhz) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 2939 tbl 03 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 2939 tbl 01 6.42 3 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table I – Non-Contention Read/Write Control Inputs(1) Outputs CE R/W OE UB LB SEM I/O8-15 I/O0-7 H X X X X H High-Z High-Z Deselected: Power-Down X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H High-Z DATAOUT Read Lower Byte Only L H L L L H DATAOUT DATAOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled Mode 2939 tbl 04 NOTE: 1. A0L — A13L ≠ A0R — A13R. Truth Table II – Semaphore Read/Write Control(1) Inputs Outputs CE R/W OE UB LB SEM I/O8-15 I/O0-7 H H L X X L DATAOUT DATAOUT Read Data in Semaphore Flag X H L H H L DATAOUT DATAOUT Read Data in Semaphore Flag H ↑ X X X L DATAIN DATAIN Write I/O0 into Semaphore Flag X ↑ X H H L DATAIN DATAIN Write I/O0 into Semaphore Flag L X X L X L ______ ______ Not Allowed L X X X L L ______ ______ Not Allowed Mode NOTE: 1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2. 2939 tbl 05 Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Military Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 -65 to +135 o C TSTG Storage Temperature -55 to +125 -65 to +150 o C IOUT DC Output Current 50 50 mA 2939 tbl 06a NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. 6.42 4 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VCC Supply Voltage GND Ground VIH Input High Voltage 2.2 ____ 6.0(2) V VIL Input Low Voltage -0.5(1) ____ 0.8 V 2939 tbl 07 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7026S Symbol Parameter Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V |ILI| (1) Input Leakage Current |ILO| Test Conditions 7026L 2939 tbl 08 NOTE: 1. At Vcc = 2.0V, input leakages are undefined. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 2939 tbl 09 5V 5V 893Ω 893Ω DATAOUT BUSY DATAOUT 347Ω 30pF 347Ω 2939 drw 04 5pF* 2939 drw 05 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) * Including scope and jig. 6.42 5 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (con't.) (VCC = 5.0V ± 10%) 7026X15 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition Version 7026X20 Com'l, Ind & Military. 7026X25 Com'l, Ind & Military Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit mA COM'L S L 190 190 325 285 180 180 315 275 170 170 305 265 MIL & IND S L ___ ___ ___ ___ 180 180 355 315 170 170 345 305 COM'L S L 35 35 95 70 30 30 85 60 25 25 85 60 MIL & IND S L ___ ___ ___ ___ 30 30 100 80 25 25 100 80 CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH COM'L S L 125 125 220 190 115 115 210 180 105 105 200 170 MIL & IND S L ___ ___ ___ ___ 115 115 245 210 105 105 230 200 Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L ___ ___ ___ ___ 1.0 0.2 30 10 1.0 0.2 30 10 COM'L S L 120 120 195 170 110 110 185 160 100 100 170 145 MIL & IND S L ___ ___ ___ ___ 110 110 210 185 100 100 200 175 CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(3) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f=fMAX(3) mA mA mA mA 2939 tbl 10 7026X35 Com'l, Ind & Military Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Version 7026X55 Com'l, Ind & Military Typ.(2) Max. Typ. (2) Max. Unit mA Dynamic Operating Current (Both Ports Active) CE = VIL , Outputs Disabled SEM = VIH f = fMAX(3) COM'L S L 160 160 295 255 150 150 270 230 MIL & IND S L 160 160 335 295 150 150 310 270 Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(3) COM'L S L 20 20 85 60 13 13 85 60 MIL & IND S L 20 20 100 80 13 13 100 80 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH COM'L S L 95 95 185 155 85 85 165 135 MIL & IND S L 95 95 215 185 85 85 195 165 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L 1.0 0.2 30 10 1.0 0.2 30 10 Full Standby Current (One Port - All CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f=fMAX(3) COM'L S L 90 90 160 135 80 80 135 110 MIL & IND S L 90 90 190 165 80 80 175 150 NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 6.42 6 mA mA mA mA 2939 tbl 11 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 7026X15 Com'l Only Symbol Parameter 7026X20 Com'l, Ind & Military 7026X25 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 15 ____ 20 ____ 25 ns tACE Chip Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tABE Byte Enable Access Time (3) ____ 15 ____ 20 ____ 25 ns tAOE Output Enable Access Time ____ 10 ____ 12 ____ 13 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ ns ____ 10 ____ 12 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 15 ____ 20 ____ 25 ns 10 ____ 12 ____ ns ____ 20 ____ 25 ns (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) tPU Chip Enable to Power Up Time (2) (2) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ tSAA Semaphore Address Access Time ____ 15 2939 tbl 12a 7026X35 Com'l, Ind & Military Symbol Parameter 7026X55 Com'l, Ind & Military Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 35 ____ 55 ____ ns tAA Address Access Time ____ 35 ____ 55 ns Chip Enable Access Time (3) ____ 35 ____ 55 ns tABE Byte Enable Access Time (3) ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 20 ____ 30 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns 3 ____ 3 ____ ns ____ 15 ____ 25 ns 0 ____ 0 ____ ns tACE tLZ Output Low-Z Time (1,2) (1,2) tHZ Output High-Z Time tPU Chip Enable to Power Up Time (2) tPD Chip Disable to Power Down Time(2) ____ 35 ____ 50 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 15 ____ 15 ____ ns tSAA Semaphore Address Access Time ____ 35 ____ 55 ns NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). 6.42 7 2939 tbl 12b 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges WAVEFORM OF READ CYCLES(5) tRC ADDR (4) tAA (4) tACE CE tAOE (4) OE tABE (4) UB, LB R/W tLZ tOH (1) DATAOUT VALID DATA (4) tHZ (2) BUSYOUT tBDD (3, 4) 2939 drw 06 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. Timing of Power-Up Power-Down CE ICC tPU tPD 50% 50% ISB 2939 drw 07 6.42 8 , 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5,6) 7026X15 Com'l Only Symbol Parameter 7026X20 Com'l, Ind & Military 7026X25 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Unit 15 ____ 20 ____ 25 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ 20 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 12 ____ 15 ____ 20 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 15 ____ 15 ____ ns ____ 10 ____ 12 ____ 15 ns WRITE CYCLE tWC tHZ Write Cycle Time Output High-Z Time tDH Data Hold Time tWZ (1,2) (4) 0 ____ 0 ____ 0 ____ ns (1,2) ____ 10 ____ 12 ____ 15 ns (1,2,4) 0 ____ 0 ____ 0 ____ ns SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns SEM Flag Contention Window 5 ____ 5 ____ 5 ____ ns Write Enable to Output in High-Z tOW tSWRD tSPS Output Active from End-of-Write 3199 tbl 13a Symbol 7026X35 Com'l, Ind & Military Parameter 7026X55 Com'l, Ind & Military Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 35 ____ 55 ____ ns tEW Chip Enable to End-of-Write (3) 30 ____ 45 ____ ns tAW Address Valid to End-of-Write 30 ____ 45 ____ ns 0 ____ 0 ____ ns (3) tAS Address Set-up Time tWP Write Pulse Width 25 ____ 40 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 15 ____ 30 ____ ns ____ 15 ____ 25 ns 0 ____ ns 25 ns ns ns tHZ tDH tWZ tOW tSWRD tSPS Output High-Z Time Data Hold Time (1,2) (4) 0 ____ (1,2) ____ 15 ____ (1,2,4) 0 ____ 0 ____ SEM Flag Write to Read Time 5 ____ 5 ____ SEM Flag Contention Window 5 ____ 5 ____ Write Enable to Output in High-Z Output Active from End-of-Write ns 2939 tbl 13b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). 6.42 9 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM (9) UB or LB (9) tWP (2) tAS (6) tWR (3) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 2939 drw 08 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS tAW (9) CE or SEM tAS (6) tWR (3) tEW (2) (9) UB or LB R/W tDW tDH DATAIN 2939 drw 09 NOTES: 1. R/W or CE or UB and LB = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a VIL CE = VIL and R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 6.42 10 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tOH tSAA A0-A2 VALID ADDRESS tAW VALID ADDRESS tWR tACE tEW SEM tSOP tDW DATAIN VALID I/O0 tAS tWP DATAOUT VALID(2) tDH R/W tSWRD tAOE OE Read Cycle Write Cycle 2939 drw 10 NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 2939 drw 11 NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH. 2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag. 6.42 11 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7) 7026X15 Com'l Only Symbol Parameter 7026X20 Com'l, Ind & Military 7026X25 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 15 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ____ 20 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 15 ____ 20 ____ 20 ns tBDC BUSY Acce ss Time from Chip Enable High ____ 15 ____ 17 ____ 17 ns 5 ____ 5 ____ 5 ____ ns ____ 18 ____ 30 ____ 30 ns 12 ____ 15 ____ 17 ____ ns tAPS tBDD Arbitration Priority Set-up Time (2) BUSY Disable to Valid Data (5) Write Hold After BUSY tWH BUSY TIMING (M/S=VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ 17 ____ ns ____ 30 ____ 45 ____ 50 ns ____ 25 ____ 30 ____ 35 ns PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) 2939 tbl 14a 7026X35 Com'l, Ind & Military Symbol Parameter 7026X55 Com'l, Ind & Military Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 20 ____ 45 ns BUSY Disable Time from Address Not Matched ____ 20 ____ 40 ns BUSY Acce ss Time from Chip Enable Low ____ 20 ____ 40 ns BUSY Acce ss Time from Chip Enable High ____ 20 ____ 35 ns 5 ____ 5 ____ ns ____ 35 ____ 40 ns 25 ____ 25 ____ ns 0 ____ 0 ____ ns 25 ____ 25 ____ ns ____ 60 ____ 80 ns ____ 45 ____ 65 BUSY TIMING (M/S=VIH) tBAA tBDA tBAC tBDC tAPS tBDD tWH Arbitration Priority Set-up Time (2) (3) BUSY Disable to Valid Data (5) Write Hold After BUSY BUSY TIMING (M/S=VIL) tWB tWH BUSY Input to Write (4) (5) Write Hold After BUSY PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ns 2939 tbl 14b NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). 7. Industrial temperature: for other speeds, packages and powers contact your sales office. 6.42 12 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5) tWC MATCH ADDR"A" tWP R/W"A" tDW tDH VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2939 drw 12 Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH R/W"B" (1) (2) , 2939 drw 13 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the “SLAVE” version. 6.42 13 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 2939 drw 14 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1) ADDR"A" ADDRESS "N" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 2939 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. Truth Table III — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D15 Left D0 - D15 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7026. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table. 6.42 14 2939 tbl 15 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Width Expansion with BUSY Logic Master/Slave Arrays Inputs Outputs CEL CER AOL-A13L AOR-A13R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 2939 tbl 16 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7026 are push pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes. 2. LOW if the inputs to the opposite port were stable prior to the address and enable inputs of this port. HIGH if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. When expanding an IDT7026 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT7026 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the MASTER Dual Port RAM BUSYL BUSYL MASTER Dual Port RAM BUSYL CE BUSYR CE BUSYR SLAVE Dual Port RAM BUSYL SLAVE Dual Port RAM BUSYL CE BUSYR DECODER Truth Table IV — Address BUSY Arbitration CE BUSYR BUSYR 2939 drw 16 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7026 RAMs. Functional Description The IDT7026 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7026 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7026 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7026 is an extremely fast Dual-Port 16K x 16 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the DualPort RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts 6.42 15 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM = VIH. Systems which can best use the IDT7026 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7026's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7026 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7026 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table III). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table III). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that 6.42 16 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D Q SEMAPHORE REQUEST FLIP FLOP Q D WRITE SEMAPHORE READ D0 WRITE SEMAPHORE READ , 2939 drw 17 Figure 4. IDT7026 Semaphore Logic semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7026’s Dual-Port RAM. Say the 16K x 16 RAM was to be divided into two 8K x 16 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 8K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 8K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 8K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 8K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the DualPort RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. 6.42 17 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tray Tape and Reel Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to + 85°C) Military (-55°C to + 125°C) Compliant to MIL-PRF-38535 QML G(2) Green G J 84-pin PGA (G84) 84-pin PLCC (J84) 15 20 25 35 Commercial Only Commercial & Industrial Commercial & Military Commercial & Military S L Standard Power Low Power 7026 256K (16K x 16) Dual-Port RAM Speed in nanoseconds 2939 drw 18 NOTES: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 2. Green parts available. For specific speeds, packages and powers contact your local sales office LEAD FINISH (SnPb) parts are Obsolete excluding PGA. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Pkg. Code Pkg. Type Temp. Grade Speed (ns) 7026L15JG PLG84 PLCC C 20 7026L15JG8 PLG84 PLCC C 7026L20G GU84 PGA C 7026L20JGI PLG84 PLCC I 7026L20JGI8 PLG84 PLCC I 25 7026L25G GU84 PGA C 7026L25GB GU84 PGA M 35 7026L35G GU84 PGA C 7026L35GB GU84 PGA M Speed (ns) 15 20 Orderable Part ID 6.42 18 Pkg. Code Pkg. Type Temp. Grade 7026S20G GU84 PGA C 25 7026S25G GU84 PGA C 35 7026S35G GU84 PGA C Orderable Part ID 7026S/L High-Speed 16K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Datasheet Document History 01/14/99: 060/3/99: 03/10/00: 05/22/00: 11/20/01: 01/29/09: 08/05/15: 03/07/18: 08/29/19: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format Page 1 Corrected DSC number Added Industrial Temperature Ranges and removed related notes Replaced IDT logo Page 1 Fixed format in Features Changed ±200mV to 0mV in notes Page 3 Clarified TA parameter Page 6 DC Electrical parameters–changed wording from "open" to "disabled" Page 1 & 18 Verified accuracy of Industrial temp information throughout datasheet and updated with registered logo Page 2 & 3 Added date revision for pin configurations Page 18 Removed "IDT" from orderable part number Page 1In Features: Added text: "Green parts available, see ordering information". Page 2 In Descriptions: Removed IDT in reference to fabrication Page 2 &18 The package code J84-1 changed to J84 to match standard package codes Page 3 &18 The package code G84-1 changed to G84 to match standard package codes Page 18 Added Green and Tape & Reel indicators to the Ordering Information and updated footnotes Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 1 & 18 Deleted obsolete speed grades Page 2 Rotated PLG84 PLCC pin configuration to accurately reflect pin 1 orientation Page 18 Added Orderable Part Information tables CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 19 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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