7034S20PF

HIGH-SPEED 4K x 18 DUAL-PORT STATIC RAM IDT7034S/L LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 Features: ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT7034S Active: 850mW (typ.) Standby: 5mW (typ.) – IDT7034L Active: 850mW (typ.) Standby: 1mW (typ.) Separate upper-byte and lower-byte control for multiplexed bus compatibility IDT7034 easily expands data bus width to 36 bits or more ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ using the Master/Slave select when cascading more than one device M/S = H for BUSY output flag on Master M/S = L for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Battery backup operation—2V data retention TTL-compatible, single 5V (±10%) power supply Available in 100-pin Thin Quad Flatpack Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available. See ordering information Functional Block Diagram R/WL R/WR LBL CEL OEL LBR CER OER UBL UBR I/O9L-I/O17L I/O0L-I/O8L I/O9R-I/O17R I/O Control I/O Control I/O0R-I/O8R (1,2) (1,2) BUSYR BUSYL A11L A0L . Address Decoder MEMORY ARRAY 13 CEL OEL R/WL SEML (2) INTL Address Decoder A11R A0R 13 ARBITRATION INTERRUPT SEMAPHORE LOGIC M/S CER OER R/WR SEMR (2) INTR 4089 drw 01 NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. MAY 2018 1 ©2018 Integrated Device Technology, Inc. DSC 4089/11 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: for reads or writes to any location in memory. An automatic power down feature controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT7034 utilizes a 18-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applications. Fabricated using CMOS high-performance technology, these devices typically operate on only 850mW of power. Low-power (L) versions offer battery backup data retention capability with typical power consumption of 500µW from a 2V battery. The IDT7034 is a high-speed 4K x 18 Dual-Port Static RAM. The IDT7034 is designed to be used as a stand-alone 72K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access I/O10L I/O9L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/W L SEML CE L UB L LBL N/C A11L A10L A9L A8L A7L A6L Pin Configurations(1,2,3) Index 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 67 9 10 11 IDT7034PF PN100(4) 12 13 14 100-PIN TQFP TOP VIEW(5) 66 65 64 63 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O7R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND I/O16R OER R/WR GND SEMR CER UBR LBR N/C A11R A10R A9R A8R A7R A6R A5R N/C N/C I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R N/C N/C NOTES: 1. All VCC pins must be connected to power supply 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 2 N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R N/C N/C N/C N/C 4089drw 02 . IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A11L A0R - A11R Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select LBL LBR Lower Byte Select INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 4089 tbl 01 Truth Table I: Non-Contention Read/Write Control Inputs(1) Outputs CE R/W OE UB LB SEM I/O9-17 I/O0-8 H X X X X H High-Z High-Z Deselected: Power-Down X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H DATAIN High-Z Write to Upper Byte Only L L X H L H High-Z DATAIN Write to Lower Byte Only L L X L L H DATAIN DATAIN Write to Both Bytes L H L L H H DATAOUT High-Z Read Upper Byte Only L H L H L H High-Z DATAOUT Read Lower Byte Only L H L L L H DATAOUT DATAOUT Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled Mode 4089 tbl 02 NOTE: 1. A0L — A11L ≠ A0R — A11R 3 6.42 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table II: Semaphore Read/Write Control(1) Inputs Outputs CE R/W OE UB LB SEM I/O9-17 I/O0-8 Mode H H L X X L DATAOUT DATAOUT Read Data in Semaphore Flag X H L H H L DATAOUT DATAOUT Read Data in Semaphore Flag H ↑ X X X L DATAIN DATAIN Write I/O0 into Semaphore Flag X ↑ X H H L DATAIN DATAIN Write I/O0 into Semaphore Flag L X X L X L ____ ____ Not Allowed L X X X L L ____ ____ Not Allowed 4089 tbl 03 NOTE: 1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O17. These eight semaphores are addressed by A0 - A2. Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Commercial & Industrial Maximum Operating Temperature and Supply Voltage(1) Unit -0.5 to +7.0 Grade V Commercial TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -65 to +150 o IOUT DC Output Current 50 Industrial C C COUT Input Capacitance Output Capacitance 0 C to +70 C 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% 4089 tbl 05 Recommended DC Operating Conditions Symbol Capacitance (TA = +25°C, f = 1.0MHz)(1) CIN Vcc O mA 4089 tbl 04 Parameter GND O NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%. Symbol Ambient Temperature Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF Parameter VCC Supply Voltage GND Ground 4089 tbl 07 4 Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VIH Input High Voltage 2.2 ____ VIL Input Low Voltage -0.5(1) ____ NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. Min. (2) 6.0 0.8 V V 4089 tbl 06 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7034S Symbol Parameter Test Conditions 7034L Min. Max. Min. Max. Unit |ILI| Input Leakage Current(1) VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA |ILO| Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ NOTE: 1. At VCC < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%) 7034X15 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Test Condition Version CE = VIL, Outputs Disabled SEM = VIH f = fMAX(3) CEL = CER = VIH SEMR = SEML = VIH f = fMAX(3) 7034X20 Com'l & Ind Typ.(2) Max. Typ.(2) Max. Unit mA COM'L S L 170 170 310 260 160 160 290 240 IND S L ____ ____ ____ ____ 160 160 370 320 COM'L S L 20 20 60 50 20 20 60 50 IND S L ____ ____ ____ ____ 20 20 90 70 Standby Current CE"A" = VIL and CE"B" = VIH(5) (One Port - TTL Level Inputs) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = VIH COM'L S L 105 105 190 160 95 95 180 150 IND S L ____ ____ ____ ____ 95 95 240 210 Full Standby Current (Both Ports - All CMOS Level Inputs) COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 IND S L ____ ____ ____ ____ 1.0 0.2 30 10 COM'L S L 100 100 170 140 90 90 155 130 IND S L ____ ____ ____ ____ 90 90 225 200 Full Standby Current (One Port - All CMOS Level Inputs) V 4089 tbl 08 Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) SEMR = SEML > VCC - 0.2V VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (TYP) 3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 5 6.42 mA mA mA mA 4089 tbl 09 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VCC = 0.2V, VHC = VCC - 0.2V)(4) Symbol Parameter Test Condition Min. Typ.(1) Max. Unit 2.0 ___ ___ V µA VDR VCC for Data Retention VCC = 2V ICCDR Data Retention Current CE > VHC IND. ___ 100 4000 VIN > VHC or < VLC COM'L. ___ 100 1500 0 ___ ___ ns tRC(2) ___ ___ ns tCDR (3) tR(3) SEM > VHC Chip Deselect to Data Retention Time Operation Recovery Time 4089 tbl 10 NOTES: 1. TA = +25°C, VCC = 2V, not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by characterization, but is not production tested. 4. At Vcc < 2.0V input leakages are undefined. Data Retention Waveform DATA RETENTION MODE VDR > 2V 4.5V VCC 4.5V tCDR CE tR VDR VIH VIH 4089 drw 03 AC Test Conditions Input Pulse Levels Input Rise/Fall Times 5V GND to 3.0V 5ns Max. 893Ω Input Timing Reference Levels 1.5V DATAOUT Output Reference Levels 1.5V BUSY INT Output Load 5V Figures 1 and 2 893Ω DATAOUT 347Ω 30pF 347Ω 5pF* 4089 tbl 11 4089 drw 04 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *including scope and jig. 6 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 7034X15 Com'l Only Symbol Parameter 7034X20 Com'l & Ind Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 ____ 20 ____ ns tAA Address Access Time ____ 15 ____ 20 ns tACE Chip Enable Access Time (3) ____ 15 ____ 20 ns tABE Byte Enable Access Time (3) ____ 15 ____ 20 ns tAOE Output Enable Access Time ____ 10 ____ 12 ns tOH Output Hold from Address Change 3 ____ 3 ____ ns tLZ Output Low-Z Time (1,2) 3 ____ 3 ____ ns tHZ Output High-Z Time (1,2) ____ 10 ____ 12 ns tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time (2) ____ 15 ____ 20 ns tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ 10 ____ ns tSAA Semaphore Address Access Time ____ 15 ____ 20 ns 4089 tbl 12 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. 4. 'X' in part numbers indicates power rating (S or L). Waveform of Read Cycles(5) tRC ADDR (4) CE tAA (4) tACE tAOE (4) OE tABE (4) UB, LB R/W tLZ tOH (1) DATAOUT VALID DATA (4) tHZ (2) BUSYOUT tBDD (3,4) 4089 drw 05 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. 3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD. 5. SEM = VIH. 7 6.42 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing of Power-up Power-down CE tPU tPD ICC 50% 50% ISB 4089 drw 06 , AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7034X15 Com'l Only Symbol Parameter 7034X20 Com'l & Ind Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 15 ____ 20 ____ ns tEW Chip Enable to End-of-Write (3) 12 ____ 15 ____ ns tAW Address Valid to End-of-Write 12 ____ 15 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ ns tWP Write Pulse Width 12 ____ 15 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 15 ____ ns tHZ Output High-Z Time (1,2) ____ 10 ____ 12 ns tDH Data Hold Time (4) 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1,2) ____ 10 ____ 12 ns tOW Output Active from End-of-Write (1,2,4) 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ ns 4089 tbl 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L). 8 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM UB or LB (9) (9) tAS (6) tWP (2) tWR (3) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 4089 drw 07 Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9) tAS(6) UB or LB tWR (3) tEW (2) (9) R/W tDW tDH DATAIN 4089 drw 08 NOTES: 1. R/W or CE or UB & LB must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW UB or LB and a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end-of-write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met for either condition. 9 6.42 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveforme of Semaphore Read After Write Timing, Either Side(1) tOH tSAA A0 - A2 VALID ADDRESS tAW VALID ADDRESS tWR tACE tEW SEM tSOP tDW DATA OUT VALID(2) DATAIN VALID DATA0 tAS tWP tDH R/W tAOE tSWRD OE tSOP Write Cycle Read Cycle 4089 drw 09 NOTE: 1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle). 2. "DATAOUT VALID' represents all I/Os (I/O0-I/O17) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 4089 drw 10 NOTES: 1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH. 2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag. 10 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 7034X15 Com'l Only Symbol Parameter 7034X20 Com'l & Ind Min. Max. Min. Max. Unit BUSY Access Time from Address Match ____ 15 ____ 20 ns tBDA BUSY Disable Time from Address Not Matched ____ 15 ____ 20 ns tBAC BUSY Acce ss Time from Chip Enable Low ____ 15 ____ 20 ns tBDC BUSY Acce ss Time from Chip Enable High ____ 15 ____ 17 ns 5 ____ 5 ____ ns BUSY TIMING (M/S=VIH) tBAA (2) tAPS Arbitration Priority Set-up Time tBDD BUSY Disable to Valid Data(3) ____ 18 ____ 30 ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns BUSY TIMING (M/S=VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 30 ____ 45 ns tDDD Write Data Valid to Read Data Delay (1) ____ 25 ____ 30 ns 4089 tbl 14 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform of Write With Port-To-Port Delay (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A". 5. To ensure that a write cycle is completed on Port "B" after contention with Port "A". 6. 'X' in part numbers indicates power rating (S or L). 11 6.42 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN "A" tDH VALID tAPS (1) ADDR"B" MATCH tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) 4089 drw 11 NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (SLAVE) then BUSY is an input. BUSY"A" = VIL and BUSY"B" = 'don't care' 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the opposite Port from Port "A". Timing Waveform of Write with BUSY tWP R/W"A" BUSY"B" tWB(3) tWH (1) R/W"B" . (2) 4089 drw 12 NOTES: 1. tWH must be met for both BUSY input (slave) output master. 2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the 'Slave' Version. 12 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 4089 drw 13 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1)(M/S = VIH) ADDR"A" ADDRESS "N" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 4089 drw 14 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 7034X15 Com'l Only Symbol Parameter 7034X20 Com'l & Ind Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 15 ____ 20 ns tINR Interrupt Reset Time ____ 15 ____ 20 ns 4089 tbl 15 NOTES: 1. 'X' in part numbers indicates power rating (S or L). 13 6.42 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing (1) tWC ADDR"A" INTERRUPT SET ADDRESS (2) tAS (3) tWR (4) CE"A" R/W"A" tINS (3) INT"B" 4089 drw 15 tRC INTERRUPT CLEAR ADDRESS ADDR"B" (2) tAS (3) CE"B" OE"B" tINR (3) INT"B" 4089 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Flag Truth Table III. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. Truth Table III — Interrupt Flag(1) Left Port Right Port R/WL CEL OEL A0L-A11L INTL R/WR CER OER A0R-A11R INTR L L X FFF X X X X X L(2) X X X X X L X X L X X FFE X (3) Function Set Right INTR Flag Reset Right INTR Flag X L L FFF H (3) L L X FFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag L H 4089 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTR and INTL must be initialized at power-up. 14 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration Inputs Outputs CEL CER AOL-A11L AOR-A11R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 4089 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7034 are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D17 Left D0 - D17 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7034. 2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Control Truth Table. 4089 tbl 18 FUNCTIONAL DESCRIPTION The IDT7034 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7034 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. INTERRUPTS If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location FFE (HEX), where a write is defined as the CER = R/WR = VIL per Truth Table III. The left port clears the interrupt by an address location FFE access when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location FFF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location FFF. The message (18 bits) at FFE or FFF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations FFE and FFF are not used as mail boxes, but as part of the random access memory. Refer to Table III for the interrupt operation. 15 6.42 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7034 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. WIDTH EXPANSION WITH BUSY LOGIC MASTER/SLAVE ARRAYS When expanding an IDT7034 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7034 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. SEMAPHORES The IDT7034 is an extremely fast Dual-Port 4K x 18 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the BUSY (L) CE MASTER Dual Port RAM BUSY (L) BUSY (R) CE SLAVE Dual Port RAM BUSY (L) BUSY (R) MASTER CE Dual Port RAM BUSY (L) BUSY (R) SLAVE CE Dual Port RAM BUSY (L) BUSY (R) DECODER BUSY LOGIC BUSY (R) 4089 drw 17 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7034 RAMs. other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/ WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table I where CE and SEM are both HIGH. Systems which can best use the IDT7034 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT7034's hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7034 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. HOW THE SEMAPHORE FLAGS WORK The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, 16 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7034 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. USING SEMAPHORES—SOME EXAMPLES Perhaps the simplest application of semaphores is their application as resource markers for the IDT7034’s Dual-Port RAM. Say the 4K x 18 RAM was to be divided into two 2K x 18 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 2K of Dual-Port RAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task was successfully completed (a zero was read back rather than a one), the left processor would assume control of the 17 6.42 IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges lower 2K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 2K section by writing, then reading a zero into Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 2K blocks of Dual-Port RAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port RAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I/O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was “off-limits” to the CPU, both the CPU and the I/O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory “WAIT” state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned RAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D SEMAPHORE REQUEST FLIP FLOP Q Q D WRITE D0 WRITE SEMAPHORE READ SEMAPHORE READ Figure 4. IDT7034 Semaphore Logic 18 4089 drw 18 . IDT7034S/L High-Speed 4K x 18 Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Type Power Speed Package Industrial and Commercial Temperature Ranges A A A Process/ Temperature Range NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available . For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 Blank 8 Tube or Tray Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to + 85°C) G(2) Green PF 100-pin TQFP (PN100) 15 20 Commercial Only Commercial & Industrial S L Standard Power Low Power 7034 72K (4K x 18) Dual-Port RAM Speed in nanoseconds 4089 drw 19 Datasheet Document History 12/03/98: 05/19/99: 06/03/99: 09/01/99: 10/04/99: 11/10/99: 05/22/00: 01/29/09: 06/05/15: 05/29/18: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations Page 9 Fixed typographical error Changed drawing format Page 1 Corrected DSC number Removed Preliminary Removed Industrial Temperature Ranges and removed corresponding notes Replaced IDT logo Page 4 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±500mV to 0mV in notes Page 19 Removed "IDT" from orderable part number Page 1 Added Green availability to Features Page 2 Removed IDT in reference to fabrication Page 2 & 19 The package code for PN100-1 changed to PN100 to match the standard package codes Page 19 Added Green and T&R indicators and the correlating footnotes to Ordering Information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 19 6.42 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.