7054L35PRF

7054L HIGH-SPEED 4K x 8 FourPortTM STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description High-speed access – Commercial: 20ns (max.) Low-power operation – IDT7054L Active: 750mW (typ.) Standby: 1.5mW (typ.) True FourPort memory cells which allow simultaneous access of the same memory locations Fully asynchronous operation from each of the four ports: P1, P2, P3, and P4 TTL-compatible; single 5V (±10%) power supply Available in 128 pin Thin Quad Flatpack package Green parts available, see ordering information The IDT7054 is a high-speed 4K x 8 FourPort™ Static RAM designed to be used in systems where multiple access into a common RAM is required. This FourPort Static RAM offers increased system performance in multiprocessor systems that have a need to communicate in real time and also offers added benefit for high-speed systems in which multiple access is required in the same cycle. The IDT7054 is also designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrated or withstand contention when all ports simultaneously access the same FourPort RAM location. The IDT7054 provides four independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for Functional Block Diagram R/WP1 CEP1 R/WP4 CEP4 OEP1 OEP4 I/O0P1-I/O7P1 A0P1 - A11P1 A0P2 - A11P2 I/O0P2-I/O7P2 COLUMN I/O COLUMN I/O PORT 1 ADDRESS DECODE LOGIC MEMORY ARRAY PORT 2 ADDRESS DECODE LOGIC COLUMN I/O PORT 4 ADDRESS DECODE LOGIC A0P4 - A11P4 PORT 3 ADDRESS DECODE LOGIC A0P3 - A11P3 COLUMN I/O OEP2 I/O0P4-I/O7P4 I/O0P3-I/O7P3 OEP3 CEP2 CEP3 R/WP2 R/WP3 3241 drw 01 JULY 2019 1 DSC 3241/15 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range reads or writes to any location in memory. It is the user’s responsibility to ensure data integrity when simultaneously accessing the same memory location from all ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low power standby power mode. Fabricated using CMOS high-performance technology, this FourPort SRAM typically operates on only 750mW of power. The IDT7054 is packaged in a 128-pin Thin Quad Flatpack (TQFP). CEP2 OEP2 N/C N/C N/C N/C N/C A0P1 A1P1 A2P1 A3P1 A4P1 A5P1 A6P1 A10P1 VCC A7P1 A8P1 A9P1 A11P1 CEP1 R/WP1 OEP1 N/C N/C N/C N/C N/C N/C I/O0P1 I/O1P1 I/O2P1 I/O3P1 GND I/O4P1 I/O5P1 I/O6P1 I/O7P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 IDT7054PRF PKG128(4) 128-Pin TQFP Top View(5) 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 INDEX 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 R/WP2 A11P2 A9P2 A8P2 A7P2 A10P2 A6P2 A5P2 A4P2 A3P2 A2P2 A1P2 A0P2 A0P3 A1P3 A2P3 A3P3 A4P3 A5P3 A6P3 A10P3 A7P3 A8P3 A9P3 A11P3 OEP3 (1,2,3) Pin Configuration 07/09/19 CEP3 R/WP3 N/C N/C N/C N/C N/C A0P4 A1P4 A2P4 A3P4 A4P4 A5P4 A6P4 A10P4 GND A7P4 A8P4 A9P4 A11P4 CEP4 R/WP4 OEP4 N/C N/C N/C N/C N/C GND N/C I/O7P4 I/O6P4 I/O5P4 GND I/O4P4 I/O3P4 I/O2P4 I/O1P4 N/C VCC I/O0P2 I/O1P2 I/O2P2 GND I/O3P2 I/O4P2 I/O5P2 VCC I/O6P2 I/O7P2 N/C I/00P3 I/O1P3 VCC I/O2P3 I/O3P3 I/O4P3 GND I/O5P3 I/O6P3 I/O7P3 N/C VCC I/O0P4 . NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 2 3241 drw 03 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range Capacitance(1) Pin Configurations(1,2) Symbol (TA = +25°C, f = 1.0MHz) TQFP ONLY Pin Name Symbol Parameter A0 P1 - A11 P1 Address Line s - Port 1 A0 P2 - A11 P2 Address Line s - Port 2 A0 P3 - A11 P3 Address Line s - Port 3 A0 P4 - A11 P4 Address Line s - Port 4 I/O0 P1 - I/O7 P1 Data I/O - Port 1 I/O0 P2 - I/O7 P2 Data I/O - Port 2 I/O0 P3 - I/O7 P3 Data I/O - Port 3 I/O0 P4 - I/O7 P4 Data I/O - Port 4 R/W P1 Read/Write - Port 1 R/W P2 Read/Write - Port 2 R/W P3 Read/Write - Port 3 R/W P4 Read/Write - Port 4 GND Ground Commercial CE P1 Chip Enab le - Port 1 Industrial CE P2 Chip Enab le - Port 2 CE P3 Chip Enab le - Port 3 CE P4 Chip Enab le - Port 4 OE P1 Output Enable - Port 1 OE P2 Output Enable - Port 2 OE P3 Output Enable - Port 3 OE P4 Output Enable - Port 4 VCC Power VCC Supply Voltage GND Ground VIH Input High Voltage VIL Input Low Voltage Grade Symbol 3241 tbl 01 VOUT = 0V 10 pF Ambient Temperature GND Vcc 0°C to +70°C 0V 5.0V + 10% -40°C to +85°C 0V 5.0V + 10% 3241 tbl 04 Rating Commercial & Industrial Unit V TERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -65 to +150 o IOUT DC Output Current 50 C C mA 3241 tbl 05 Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. pF Absolute Maximum Ratings(1) Max. ____ 9 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Typ. -0.5 Output Capacitance VIN = 0V Maximum Operating Temperature and Supply Voltage(1) Min. (1) COUT Unit 3241 tbl 03 Recommended DC Operating Conditions Parameter Input Capacitance Max. NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and the output signals switch from 0V to 3V or from 3V to 0V. NOTES: 1. All VCC pins must be connected to the power supply. 2. All GND pins must be connected to the ground supply. Symbol CIN Conditions(2) (2) 6.0 0.8 V NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%. V 3241 tbl 02 6.42 3 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%) 7054X20 Com'l Only Symbol ICC1 ICC2 ISB ISB1 Parameter Condition Operating Power Supply Current (All Ports Active) Version CE = V IL Outputs Disabled f = 0(3) Dynamic Operating Current (All Ports Active) CE = V IL Outputs Disabled f = fMAX(4) Standby Current (All Ports - TTL Level Inputs) CE = V IH f = fMAX(4) All Ports CE > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(3) Full Standby Current (All Ports - All CMOS Level Inputs) 7054X25 Com'l & Ind 7054X35 Com'l Only TYP.(2) Max. TYP.(2) Max. TYP.(2) Max. Unit COM'L. S L 150 150 300 250 150 150 300 250 150 150 300 250 mA IND. S L ____ ____ ____ ____ 150 150 360 300 150 150 360 300 mA COM'L. S L 240 210 370 325 225 195 350 305 210 180 335 290 mA IND. S L ____ ____ ____ ____ 225 195 400 340 210 180 395 330 mA COM'L. S L 70 60 95 80 60 50 85 70 40 35 75 60 mA IND. S L ____ ____ ____ ____ 60 50 115 85 40 35 110 80 mA COM'L. S L 1.5 0.3 15 1.5 1.5 0.3 15 1.5 1.5 0.3 15 1.5 mA IND. S L ____ ____ ____ ____ 1.5 0.3 30 4.5 1.5 0.3 30 4.5 mA 3241 tbl 06 NOTES: 1. 'X' in part number indicates power rating (S or L). 2. VCC = 5V, TA = +25°C and are not production tested. 3. f = 0 means no address or control lines change. 4. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V. 5. For the case of one port, divide the appropriate current above by four. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7054S Symbol Parameter Test Conditions 7054L Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V |ILI| (1) Input Leakage Current |ILO| 2674 tbl 07 NOTE: 1. At Vcc < 2.0V input leakages are undefined. 6.42 4 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1 and 2 3241 tbl 08 5V 5V 893Ω 893Ω DATAOUT DATAOUT 347Ω 347Ω 30pF 5pF* , 3241 drw 04 Figure 2. Output Test Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig Figure 1. AC Output Test Load Timing Waveform of Read Cycle No. 1, Any Port(1) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATA VALID DATA VALID 3241 drw 05 NOTE: 1. R/W = VIH, OE = VIL, and CE = VIL. 6.42 5 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3) 7054X20 Com'l Only Symbol Parameter 7054X25 Com'l & Ind 7054X35 Com'l Only Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 10 ____ 15 ____ 25 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ 5 ____ ns ____ 12 ____ 15 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 25 ____ 35 ns (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time(1,2) Chip Enable to Power Up Time tPU (2) Chip Disable to Power Down Time tPD (2) 3241 tbl 09 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. 'X' in part number indicates power rating (S or L). Timing Waveform of Read Cycle No. 2, Any Port(1, 2) tACE CE tAOE tHZ OE tLZ tHZ DATAOUT VALID DATA tLZ tPU tPD ICC 50% CURRENT 50% ISB 3241 drw 06 NOTES: 1. R/W = VIH for Read Cycles. 2. Addresses valid prior to or coincident with CE transition LOW. 6.42 6 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7054X20 Com'l Only Symbol Parameter 7054X25 Com'l & Ind 7054X35 Com'l Only Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 20 ____ 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns 15 ____ 20 ____ 30 ____ ns ____ 0 ____ ns 20 ____ ns 15 ns ____ ns (3) tWP Write Pulse Width tWR Write Recovery Time 0 ____ 0 tDW Data Valid to End-of-Write 15 ____ 15 ____ 15 ____ 15 ____ 0 ____ 0 ____ 0 ____ 12 ____ 15 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 35 ____ 45 ____ 55 ns ____ 30 ____ 35 ____ 45 ns (1,2) tHZ Output High-Z Time tDH Data Hold Time tWZ Write Enable to Output in High-Z(1,2) tOW Output Active from End-of-Write (1,2) (4) tWDD Write Pulse to Data Delay tDDD Write Data Valid to Read Data Delay(4) 3241 tbl 10 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. Specified for OE = VIH (refer to “Timing Waveform of Write Cycle”, Note 8). 4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”. 5. 'X' in part number indicates power rating. 6.42 7 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(5,8) tWC ADDRESS (6) tAS OE tWR(3) tAW CE tHZ tWP(2) (7) R/W tWZ (7) tLZ tHZ (7) tOW DATAOUT (4) (4) tDW tDH DATAIN 3241 drw 07 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE (6) tAS (2) tWR tEW (3) R/W tDW tDH DATAIN 3241 drw 08 NOTES: 1. R/W or CE = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W = VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed but is not production tested. 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 6.42 8 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range Timing Waveform of Write with Port-to-Port Read(1, 2) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN"A" tDH VALID ADDR"B" MATCH tWDD DATA"B" VALID tDDD NOTES: 1. OE = VIL for the reading ports. 2. All timing is the same for left and right ports. Port "A" may be either of the four ports and Port "B" is any other port. Functional Description The IDT7054 provides four ports with separate control, address, and I/O pins that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port’s OE turns on the output drivers when set LOW. READ/ WRITE conditions are illustrated in the table. 3241 drw 09 Table I – Read/Write Control Any Port(1) R/W CE OE D0-7 Function X H X Z Port Deselected: Power-Down X H X Z CEP1=CEP2=CEP3=CEP4=VIH Power Down Mode ISB or ISB1 L L X DATA IN H L L DATAOUT X X H Z Data on port written into memory (2) Data in memory output on port Outputs Disabled 3241 tbl 11 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don’t Care, "Z "= High Impedance 2. For valid write operation, no more than one port can write to the same address location at the same time. 6.42 9 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range Ordering Information A XXXX A 999 A Device Type Power Speed Package A A Process/ Temperature Range Blank Tray 8 Tape and Reel Blank Commercial (0°C to +70°C) G Green PRF 128-Pin Thin Quad Plastic Flatpack (PKG128) 20 Commercial Only L Low Power 7054 32K (4K x 8) FourPort RAM Speed in nanoseconds 3241 drw 10 NOTES: LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Ordering Information Speed (ns) 20 Pkg. Code Pkg. Type Temp. Grade 7054L20PRFG PKG128 TQFP C 7054L20PRFG8 PKG128 TQFP C Orderable Part ID 6.42 10 7054L High-Speed 4K x 8 FourPort™ Static RAM Industrial and Commercial Temperature Range Datasheet Document History 01/18/99: 06/04/99: 09/01/99: 11/10/99: 05/23/00: 10/22/01: 02/20/15: 07/02/18: 07/11/19: Initiated datasheet document history Converted to new format Cosmetic typographical corrections Added additional notes to pin configurations Changed drawing format Page 1 Corrected DSC number Removed Preliminary Replaced IDT logo Page 4 Increased storage temperature parameter Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Page 2 & 3 Added date revision for pin configurations Page 5, 7 & 8 Added Industrial temp to column heading for 25ns speed to DC & AC Electrical Characteristics Page 11 Added Industrial temp offering to 25ns ordering information Page 4, 5, 7 & 8 Removed Industrial temp footnote from all tables Page 6 Changed 5ns to 3ns in AC Test Conditions table Page 1 & 11 Replaced TM logo with ® logo Page 1 Added green availability to features Page 2 Removed IDT in reference to fabrication Page 2 2V battery backup for Low-power versions are no longer offered Page 2,3 & 10 The package code PK128-1 changed to PK128 to match standard package codes Page 10 Added Tape and Reel and Green to Ordering Information Pages 1-10 Removed all military data including the G108 pin configuration, changed table headings and ordering information to indicate that there is no longer a military offering for this 7054 device Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Pages 1 & 10 Deleted obsolete Commercial 25/35ns and Industrial 25ns speed grades Pages 1 & 10 Removed standard product offering and Industrial speed grade offering Pages 2 & 10 Updated package code PK128 to PKG128 Page 10 Added Orderable Part Information CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 11 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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