709099L
HIGH-SPEED 128K x 8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
◆
◆
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Industrial: 9ns (max.)
Low-power operation
– IDT709099L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the FT/PIPE pins
Dual chip enables allow for depth expansion without
additional logic
◆
◆
◆
Counter enable and reset features
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66.7MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WR
OER
R/WL
OEL
CE0L
CE1L
FT/PIPEL
0/1
1
0
0
I/O0L - I/O7L
1
0/1
FT/PIPER
I/O0R - I/O7R
I/O
Control
I/O
Control
A16L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
CE0R
CE1R
1
0
0/1
1
0
0/1
A16R
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4846 drw 01
1
Nov.29.21
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Description
The IDT709099 is a high-speed 128K x 8 bit synchronous DualPort RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Industrial Temperature Range
With an input data register, the IDT709099 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by CE0 and CE1, permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using CMOS high-performance technology, these
devices typically operate on only 1.2W of power.
NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
Pin Configurations(1,2,3)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
76
50
77
49
78
48
47
79
80
81
82
46
45
44
83
84
43
42
709099
PNG100(4)
85
86
87
88
100-PIN TQFP
TOP VIEW
89
90
91
92
93
41
40
39
38
37
36
35
34
94
95
33
32
31
96
97
30
29
98
99
28
27
26
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100
1 2
3 4
NC
NC
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
A16L
VCC
NC
NC
NC
NC
CE0L
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
NC
NC
A6R
A5R
A4R
A3R
A2R
A1R
A0R
CNTENR
CLKR
ADSR
GND
ADSL
CLKL
CNTENL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
NC
NC
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
2
6.42
Nov.29.21
NC
NC
NC
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
VCC
I/O2R
I/O1R
I/O0R
GND
VCC
I/O0L
I/O1L
GND
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
4846 drw 02
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A16L
A0R - A16R
Address
I/O0L - I/O7L
I/O0R - I/O7R
Data Input/Output
CLKL
CLKR
Clock
ADSL
ADSR
Address Strobe
CNTENL
CNTENR
Counter Enable
CNTRSTL
CNTRSTR
Counter Reset
FT/PIPEL
FT/PIPER
Flow-Through/Pipeline
VCC
Power
GND
Ground
4846 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3)
OE
CLK
CE0
CE1
R/W
I/O0-7
X
↑
H
X
X
High-Z
Deselected—Power Down
X
↑
X
L
X
High-Z
Deselected—Power Down
X
↑
L
H
L
DATAIN
Write
L
↑
L
H
H
DATAOUT
Read
H
X
L
H
X
High-Z
Mode
Outputs Disabled
4846 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2,6)
Address
Previous
Address
Addr
Used
CLK
ADS
CNTEN
CNTRST
I/O(3)
X
X
0
↑
X
X
L
DI/O(0)
Counter Reset to Address 0
An
X
An
↑
L(4)
X
H
DI/O(n)
External Address Utilized
An
Ap
Ap
↑
H
H
H
DI/O(n)
External Address Blocked—Counter Disabled (Ap reused)
H
DI/O(n+1)
X
Ap
Ap + 1
↑
H
(5)
L
Mode
Counter Enable—Internal Address Generation
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
3
6.42
Nov.29.21
4846 tbl 03
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Recommended DC Operating
Conditions
Ambient
Temperature(2)
GND
Vcc
0OC to +70OC
0V
5.0V + 10%
-40OC to +85OC
0V
5.0V + 10%
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Industrial Temperature Range
Symbol
4846 tbl 04
Parameter
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
VIL
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
(2)
-0.5
(1)
6.0
0.8
____
V
V
4846 tbl 05
NOTES:
1. VTERM must not exceed Vcc + 10%.
2. VIL > -1.5V for pulse width less than 10ns.
Capacitance(1)
Absolute Maximum Ratings(1)
Symbol
(2)
Rating
Commercial
& Industrial
Unit
(TA = +25°C, f = 1.0MHz)
Symbol
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
Storage
Temperature
-65 to +150
o
IOUT
DC Output
Current
CIN
COUT(3)
50
C
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
4846 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
C
mA
4846 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
709099L
Symbol
Parameter
(1)
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VCC = 5.5V, VIN = 0V to V CC
___
5
µA
|ILO|
Output Leakage Current
CE0 = VIH or CE1 = VIL, VOUT = 0V to V CC
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
4
6.42
Nov.29.21
V
4846 tbl 08
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VCC = 5V ± 10%)
709099L9
Com'l
& Ind
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
709099L12
Com'l Only
Typ. (4)
Max.
Typ.(4)
Max.
Unit
mA
Dynamic Operating
Current
(Both Ports Active)
CEL and CER= VIL
Outputs Disabled
f = fMAX(1)
COM'L
L
250
400
230
355
IND
L
300
430
____
____
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
L
80
135
70
110
IND
L
95
160
____
____
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(3)
Active Port Outputs
Disabled, f=fMAX(1)
COM'L
L
175
275
150
240
IND
L
195
295
____
____
Full Standby Current
(Both Ports CMOS Level Inputs)
Both Ports CER and
CEL > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L
L
0.5
3.0
0.5
3.0
IND
L
____
____
Full Standby Current
(One Port CMOS Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port
Outputs Disabled, f = fMAX(1)
COM'L
L
140
225
IND
L
____
____
0.5
6.0
170
270
190
290
mA
mA
mA
mA
4846 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of
GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 150mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
5
6.42
Nov.29.21
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns Max.
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1,2 and 3
4846 tbl 10
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
30pF
347Ω
347Ω
4846 drw 04
4846 drw 05
Figure 1. AC Output Test load.
8
7
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
6
tCD1,
tCD2
(Typical, ns)
5
4
3
2
1
0
20 40 60 80 100 120 140 160 180 200
-1
Capacitance (pF)
4846 drw 06
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6
6.42
Nov.29.21
5pF*
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3) (VCC = 5V ± 10%=)
709099L9
Com'l
& Ind
Symbol
Parameter
(2)
tCYC1
Clock Cycle Time (Flow-Through)
tCYC2
Clock Cycle Time (Pipelined)(2)
tCH1
Clock High Time (Flow-Through)(2)
tCL1
tCH2
Clock Low Time (Flow-Through)
Clock High Time (Pipelined)
(2)
(2)
(2)
709099L12
Com'l Only
Min.
Max.
Min.
Max.
Unit
25
____
30
____
ns
15
____
20
____
ns
12
____
12
____
ns
12
____
12
____
ns
6
____
8
____
ns
ns
tCL2
Clock Low Time (Pipelined)
6
____
8
____
tR
Clock Rise Time
____
3
____
3
ns
tF
Clock Fall Time
____
3
____
3
ns
tSA
Address Setup Time
4
____
4
____
ns
tHA
Address Hold Time
1
____
1
____
ns
tSC
Chip Enable Setup Time
4
____
4
____
ns
tHC
Chip Enable Hold Time
1
____
1
____
ns
tSW
R/W Setup Time
4
____
4
____
ns
tHW
R/W Hold Time
1
____
1
____
ns
tSD
Input Data Setup Time
4
____
4
____
ns
tHD
Input Data Hold Time
1
____
1
____
ns
ADS Setup Time
4
____
4
____
ns
ADS Hold Time
1
____
1
____
ns
CNTEN Setup Time
4
____
4
____
ns
CNTEN Hold Time
1
____
1
____
ns
ns
tSAD
tHAD
tSCN
tHCN
tSRST
CNTRST Setup Time
4
____
4
____
tHRST
CNTRST Hold Time
1
____
1
____
ns
tOE
Output Enable to Data Valid
____
12
____
12
ns
2
____
2
____
ns
ns
tOLZ
tOHZ
(1)
Output Enable to Output Low-Z
(1)
Output Enable to Output High-Z
tCD1
Clock to Data Valid (Flow-Through)
tCD2
Clock to Data Valid (Pipelined)(2)
tDC
Data Output Hold After Clock High
tCKHZ
tCKLZ
(2)
(1)
Clock High to Output High-Z
(1)
Clock High to Output Low-Z
1
7
1
7
____
20
____
25
ns
____
9
____
12
ns
2
____
2
____
ns
2
9
2
9
ns
2
____
2
____
ns
ns
Port-to-Port Delay
tCWDD
Write Port Clock High to Read Data Delay
____
35
____
40
tCCS
Clock-to-Clock Setup Time
____
15
____
15
ns
4846 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device
characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) to either the Left or Right ports when FT/PIPE = VIH. Flow-Through parameters (tCYC1, tCD1) apply when FT/PIPE
= VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER and FT/PIPEL.
7
6.42
Nov.29.21
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Read Cycle for
Flow-Through Output (FT/PIPE"X" = VIL)(3,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
tHC
(4)
CE1
R/W
tSW
tHW
tSA
tHA
(5)
ADDRESS
An
An + 1
An + 2
tCD1
tCKHZ (1)
Qn
DATAOUT
Qn + 1
tCKLZ (1)
OE
An + 3
tDC
tOHZ
Qn + 2
(1)
tOLZ
tDC
(1)
(2)
tOE
4846 drw 07
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE"X" = VIH)(3,6)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(4)
CE1
tSB
R/W
(5)
ADDRESS
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
tHB
Qn + 1
(1)
tOHZ
Qn + 2
(1)
tOLZ
(6)
(1)
(2)
OE
tOE
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL and CNTRST = VIH.
4. The output is disabled (High-Impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
6. 'X' here denotes Left or Right port. The diagram is with respect to that port.
8
6.42
Nov.29.21
4846 drw 08
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC
A6
A5
A4
A3
A2
A1
tHC
tSC tHC
tCD2
Q0
DATAOUT(B1)
tCD2
Q3
tCKLZ
(3)
tCKHZ (3)
tHA
A0
ADDRESS(B2)
tCKHZ
Q1
tDC
tDC
tSA
(3)
tCD2
A6
A5
A4
A3
A2
A1
tSC tHC
CE0(B2)
tSC
tHC
tCKHZ (3)
tCD2
DATAOUT(B2)
tCKLZ
(3)
Q2
tCD2
Q4
tCKLZ (3)
4846 drw 09
Timing Waveform of Write with Port-to-Port Flow-Through Read(4,5,7)
CLK "A"
tSW tHW
R/W "A"
tSA
ADDRESS "A"
NO
MATCH
MATCH
tSD
DATAIN "A"
tHA
tHD
VALID
tCCS
(6)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCWDD
(6)
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
4846 drw 10
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709099 for this waveform, and are setup for depth expansion in this example.
ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE, and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.
3. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
9
6.42
Nov.29.21
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(2)
tCKHZ
(1)
(1)
tCD2
tCKLZ
Qn + 3
Qn
DATAOUT
NOP(5)
READ
WRITE
READ
4846 drw 11
Timing Waveforn of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
(4)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Dn + 2
tCD2
(2)
An + 3
An + 4
An + 5
tHD
Dn + 3
tCKLZ(1)
tCD2
Qn
DATAOUT
Qn + 4
(1)
tOHZ
OE
READ
WRITE
READ
4846 drw 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data integrity.
10
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709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1
tCYC1
tCL1
CLK
CE0
tSC tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(2)
tCD1
tCD1
Qn
DATAOUT
tCD1
Qn + 3
Qn + 1
(1)
(1)
tDC
tCKHZ
(5)
NOP
READ
tCKLZ
WRITE
tDC
READ
4846 drw 13
.
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
ADDRESS
tSA
An
tHA
An +1
An + 2
DATAIN
Dn + 2
(2)
DATAOUT
An + 3
An + 4
An + 5
tSD tHD
Dn + 3
tDC
tCD1
Qn
tOE
tCD1
(1)
tOHZ
tCKLZ
(1)
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
4846 drw 14
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be rewritten to guarantee data integrity.
11
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709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
4846 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
4846 drw 16
NOTES:
1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output
remains constant for subsequent clocks.
12
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Nov.29.21
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
4846 drw 17
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
ADDRESS(4)
INTERNAL(3)
ADDRESS
An
Ax(6)
0
1
An + 2
An + 1
An + 1
An
tSW tHW
R/W
ADS
CNTEN
tSRST tHRST
CNTRST
tSD
tHD
D0
DATAIN
Qn
Q1
Q0
DATAOUT(5)
.
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
READ
ADDRESS n+1
4846 drw 18
NOTES:
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
2. CE0 = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written
to during this cycle.
13
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709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
A Functional Description
Depth and Width Expansion
The IDT709099 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory applications.
CE0 = VIL or CE1 = VIL for one clock cycle will power down the
internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709099's for depth
expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 = VIL and CE1 = VIH to reactivate
the outputs.
The IDT709099 features dual chip enables (refer to Truth Table I)
in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various
chip enables in order to expand two devices in depth.
The 709099 can also be used in applications requiring expanded
width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 16-bit
or wider applications.
A17
CE0
IDT709099
CE1
CE1
CE1
VCC
IDT709099
VCC
CE1
CE0
CE0
Control Inputs
CE0
Control Inputs
Control Inputs
IDT709099
IDT709099
Control Inputs
4846 drw 19
Figure 4. Depth and Width Expansion with IDT709099
14
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Nov.29.21
CNTRST
CLK
ADS
CNTEN
R/W
OE
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Ordering Information
XXXXX
A
99
A
Device
Type
Power
Speed
Package
A
A
A
Process/
Temperature
Range
Blank
8
Tray
Tape and Reel
I
Industrial (-40°C to +85°C)
G
Green
PF
100-pin TQFP (PNG100)
9
Industrial Only
L
Low Power
709099
1024K (128K x 8-Bit) Synchronous Dual-Port RAM
Speed in nanoseconds
NOTES:
LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02
Note that information regarding the recently obsoleted commercial speed grade is included in this datasheet for customer convenience.
4846 drw 20
Orderable Part Information
Speed
(ns)
9
Pkg.
Code
Pkg.
Type
Temp.
Grade
709099L9PFGI
PNG100
TQFP
I
709099L9PFGI8
PNG100
TQFP
I
Orderable Part ID
Datasheet Document History
9/30/99:
11/10/99:
12/22/99:
1/5/01:
11/09/01:
Initial Public Release
Replaced IDT logo
Page 1
Added missing diamond
Page 3
Changed information in Truth Table II
Page 4
Increased storage temperature parameter
Clarified TA parameter
Page 5
DC Electrical parameters–changed wording from "open" to "disabled"
Added overbar to CE in notes
Changed ±200mV to 0mV in notes
Removed Preliminary status
Page 2
Added date revision for pin configuration
Page 5 & 7
Added Industrial temp to column heading and values for 9ns speed to DC & AC Electrical Characteristics
Page 15
Added Industrial temp offering to 9ns ordering information
Page 4, 5 & 7 Removed Industrial temp footnote from all tables
15
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Nov.29.21
709099L
High-Speed 128K x 8 Synchronous Pipelined Dual-Port Static RAM
Industrial Temperature Range
Datasheet Document History (continued)
01/29/09:
08/20/10:
Page 15
Page 1
Page 15
Page 7
Pages 8-11
04/08/15:
01/24/18:
08/13/19:
11/29/21:
Page 1
Page 5
Page 7
Page 15
Page 1
Page 2
Page 2 &16
Page 6
Page 16
Page 1 & 15
Page 2
Page 15
Page 1 -17
Page 2
Page 15
Removed "IDT" from orderable part number
Added green parts availability to features
Added green indicator to ordering information
In order to correct the header notes of the AC Elect Chars Table and align them with the Industrial temp range
values located in the table, the commercial TA header note has been removed
In order to correct the footnotes of timing diagrams, CNTEN has been removed to reconcile the footnotes
with the CNTEN logic definition found in Truth Table II - Address Counter Control
Removed the 7.5ns speed grade from the commercial offering
Removed the 7ns speed grade from the commercial offering in the DC Electrical Characteristics table
Removed the 7ns speed grade from the commercial offering in the AC Electrical Characteristics table
Removed the 7ns speed grade from the commercial offering in the ordering information
Numbers for Pipelined Output Mode updated: includes clock to data out, cycle time and operation
Removed IDT in reference to fabrication
The package code PN100-1 changed to PN100 to match standard package codes
Corrected typo in the Typical Output Derating(Lumped Capitive Load) diagram
Added Tape and Reel to Ordering Information
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Deleted obsolete Commercial grades 9/12ns
Rotated PNG100 TQFP pin configuration to accurately reflect pin 1 orientation
Added Orderable Part Information table
Source file updated to reflect previous Corporate Marketing rebranding
Updated header by removing obsoleted commercial temperature range
Updated package code
Removed obsoleted commercial entry from Ordering Information
16
6.42
Nov.29.21
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