70P3519S166BCGI

HIGH-SPEED 1.8V 256/128K x 36 IDT70P3519/99 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V/2.5V/1.8V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location Low Power High-speed data access – Commercial: 3.4 (200MHz)/3.6ns (166MHz) – Industrial: 3.6ns (166MHz) Selectable Pipelined or Flow-Through output mode Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 5ns cycle time, 200MHz operation (14Gbps bandwidth) – Fast 3.4ns clock to data out – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time ◆ ◆ ◆ ◆ ◆ Counter enable and repeat features Interrupt and Collision Detection Flags Separate byte controls for multiplexed bus and bus matching compatibility Dual Cycle Deselect (DCD) for Pipelined Output Mode 1.8V (±100mV) power supply for core LVTTL compatible,1.8V to 3.3V power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available at 166MHz Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine pitch Ball Grid Array (fpBGA) Supports JTAG features compliant with IEEE 1149.1 Green parts available, see ordering information R O F D E D S N N E IG M S M E O D C W E E R N ◆ ◆ ◆ ◆ Functional Block Diagram BE3L BE 2L BE1L BE0L FT/PIPEL 1/0 0a 1a 0b 1b 0c 1c 0d 1d 1d 0d 1c 0c 1b 0b 1a 0a a b c d d c b a R/WL CE0L CE1L 1/0 1 1 BE3R BE2R BE1R BE0R FT/PIPER R/WR CE0R CE1R 0 0 1/0 T O N OE L B B WW 0 1 L L B B B WWW 2 3 3 L L R Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L B W 2 R B B WW 1 0 RR 1/0 1d 0d 1c 0c 1b 0b 1a 0a FT/PIPEL OER Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R , 0a 1a 0b 1b 0c 1c 0d 1d FT/PIPER 0/1 0/1 abcd dcba 256/128K x 36 MEMORY ARRAY I/O0L - I/O 35L Din_L I/O0R - I/O35R Din_R CLKR CLKL A0L REPEATL ADSL CNTENL , A17R(1) A17L(1) Counter/ Address Reg. ADDR_L Counter/ Address Reg. ADDR_R TDI INTERRUPT COLLISION DETECTION LOGIC CE 0 L CE1L R/W L A0R REPEATR ADSR CNTENR CE0 R CE1R JTAG TDO TCK TMS TRST R/W R COL L INTL COLR INTR (2) ZZL ZZ CONTROL (2) ZZR LOGIC NOTES: 1. Address A17 is a NC for the IDT70P3599. +. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 7144 drw 01 JUNE 2009 1 ©2009 Integrated Device Technology, Inc. DSC 7144/3 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70P3519/99 is a high-speed 256/128K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70P3519/99 has been optimized for applications having unidirectional T O N or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70P3519/99 can support an operating voltage of 3.3V, 2.5V or 1.8V on one or both ports. The power supply for the core of the device (VDD) is 1.8V. R O F D E D S N N E IG M S M E O D C W E E R N 6.422 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Configuration (2,3,4) 70P3519/99BC BC-256(5) 256-Pin BGA Top View(6) 02/12/08 A1 NC B1 I/O18L C1 A2 TDI B2 NC C2 I/O18R I/O19L D1 D2 A3 NC B3 TDO C3 VSS D3 A4 A5 A6 A17L(1) A 14L A11L B4 B6 NC B5 A15L A12L A7 A 8L B7 A 9L A9 A8 BE2L CE1L B9 B8 BE3L A10 A11 A12 OEL CNTENL A5L B10 B11 CE0L R/WL REPEATL B12 A4L A13 A2L B13 A1L A14 A0L B14 VDD R O F A15 NC B15 I/O17L D E D S N N E IG M S M E O D C W E E R N C4 A16L D4 C5 A13L D5 C6 A10L D6 C7 A7L D7 C9 C8 C10 C11 BE1L BE0L CLKL ADSL D9 D8 D10 D11 C12 A6L D12 C13 A3L D13 C14 NC D14 C15 A16 NC B16 NC C16 I/O17R I/O16L D15 D16 I/O20R I/O19R I/O20L PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R E1 E2 E3 E4 E5 I/O21R I/O21L I/O22L VDDQL VDD F1 F2 F3 F4 F5 I/O23L I/O22R I/O23R VDDQL VDD G1 G2 G3 G4 G5 I/O24R I/O24L I/O25L VDDQR V SS H1 H2 H3 H4 H5 I/O26L I/O25R I/O26R VDDQR VSS J1 J2 J3 J4 J5 I/O27L I/O28R I/O27R VDDQL ZZ R K1 K2 K3 K4 K5 I/O29R I/O29L I/O28L VDDQL V SS L1 L2 L3 L4 L5 I/O30L I/O31R I/O30R VDDQR VDD M1 M2 M3 M4 I/O32R I/O32L I/O31L VDDQR N1 N2 N3 T O N N4 M5 VDD N5 E6 VDD E7 INTL F7 F6 NC G6 VSS H6 VSS J6 VSS K6 VSS L6 NC M6 VDD N6 COLL G7 VSS H7 VSS J7 VSS K7 VSS L7 E8 E9 VSS F9 F8 VSS INT R N7 VSS H8 V SS H9 VSS J8 VSS J9 VSS K8 V SS K9 VSS L8 V SS L9 V SS M9 M8 VSS N8 V SS G9 G8 COLR VSS M7 V SS V SS N9 E10 VSS F10 VSS G10 VSS H10 VSS J10 VSS K10 VSS L10 VSS M10 VSS N10 E11 VDD F11 VSS G11 VSS H11 VSS J11 VSS K11 VSS L11 VSS M11 VDD N11 E12 E13 F12 P2 P3 I/O35R I/O34L TMS R1 I/O35L T1 NC R2 NC T2 TCK R3 TRST T3 P4 A16R R4 NC T4 P5 A13R R5 A15R T5 NC A17R(1) A14R P6 A10R R6 A12R T6 A11R P7 A7R R7 A9R T7 A8R P8 P9 P10 P11 BE1R BE0R CLKR ADSR R8 R9 R10 R11 G12 VSS H12 VSS J12 T9 T10 T11 K12 VSS L12 VDD M12 F13 6.42 3 F14 F15 F16 G13 G14 G15 G16 VDDQL I/O10L I/O11L I/O11R H13 H14 VDDQL I/O9R J13 J14 H15 H16 IO9L I/O10R J15 J16 K13 K14 K15 K16 V DDQR I/O6R I/O6L I/O7L L13 L14 V DDQL I/O5L M13 M14 L15 L16 I/O4R I/O5R M15 M16 VDD V DDQL I/O3R I/O3L I/O4L N12 P12 A6R R12 T12 BE2R CE1R OER CNTENR A 5R NOTES: 1. Pin is a NC for IDT70P3599. 2. All VDD pins must be connected to 1.8V power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. E16 ZZL VDDQR I/O8R I/O7R I/O8L BE3R CE0R R/WR REPEATR A4R T8 E15 VDD VDDQR I/O12R I/O13R I/O12L N13 I/O33L I/O34R I/O33R PIPE/FTR VDDQR VDDQR VDDQL VDDQL VDDQR V DDQR VDDQL VDDQL VDD P1 E14 VDD VDDQR I/O13L I/O14L I/O14R P13 A3R R13 A1R T13 A2R N14 I/O2L P14 N15 P15 I/O0L I/O0R R14 NC T14 A0R N16 I/O1R I/O2R R15 NC T15 NC P16 I/O1L R16 NC , T16 NC 7144 drw 02d , IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Configuration (2,3,4) (con't.) 02/12/08 A1 A2 I/O19L I/O18L B1 B2 A3 VSS B3 I/O20R VSS I/O18R C1 C2 C3 A4 A5 TDO COLL B4 B5 I/O22L E1 D2 VSS E2 D3 C4 C5 D4 D5 I/O21L I/O20L A15L E3 A16L B6 TDI A17L(1) A13L VDDQL I/O19R VDDQR PL/FTL INTL D1 A6 C6 A14L D6 A11L A7 A12L B7 A9L C7 A10L D7 A7L A8 A8L B8 BE2L C8 A9 BE1L B9 CE0L C9 BE3L CE1L D8 BE0L D9 VDD A10 VDD B10 VSS C10 VSS D10 A11 A12 A13 CLKL CNTENL A4L B11 ADSL C11 R/WL D11 OEL REPEATL B12 A5L C12 A6L D12 A3L B13 A1L C13 A2L D13 F2 F3 VDDQL I/O23R I/O24L G1 G2 I/O26L VSS H1 H2 G3 J2 VDDQL VDD K1 I/O28R L1 K2 VSS L2 J3 VSS K3 I/O27R L3 M2 M3 I/O31L P1 N2 N3 P3 G4 VSS R2 R3 70P3519/99BF BF-208(5) H14 VDD J4 J14 ZZR ZZL 208-Pin fpBGA Top View(6) K4 VSS K14 T2 T3 L14 I/O6R M4 M14 VSS N4 R4 T4 I/O33R I/O34L VDDQL TMS U1 VSS U2 U3 R O F B15 U4 B17 B16 VDDQR I/O16L I/O15R C15 C16 C17 D15 D16 VSS D17 E15 F15 E17 E16 VSS I/O13L F17 F16 G15 G16 G17 H15 I/O9R J15 VDD K15 H17 H16 VSS N14 L15 I/O7L M15 VSS VDDQR K16 K17 P6 R5 R6 T5 INTR U5 I/O35L PL/FTR COLR A15R T6 A14R U6 A11R P7 A12R R7 A9R T7 A10R U7 A7R P8 A8R R8 P9 BE1R R9 BE 2R CE0R T8 T9 BE3R CE1R U8 BE0R U9 VDD P10 VDD R10 VSS T10 VSS U10 OER P11 P12 P13 CLKR CNTEN R A4R R11 ADSR T11 R/WR R12 A5R T12 A6R U12 A3R R13 A1R T13 A2R U13 A0R P14 VSS NC T14 VSS U14 VDD I/O8L M17 M16 I/O6L I/O5R VDDQR N15 P15 I/O2L I/O3L R14 VSS L17 L16 N17 N16 I/O3R VDDQL I/O4R P5 I/O10R J17 J16 I/O7R VDDQL I/O8R L4 I/O33L I/O34R TCK A17R(1) A13R T O N T1 D14 VSS I/O9L VDDQL I/O10L I/O11R I/O32R I/O32L VDDQR I/O35R TRST A16R R1 I/O17L VDD I/O16R I/O15L G14 H4 P4 A17 A16 VSS I/O12R I/O11L VDDQR VSS VSS I/O31R I/O30L P2 NC D E D S N N E IG M S M E O D C W E E R N F4 VDDQL I/O29L I/O30R VSS N1 C14 F14 I/O29R I/O28L VDDQR I/O27L M1 NC A15 I/O12L I/O13R VDD I/O26R VDDQR I/O25R J1 B14 E14 E4 I/O25L I/O24R H3 A0L VDD I/O17R VDDQL I/O14L I/O14R I/O23L I/O22R VDDQR I/O21R F1 A14 R15 I/O5L P17 P16 VSS R16 I/O4L R17 VDDQL I/O1R VDDQR T15 I/O0R U15 NC T16 T17 VSS I/O2R U17 U16 I/O0L I/O1L 7144 drw 02c NOTES: 1. Pin is a NC for IDT70P3599. 2. All VDD pins must be connected to 1.8V power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 6.424 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (Input)(5) R/WL R/WR Read/Write Enable (Input) OER OEL (4) Output Enable (Input) (4) A0L - A17L A0R - A17R Address (Input) I/O0L - I/O35L I/O0R - I/O35R Data Input/Output CLKL CLKR Clock (Input) PL/FTL PL/FTR Pipeline/Flow-Through (Input) ADSL ADSR Address Strobe Enable (Input) CNTENL CNTENR Counter Enable (Input) REPEATL REPEATR Counter Repeat(2) BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) (Input)(5) VDDQL VDDQR ZZL ZZR R O F D E D S N N E IG M S M E O D C W E E R N Power (I/O Bus) (3.3V, 2.5V or 1.8V)(1) (Input) Sleep Mode pin(3) (Input) (1) VDD Power (1.8V) (Input) VSS Ground (0V) (Input) TDI Test Data Input TDO Test Data Output TCK Test Logic Clock (10MHz) (Input) TMS Test Mode Select (Input) TRST Reset (Initialize TAP Controller) (Input) INTL INTR Interrupt Flag (Output) COLL COLR Collision Alert (Output) NOTES: 1. VDD and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 3. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 4. Address A17x is a NC for the IDT70P3599. 5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the signals take two cycles to deselect. 7144 tbl 01 T O N 6.42 5 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control(1,2,3,4) OE CLK CE0 CE 1 BE3 BE2 BE1 BE0 R/W ZZ Byte 3 I/O27-35 Byte 2 I/O18-26 Byte 1 I/O9-17 Byte 0 I/O0-8 X ↑ H X X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down X ↑ X L X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down X ↑ L H H H H H X L High-Z High-Z High-Z High-Z All Bytes Deselected MODE X ↑ L H H H H L L L High-Z High-Z High-Z DIN Write to Byte 0 Only X ↑ L H H H L H L L High-Z High-Z DIN High-Z Write to Byte 1 Only X ↑ L H H L H H L L High-Z DIN High-Z High-Z Write to Byte 2 Only X ↑ L H L H H H L L DIN High-Z High-Z High-Z Write to Byte 3 Only X ↑ L H H H L L L L High-Z High-Z DIN DIN Write to Lower 2 Bytes Only X ↑ L H L L H H L L DIN DIN High-Z High-Z Write to Upper 2 bytes Only X ↑ L H L L L L L L DIN DIN DIN DIN Write to All Bytes L ↑ L H H L ↑ L H H L ↑ L H H L ↑ L H L L ↑ L H H L ↑ L H L L ↑ L H L H ↑ X X X X X X X X R O F D E D S N N E IG M S M E O D C W E E R N H H L H L High-Z High-Z High-Z DOUT Read Byte 0 Only H L H H L High-Z High-Z DOUT High-Z Read Byte 1 Only L H H H L High-Z DOUT High-Z High-Z Read Byte 2 Only H H H H L DOUT High-Z High-Z High-Z Read Byte 3 Only H L L H L High-Z High-Z DOUT DOUT Read Lower 2 Bytes Only L H H H L DOUT DOUT High-Z High-Z Read Upper 2 Bytes Only L L L H L DOUT DOUT DOUT DOUT X X X X L High-Z High-Z High-Z High-Z Outputs Disabled X X X X H High-Z High-Z High-Z High-Z Sleep Mode Read All Bytes NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = X. 3. OE and ZZ are asynchronous input signals. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. 7144 tbl 02 Truth Table II—Address Counter Control(1,2) Address An X X X Previous Internal Address Internal Address Used CLK X An ↑ L X H DI/O (n) An An + 1 ↑ H L H DI/O(n+1) An + 1 An + 1 ↑ H H H DI/O(n+1) X An ↑ X X L DI/O(n) T O N ADS(4) CNTEN(5) REPEAT(4,6) MODE I/O(3) External Address Used Counter Enabled—Internal Address generation External Address Blocked—Counter disabled (An + 1 reused) Counter Set to last valid ADS load 7144 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. 6.426 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Ambient Temperature Grade O Commercial GND VDD 0V 1.8V + 100mV 0V 1.8V + 100mV O 0 C to +70 C O Industrial O -40 C to +85 C 7144 tbl 04 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Recommended DC Operating Conditions with VDDQ at 1.8V Symbol Parameter Min. VDD Core Supply Voltage VDDQ I/O Supply Voltage VSS Ground VIH Input High Voltage VIH Input High Voltage JTAG(3) VIH Input High Voltage ZZ, PIPE/FT VIL Input Low Voltage VIL Input Low Voltage ZZ, PIPE/FT _ Typ. Max. Unit D E D S N N E IG M S M E O D C W E E R N 1.7 1.8 1.9 V 1.7 1.8 1.9 V 0 0 0 V (2) V 0.7 VDDQ ____ VDDQ + 100mV 0.7 VDDQL ____ VDDQL + 100mV(2) V VDDQ - 0.2V ____ VDDQ + 100mV(2) V -0.3(1) ____ 0.3 VDDQ V -0.3(1) ____ 0.2 V 7144 tbl 05c NOTES: 1. VIL (min.) = -0.75V for pulse width less than tCYC/2, or 5ns, whichever is less. 2. VIH (max.) = VDDQ + 0.75V for pulse width less than tCYC/2 or 5ns, whichever is less. 3. JTAG is driven by the left port VDDQL. Recommended DC Operating Conditions with VDDQ at 2.5V Symbol T O N Parameter VDD Core Supply Voltage VDDQ I/O Supply Voltage VSS Ground R O F Min. Typ. Max. Unit 1.7 1.8 1.9 V 2.4 2.5 2.6 V 0 0 0 V (2) V VIH Input High Volltage 1.7 ____ VIH Input High Voltage _ JTAG(3) 1.7 ____ VDDQL + 100mV(2) V VIH Input High Voltage ZZ, PIPE/FT VDDQ - 0.2V ____ VDDQ + 100mV(2) V VIL Input Low Voltage -0.3(1) ____ 0.7 V VIL Input Low Voltage ZZ, PIPE/FT -0.3(1) ____ 0.2 V VDDQ + 100mV 7144 tbl 05a NOTES: 1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less. 2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less. 3. JTAG is driven by the left port VDDQL. 6.42 7 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Recommended DC Operating Conditions with VDDQ at 3.3V Symbol Parameter Min. Typ. Max. Unit V VDD Core Supply Voltage 1.7 1.8 1.9 V DDQ I/O Supply Voltage 3.15 3.3 3.45 V VSS Ground 0 0 0 V VIH Input High Voltage 2.0 ____ V DDQ + 150mV (2) V 2.0 ____ VDDQL + 150mV(2) V VDDQ - 0.2V ____ V DDQ + 150mV (2) V (1) _ VIH Input High Voltage JTAG(3) VIH Input High Voltage ZZ, PIPE/FT V IL Input Low Voltage -0.3 ____ 0.8 V V IL Input Low Voltage ZZ, PIPE/FT -0.3(1) ____ 0.2 V D E D S N N E IG M S M E O D C W E E R N 7144 tbl 05b NOTES: 1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less. 2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less. 3. JTAG is driven by the left port VDDQL. Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Unit VTERM (VDD) VDD Terminal Voltage with Respect to GND VTERM(2) (VDDQ) VDDQ Terminal Voltage with Respect to GND VTERM(2) (INPUTS and I/O's) Input and I/O Terminal Voltage with Respect to GND TBIAS(3) Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -65 to +150 o C +150 o C TJN Junction Temperature IOUT(For VDDQ = 3.3V) DC Output Current T O N IOUT(For VDDQ = 2.5V) DC Output Current IOUT(For VDDQ = 1.8V) DC Output Current R O F - 0.5 to + 2.5 V - 0.3 to + 4.2 V - 0.3 to min. {VDDQ + 0.3, 4.2}(4) V 50 mA 40 mA 35 mA 7144 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed VDDQ during power supply ramp up. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. 4. VTERM (Inputs and I/O's) -0.3 to min {VDDQ + 0.3, 4.2} means that the range is -0.3V to either VDDQ +0.3V or 4.2V whichever is less. 6.428 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Capacitance(1) (TA = +25°C, F = 1.0MHZ) Symbol Parameter CIN Input Capacitance (3) Output Capacitance COUT Conditions(2) Max. Unit VIN = 3dV 8 pF VOUT = 3dV 10.5 pF 7144 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. R O F D E D S N N E IG M S M E O D C W E E R N DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(VDD = 1.8V ± 100mV) 70P3519/99S Symbol Parameter |ILI| Test Conditions Input Leakage Current (1) |ILI| JTAG & ZZ Input Leakage Current (2) |ILO| Output Leakage Current VOL (3.3V) Output Low Voltage VOH (3.3V) Output High Voltage VOL (2.5V) Output Low Voltage VOH (2.5V) Output High Voltage VOL (1.8V) Output Low Voltage VOH (1.8V) Output High Voltage Min. Max. Unit VDDQ = Max., VIN = 0V to VDDQ ___ 10 µA VDDQL = Max., VIN = 0V to V DDQL ___ 30 µA CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ ___ 10 µA IOL = +4mA, VDDQ = Min. ___ 0.4 V IOH = -4mA, VDDQ = Min. 2.4 ___ V IOL = +2mA, VDDQ = Min. ___ 0.4 V IOH = -2mA, VDDQ = Min. 2.0 ___ V IOL = +2mA, VDDQ = Min. ___ 0.4 V IOH = -2mA, VDDQ = Min. NOTES: 1. Applicable only for TMS, TDI and TRST inputs. 2. Outputs tested in tri-state mode. T O N 6.42 9 VDDQ -0.40 ___ V 7144 tbl 08 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3)(VDD = 1.8V ± 100mV) 70P3519/99 S200 Com'l Only Symbol IDD ISB1(6) ISB2(6) ISB3 ISB4(6) Izz Parameter Test Condition Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH f = fMAX(1) Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V or VIN < 0.2V, f = 0(2) Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5) VIN > VDDQ - 0.2V or VIN < 0.2V Active Port, Outputs Disabled, f = fMAX(1) Sleep Mode Current (Both Ports - TTL Level Inputs) ZZL = ZZR = VIH f=fMAX(1) Version 70P3519/99 S166 Com'l & Ind Typ.(4) Max. Typ.(4) Max. 285 COM'L S 226 325 190 IND S ___ ___ 190 325 COM'L S 120 195 102 170 IND S ___ ___ 102 205 COM'L S 176 265 148 230 IND S ___ ___ 148 270 COM'L S 15 45 15 45 IND S ___ ___ 15 60 COM'L S 176 265 148 230 IND S ___ ___ 148 270 COM'L S 15 45 15 45 S ___ ___ 15 60 Unit mA R O F mA mA D E D S N N E IG M S M E O D C W E E R N IND mA mA mA 7144 tbl 09 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS". 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 1.8V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V "X" represents "L" for left port or "R" for right port. 6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH. T O N 6.42 10 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ - 3.3V/2.5V/1.8V) Input Pulse Levels (Address & Controls) GND to 3.0V/GND to 2.4V/GND to 1.7V Input Pulse Levels (I/Os) GND to 3.0V/GND to 2.4V/GND to 1.7V Input Rise/Fall Times 2ns Input Timing Reference Levels 1.5V/1.25V/0.85V Output Reference Levels 1.5V/1.25V/0.85V Output Load Figure 1 R O F 7144 tbl 10 D E D S N N E IG M S M E O D C W E E R N 50Ω DATAOUT 50Ω , 1.5V/1.25V/0.85V 10pF (Tester) 7144 drw 03 Figure 1. AC Output Test load. ∆ tCD (Typical, ns) T O N ∆ Capacitance (pF) from AC Test Load 6.42 11 7144 drw 04 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(2,3) (VDD = 1.8V ± 100mV, TA = 0°C to +70°C) 70P3519/99 S200 Com'l Only Symbol Parameter 70P3519/99 S166 Com'l & Ind Min. Max. Min. Max. Unit tCYC1 Clock Cycle Time (Flow-Through)(1) 15 ____ 20 ____ ns tCYC2 Clock Cycle Time (Pipelined)(1) 5 ____ 6 ____ ns tCH1 Clock High Time (Flow-Through)(1) 6 ____ 8 ____ ns 8 (1) tCL1 Clock Low Time (Flow-Through) 6 ____ tCH2 Clock High Time (Pipelined)(2) 2 ____ 2.4 tCL2 Clock Low Time (Pipelined)(1) 2 ____ 2.4 tSA Address Setup Time 1.5 ____ 1.7 0.5 1.7 R O F ____ ns ____ ns ____ ns ____ ns ____ ns ____ ns ____ ns ____ ns ns tHA Address Hold Time 0.5 ____ tSC Chip Enable Setup Time 1.5 ____ tHC Chip Enable Hold Time 0.5 ____ 0.5 tSB Byte Enable Setup Time 1.5 ____ 1.7 0.5 ____ 0.5 ____ 1.5 ____ 1.7 ____ ns 0.5 ____ 0.5 ____ ns 1.5 ____ 1.7 ____ ns 0.5 ____ 0.5 ____ ns 1.5 ____ 1.7 ____ ns 0.5 ____ 0.5 ____ ns 1.5 ____ 1.7 ____ ns 0.5 ____ 0.5 ____ ns 1.5 ____ 1.7 ____ ns 0.5 ____ 0.5 ____ ns ____ 4.4 ____ 4.4 ns 1 ____ 1 ____ ns 1 3.4 1 3.6 ns ____ 10 ____ 12 ns ____ 3.4 ____ 3.6 ns 1 ____ 1 ____ ns tHB Byte Enable Hold Time tSW R/W Setup Time tHW R/W Hold Time tSD Input Data Setup Time tHD Input Data Hold Time tSAD ADS Setup Time tHAD ADS Hold Time tSCN CNTEN Setup Time tHCN CNTEN Hold Time tSRPT REPEAT Setup Time tHRPT REPEAT Hold Time D E D S N N E IG M S M E O D C W E E R N tOE Output Enable to Data Valid tOLZ(4) Output Enable to Output Low-Z tOHZ(4) Output Enable to Output High-Z tCD1 Clock to Data Valid (Flow-Through)(1) (1) tCD2 Clock to Data Valid (Pipelined) tDC Data Output Hold After Clock High tCKHZ(4) Clock High to Output High-Z 1 3.4 1 3.6 ns tCKLZ(4) Clock High to Output Low-Z 1 ____ 1 ____ ns ____ 7 ____ 7 ns Interrupt Flag Reset Time ____ 7 ____ 7 ns Collision Flag Set Time ____ 3.4 ____ 3.6 ns ____ 3.4 ____ 3.6 ns Sleep Mode Set Cycles 2 ____ 2 ____ cycles Sleep Mode Recovery Cycles 3 ____ 3 ____ cycles 4 ____ 5 ____ ns tINS tINR tCOLS tCOLR tZZSC tZZRC T O N Interrupt Flag Set Time Collision Flag Reset Time Port-to-Port Delay tCO tOFS Clock-to-Clock Offset Please refer to Collision Detection Timing Table on Page 21 Clock-to-Clock Offset for Collision Detection 7144 tbl 11 NOTES: 1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when PL/FTX = VDD (1.8V). Flow-through parameters (tCYC1, tCD1) apply when PL/FT = VSS (0V) for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and PL/FT. PL/FT should be treated as DC signals, i.e. steady state during operation. 3. These values are valid for any level of VDDQ (3.3V/2.5V/1.8V). 4. Guaranteed by design (not production tested). 6.42 12 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE'X' = VIH)(1,2) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC tHC R O F (3) CE1 tSB tSB tHB BEn tHB (5) R/W (4) ADDRESS tSW tHW tSA tHA An D E D S N N E IG M S M E O D C W E E R N An + 1 (1 Latency) DATAOUT An + 2 An + 3 tDC tCD2 Qn tCKLZ OE (1) Qn + 1 Qn + 2 (5) (1) tOHZ tOLZ , tOE 7144 drw 05 Timing Waveform of Read Cycle for Flow-through Output (FT/PIPE"X" = VIL)(1,2,6) tCYC1 tCH1 CLK CE0 tSC tSC tHC tHC (3) CE1 tSB BEn tHB tSB T O N R/W tHB tSW tHW tSA ADDRESS tCL1 (4) tHA An An + 1 tCD1 An + 3 tCKHZ Qn DATAOUT OE An + 2 tDC Qn + 2 Qn + 1 tCKLZ tOHZ tOLZ (5) tDC (1) tOE 7144 drw 06 NOTES: 1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge. 2. ADS = VIL, CNTEN and REPEAT = VIH. 3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port. 6.42 13 , IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Multi-Device Pipelined Read(1,2) tCH2 tCYC2 tCL2 CLK tSA tHA A0 ADDRESS(B1) tSC tHC CE0(B1) tSC tCD2 tCKHZ Q0 DATAOUT(B1) tSC tCKHZ tHC D E D S N N E IG M S M E O D C W E E R N tHC tCD2 DATAOUT(B2) A6 A5 A4 A3 A2 A1 tSC CE0(B2) Q3 tCKLZ tDC tHA A0 ADDRESS(B2) tCD2 Q1 tDC tSA R O F tHC tCD2 A6 A5 A4 A3 A2 A1 tCKHZ tCD2 , Q4 Q2 tCKLZ tCKLZ 7144 drw 07 Timing Waveform of a Multi-Device Flow-Through Read(1,2) tCH1 CLK tSA ADDRESS(B1) CE0(B1) tH A A0 tSC tHC T O N tSA CE0(B2) A6 A5 A4 A3 A2 A1 tSC tHC DATAOUT(B1) ADDRESS(B2) tCYC1 tCL1 tHA A0 tCD1 tCKHZ tCD1 D0 tCD1 tCD1 D5 D3 D1 tDC A1 (1) tCKLZ tDC (1) tCKLZ (1) A6 A5 A4 A3 A2 tCKHZ(1) tSC tHC tSC tHC tCD1 DATAOUT(B2) tCKLZ (1) tCKHZ (1) tCD1 D2 tCKLZ (1) tCKHZ (1) D4 , 7144 drw 08 NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70P3519/99 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH. 6.42 14 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4) CLK"A" tSW tHW tSA tHA R/W"A " ADDRESS"A" tSD DATAIN"A" NO MATCH MATCH R O F tHD VALID tCO(3) CLK"B" tCD2 R/W"B" ADDRESS"B" D E D S N N E IG M S M E O D C W E E R N tSW tHW tSA tHA MATCH DATAOUT"B" NO MATCH VALID , tDC 7144 drw 09 NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to. 3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2). 4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A" Timing Waveform with Port-to-Port Flow-Through Read(1,2,4) CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" T O N CLK "B" R/W "B" ADDRESS "B" NO MATCH MATCH tSD DATAIN "A" tHA tHD VALID tCO (3) tCD1 tSW tHW tSA tHA NO MATCH MATCH tCD1 DATAOUT "B" VALID VALID tDC tDC , 7144 drw 10 NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + tCD1). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". 6.42 15 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(2) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC CE1 tSB R O F tHB BEn tSW tHW R/W (3) ADDRESS tSW tHW An tSA tHA DATAIN D E D S N N E IG M S M E O D C W E E R N An + 4 An + 3 An + 2 An + 2 An +1 tSD tHD Dn + 2 tCD2 (1) tCKLZ tCKHZ tCD2 Qn DATAOUT (4) WRITE NOP READ Qn + 3 READ 7144 drw 11 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. , Timing Waveform of Pipelined Read-to-Write-to-Read( OE Controlled)(2) tCH2 CLK CE0 tSC tHC CE1 tSB tHB T O N BEn R/W (3) ADDRESS tCYC2 tCL2 tSW tHW tSW tHW An tSA tHA An + 2 An +1 tSD DATAIN Dn + 2 tCD2 (1) Qn DATAOUT An + 3 An + 4 An + 5 tHD Dn + 3 tCKLZ tCD2 Qn + 4 (4) tOHZ OE READ WRITE READ , NOTES: 7144 drw 12 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows. 6.42 16 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read(OE = VIL)(2) tCH1 tCYC1 tCL1 CLK CE0 tSC tHC R O F CE1 tSB tHB BEn tSW tHW R/W tSW tHW (3) ADDRESS tSA An tHA D E D S N N E IG M S M E O D C W E E R N An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD1 (1) Qn DATAOUT tCD1 tCD1 Qn + 1 tDC tCKLZ tCKHZ READ NOP (5) tCD1 Qn + 3 tDC READ WRITE , 7144 drw 13 Timing Waveform of Flow-Through Read-to-Write-to-Read(OE Controlled)(2) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSB tHB BEn T O N tSW tHW R/W (3) An tSA tHA ADDRESS tSW tHW An +1 DATAIN (1) DATAOUT An + 2 tSD tHD An + 3 Dn + 2 Dn + 3 tDC tCD1 An + 4 tOE tCD1 Qn tCKLZ tOHZ An + 5 tCD1 Qn + 4 tDC OE READ WRITE READ 7144 drw 14 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 17 , IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) R O F D E D S N N E IG M S M E O D C W E E R N Qn Qx Qn + 2(2) Qn + 1 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER , Qn + 3 7144 drw 15 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCYC1 tCH1 tCL1 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN T O N DATAOUT tCD1 Qx(2) tDC READ EXTERNAL ADDRESS Qn Qn + 1 Qn + 2 READ WITH COUNTER Qn + 3(2) COUNTER HOLD , Qn + 4 READ WITH COUNTER 7144 drw 16 NOTES: 1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 18 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs)(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 R O F An + 4 An + 3 tSAD tHAD ADS D E D S N N E IG M S M E O D C W E E R N tSCN tHC N CNTEN tSD tHD Dn DATAIN Dn + 1 WRITE EXTERNAL ADDRESS Dn + 3 Dn + 2 Dn + 1 WRITE WRITE WITH COUNTER COUNTER HOLD Dn + 4 WRITE WITH COUNTER , 7144 drw 17 Timing Waveform of Counter Repeat(2,6) tCYC2 CLK tSA tHA An ADDRESS (3) INTERNAL ADDRESS An tSAD tHAD ADS tSW tHW R/W An+2 An+1 An+2 An An+1 An+2 An+2 tSCN tHCN CNTEN T O N REPEAT (4) tSRPT tHRPT tSD tHD DATAIN D0 D3 D2 D1 tCD1 An DATAOUT WRITE TO ADS ADDRESS An , ADVANCE COUNTER WRITE TO An+1 ADVANCE COUNTER WRITE TO An+2 HOLD COUNTER WRITE TO An+2 REPEAT READ LAST ADS ADDRESS An An+1 ADVANCE COUNTER READ An+1 An+2 An+2 , ADVANCE COUNTER READ An+2 HOLD COUNTER READ An+2 7144 drw 18 NOTES: 1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH. 2. CE0, BEn = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. For more information on REPEAT function refer to Truth Table II. 5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations. 6.42 19 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(2) CLKL tSW tHW tSA tHA R/WL ADDRESSL(3) 3FFFF(4) tSC CEL R O F tHC (1) tINS INTR tINR CLKR D E D S N N E IG M S M E O D C W E E R N tSC CER(1) R/WR tHC tSW tHW tSA tHA 3FFFF(4) ADDRESSR(3) 7144 drw 19 NOTES: 1. CE0 = VIL and CE1 = VIH 2. All timing is the same for Left and Right ports. 3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals. 4. For IDT70P3599, the Interrupt Address is 1FFFF. T O N Truth Table III — Interrupt Flag(1) Left Port CLKL ↑ R/WL (2) CEL (2) Right Port A17L-A0L (3,4) INTL CLKR (2) R/WR CER(2) A17R-A0R(3,4) INTR Function L L 3FFFF X ↑ X X X L Set Right INTR Flag X X X X ↑ H L 3FFFF H Reset Right INTR Flag ↑ X X X L ↑ L L 3FFFE X Set Left INTL Flag ↑ H L 3FFFE H ↑ X X X X Reset Left INTL Flag ↑ NOTES: 1. INTL and INTR must be initialized at power-up by Resetting the flags. 2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times. 3. A17X is a NC for IDT70P3599, therefore Interrupt Addresses are 1FFFF and 1FFFE. 4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals. 6.42 20 FEBRUARY 15, 2008 7144 tbl 12 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Waveform of Collision Timing(1,2) Both Ports Writing with Left Port Clock Leading CLKL tOFS tSA (4) tHA ADDRESSL A3 A2 A1 A0 tCOLR tCOLS COLL (3) tOFS CLKR tSA (4) ADDRESSR D E D S N N E IG M S M E O D C W E E R N tHA A0 A3 A2 A1 tCOLR tCOLS COLR R O F 7144 drw 20 NOTES: 1. CE0 = VIL, CE1 = VIH. 2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases. 3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match. 4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals. Collision Detection Timing(3,4) tOFS (ns) Cycle Time Region 1 (ns) 5ns 0 - 2.8 6ns 0 - 3.8 7.5ns 0 - 5.3 T O N (1) Region 2 (ns) (2) 2.81 - 4.6 3.81 - 5.6 5.31 - 7.1 NOTES: 1. Region 1 Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc. 2. Region 2 Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc. while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc. 3. All the production units are tested to midpoint of each region. 4. These ranges are based on characterization of a typical device. 7144 tbl 13 Truth Table IV — Collision Detection Flag Left Port Right Port R/WL(1) CEL(1) A17L-A0L(2) COLL CLKR R/WR(1) CER(1) A17R-A0R(2) COLR Function H L MATCH H ↑ H L MATCH H Both ports reading. Not a valid collision. No flag output on either port. ↑ H L MATCH L ↑ L L MATCH H Left port reading, Right port writing. Valid collision, flag output on Left port. ↑ L L MATCH H ↑ H L MATCH L Right port reading, Left port writing. Valid collision, flag output on Right port. ↑ L L MATCH L ↑ L L MATCH L Both ports writing. Valid collision. Flag output on both ports. CLKL ↑ NOTES: 1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times. 2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals. 6.42 21 7144 tbl 14 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform - Entering Sleep Mode(1,2) R O F R/W D E D S N N E IG M S M E O D C W E E R N (3) Timing Waveform - Exiting Sleep Mode(1,2) An An+1 (5) R/W T O N OE (5) Dn DATAOUT Dn+1 (4) NOTES: 1. CE1 = V IH. 2. All timing is same for Left and Right ports. 3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH). 4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL). 5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle. 6.42 22 FEBRUARY 15, 2008 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Functional Description The IDT70P3519/99 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse width is independent of the cycle time. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70P3519/99 for depth expansion configurations. Two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs. Interrupts Collision is defined as accessing the same memory address from both ports resulting in the potential for either reading or writing incorrect data to a specific address. For the specific cases: (a) Both ports reading - no data is corrupted, lost, or incorrectly output, so no collision flag is output on either port. (b) One port writing, the other port reading - the end result of the write will still be valid. However, the reading port might capture data that is in a state of transition and hence the reading port’s collision flag is output. (c) Both ports writing - there is a risk that the two ports will interfere with each other, and the data stored in memory will not be a valid write from either port (it may essentially be a random combination of the two). Therefore, the collision flag is output on both ports. Please refer to Truth Table IV for all of the above cases. The alert flag (COLx) is asserted on the 2nd or 3rd rising clock edge of the affected port following the collision, and remains low for one cycle. Please refer to Collision Detection Timing table on Page 21. During that next cycle, the internal arbitration is engaged in resetting the alert flag (this avoids a specific requirement on the part of the user to reset the alert flag). If two collisions occur on subsequent clock cycles, the second collision may not generate the appropriate alert flag. A third collision will generate the T O N proper alert flag. In the event that a user initiates a burst access on both ports with the same starting address on both ports and one or both ports writing during each access (i.e., imposes a long string of collisions on contiguous clock cycles), the alert flag will be asserted and cleared every other cycle. Please refer to the Collision Detection timing waveform on Page 21. Collision detection on the IDT70P3519/99 represents an advance in functionality over other sync multi-ports, which have no such capability. The IDT70P3519/99 sustains the key features of bandwidth and flexibility. The collision detection function is very useful in the case of bursting data, or a string of accesses made to sequential addresses, in that it indicates a problem within the burst, giving the user the option of either repeating the burst or continuing to watch the alert flag to see whether the number of collisions increases above an acceptable threshold value. Offering this function on chip also allows users to reduce their need for arbitration circuits, typically done in CPLD’s or FPGA’s. This reduces board space and design complexity, and gives the user more flexibility in developing a solution. R O F D E D S N N E IG M S M E O D C W E E R N If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FFFE (1FFFE for IDT70P3599), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location 3FFFE (1FFFE for IDT70P3599) when CEL = VIL and R/WL = VIH. Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFFF (1FFF for IDT70P3599) and to clear the interrupt flag (INTR), the right port must read the memory location 3FFFF (1FFFF for IDT70P3599). The message (36 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70P3599) is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70P3599) are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Collision Detetion Industrial and Commercial Temperature Ranges Sleep Mode The IDT70P3519/99 is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is asynchronous and active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode. For normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. Clocks must also meet cycle high and low times during these periods. Three cycles prior to asserting ZZ (ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device must be disabled via the chip enable pins. If a write or read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). When exiting sleep mode, the device must be in Read mode (R/Wx = VIH)when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid data. During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected and will not perform any reads or writes. 6.42 23 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Depth and Width Expansion The IDT70P3519/99 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70P3519/99 can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider. A18/A17 R O F D E D S N N E IG M S M E O D C W E E R N IDT70P3519/99 CE0 CE1 CE1 VDD CE1 IDT70P3519/99 VDD CE1 CE0 CE0 Control Inputs CE0 Control Inputs Control Inputs IDT70P3519/99 IDT70P3519/99 Control Inputs 7144 drw 23 Figure 4. Depth and Width Expansion with IDT70P3519/99 NOTE: 1. A18 is for IDT70P3519, A17 is for IDT70P3599. T O N 6.42 24 FEBRUARY 15, 2008 BE, R/W, OE, CLK, ADS, REPEAT, CNTEN , IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tJF tJCL tJCYC tJR tJCH TCK Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO tJDC tJH tJRSR tJCD TRST R O F , 7144 drw 24 tJRST Figure 5. Standard JTAG Timing D E D S N N E IG M S M E O D C W E E R N NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics (1,2,3,4) 70P3519/99 Symbol Parameter tJCYC JTAG Clock Input Period tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Min. Max. Units 100 ____ ns 40 ____ ns JTAG Clock Low 40 ____ ns JTAG Clock Rise Time ____ (1) ns (1) JTAG Clock HIGH T O N 3 JTAG Clock Fall Time ____ 3 ns JTAG Reset 50 ____ ns JTAG Reset Recovery 50 ____ ns JTAG Data Output ____ 25 ns 0 ____ ns JTAG Setup 15 ____ ns JTAG Hold 15 ____ ns JTAG Data Output Hold 7144 tbl 15 NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 6.42 25 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Value Revision Number (31:28) Description 0x0 Reserved for version number IDT Device ID (27:12) 0x380(1) IDT JEDEC ID (11:1) 0x33 ID Register Indicator Bit (Bit 0) Defines IDT part number Allows unique identification of device vendor as IDT 1 Indicates the presence of an ID register R O F NOTE: 1. Device ID for IDT70P3599 is 0x383. Scan Register Sizes Register Name Instruction (IR) D E D S N N E IG M S M E O D C W E E R N Bit Size 4 Bypass (BYR) 7144 tbl 16 1 Identification (IDR) Boundary Scan (BSR) 32 Note (3) 7144 tbl 17 System Interface Parameters Instruction EXTEST BYPASS IDCODE HIGHZ CLAMP T O N PRIVATE Description 0000 Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between TDI and TDO. 1111 Places the bypass register (BYR) between TDI and TDO. 0010 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. 0100 Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state except COLx & INTx outputs. 0011 SAMPLE/PRELOAD RESERVED Code Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. 0001 Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. 0101, 0111, 1000, 1001, 1010, 1011, 1100 Several combinations are reserved. Do not use codes other than those identified above. 0110,1110,1101 For internal use only. NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 6.42 26 FEBRUARY 15, 2008 7144 tbl 18 IDT70P3519/99 High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Type Power Speed Package A A Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green BC BF 256-pin BGA (BC-256) 208-pin fpBGA (BF-208) R O F D E D S N N E IG M S M E O D C W E E R N 200 166 Commercial Only Commercial & Industrial S Standard Power Speed in Megahertz 70P3519 9Mbit (256K x 36) 2.5V Synchronous Dual-Port RAM 70P3599 4Mbit (128K x 36) 2.5V Synchronous Dual-Port RAM 7144 drw 25 IDT Clock Solution for IDT70P3519/99 Dual-Port Dual-Port I/O Specifications IDT Dual-Port Part Number Voltage 70P3519/99 2.5 T O N Clock Specifications I/O Input Capacitance Input Duty Cycle Requirement LVTTL 3.5-6pF 40% Maximum Frequency Jitter Tolerance 200 75ps IDT PLL Clock Device IDT Non-PLL Clock Device 5T2010 5T9010 5T905, 5T9050 5T907, 5T9070 Datasheet Document History: 07/07/08: 01/19/09: 06/08/09: Initial Datasheet Page 28 Removed "IDT" from orderable part number Removed preliminary status Š CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 27 for Tech Support: 408-284-2794 DualPortHelp@idt.com 7144 tbl 19