70T653MS12BCI8

HIGH-SPEED 2.5V 512K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12ns (max.) RapidWrite Mode simplifies high-speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T653M easily expands data bus width to 72 bits or more using the Busy Input when cascading more than one device Busy input for port contention management Interrupt Flags 70T653M Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Single 2.5V (±100mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Includes JTAG functionality Available in a 256-ball Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Functional Block Diagram BE 3L BE 3R BE2L BE 2R BE 1L BE 1R BE0L BE 0R R/ WL R/W R BB EE 01 LL CE0L CE 1L BB EE 23 LL BBBB EEEE 3210 R RRR CE0R CE1R OEL OER Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R Dout18-26_L Dout18-26_R Dout27-35_L Dout27-35_R 512K x 36 MEMORY ARRAY I/O0L- I/O35L A18L A0L Di n_L Address Decoder Di n_R ADDR_L CE0L CE1L OEL R/WL I/O0R -I/O35R ARBITRATION INTERRUPT SEMAPHORE LOGIC BUSYL A18R Address Decoder ADDR_R OER CE0R CE1R A0R TDI JTAG TDO TCK TMS TRST R/WR BUSYR SEMR INTR(1) SEML INTL(1) ZZ NOTES: CONTROL ZZL(2) ZZR(2) LOGIC 1. INT is non-tri-state totem-pole outputs (push-pull). 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 5679 drw 01 JUNE 2019 1 DSC-5679/8 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT70T653M is a high-speed 512K x 36 Asynchronous DualPort Static RAM. The IDT70T653M is designed to be used as a standalone 18874K-bit Dual-Port RAM. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. The IDT70T653M has a RapidWrite Mode which allows the designer to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 10ns cycle time of the IDT70T653M, easing design considerations at these high performance levels. The 70T653M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. 2 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3) 70T653M BC256(4,5) BCG256(4,5) 256-Pin BGA Top View A1 NC B1 I/O18L C1 A2 TDI B2 NC C2 I/O18R I/O19L D1 D2 A3 NC B3 TDO C3 VSS D3 I/O20R I/O19R I/O20L E1 E2 E3 A4 B4 A 18L C4 A16L D4 V DD E4 I/O21R I/O21L I/O22L VDDQL F1 F2 F3 A5 A17L A 14L F4 B5 A15L C5 A13L D5 G2 G3 G4 I/O24R I/O24L I/O25L VDDQR H1 H2 H3 H4 E5 VDD F5 G5 V SS H5 I/O26L I/O25R I/O26R VDDQR VSS J1 J2 J3 J4 I/O27L I/O28R I/O27R VDDQL K1 K2 K3 K4 J5 ZZR K5 I/O29R I/O29L I/O28L V DDQL V SS L1 L2 L3 L4 L5 I/O30L I/O31R I/O30R VDDQR VDD M1 M2 M3 M4 I/O32R I/O32L I/O31L VDDQR N1 N2 N3 I/O33L I/O34R I/O33R P1 P2 P3 I/O35R I/O34L TMS R1 I/O35L T1 NC R2 NC T2 TCK R3 N4 VDD P4 A16R R4 TRST A18R T3 NC T4 A17R A11L B6 A12L C6 A10L D6 A7 A 8L B7 A 9L C7 A7L D7 A8 BE 2L B8 BE3L C8 BE1L D8 A9 CE1L B9 A10 OEL B10 CE0L R/WL C9 C10 A11 INTL B11 NC C11 BE0L SEML BUSYL D9 D10 D11 A12 A5L B12 A4L C12 A6L D12 A13 A2L B13 A1L C13 A3L D13 A14 A0L B14 NC C14 A15 NC B15 I/O17L C15 A16 NC B16 NC C16 OPTL I/O17R I/O16L D14 D15 D16 VDDQL VDDQL V DDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R I/O23L I/O22R I/O23R VDDQL VDD G1 A6 M5 VDD N5 E6 VDD F6 NC G6 VSS H6 V SS J6 VSS K6 VSS L6 NC M6 V DD N6 E7 VSS F7 VSS G7 VSS H7 VSS J7 VSS K7 VSS L7 VSS M7 VSS N7 E8 E9 VSS F8 V SS F9 V SS VSS G8 G9 VSS H8 V SS H9 VSS J8 VSS J9 VSS K8 V SS K9 VSS L8 V SS L9 VSS M8 V SS M9 VSS N8 V SS N9 E10 VSS F10 VSS G10 VSS H10 V SS J10 VSS K10 VSS L10 V SS M10 VSS N10 E11 VDD F11 VSS G11 VSS H11 VSS J11 VSS K11 VSS L11 VSS M11 VDD N11 E12 F12 A13R R5 A15R T5 A14R P6 A10R R6 A12R T6 A11R P7 A7R R7 A9R T7 A8R P8 P9 P10 P11 BE1R BE0R SEMR BUSYR R8 R9 R10 BE3R CE0R R/WR T8 T9 BE 2R CE1R T10 OER R11 V SS T11 INTR E14 E15 E16 F13 F14 F15 F16 VDD V DDQR I/O12R I/O13R I/O12L G12 VSS H12 VSS J12 G13 G14 G15 K12 VSS L12 VDD M12 VDD N12 P12 A6R R12 A4R T12 A 5R G16 VDDQL I/O10L I/O11L I/O11R H13 H14 VDDQL I/O9R J13 J14 H15 K13 K14 H16 IO9L I/O10R J15 ZZL V DDQR I/O8R I/O7R V DDQR VDDQR VDDQL VDDQL VDDQR V DDQR VDDQL VDDQL P5 E13 VDD V DDQR I/O13L I/O14L I/O14R K15 J16 I/O8L K16 V DDQR I/O6R I/O6L I/O7L L13 L14 V DDQL I/O5L M13 M14 L15 L16 I/O4R I/O5R M15 M16 V DDQL I/O3R I/O3L I/O4L N13 VDD P13 A3R R13 A1R T13 A2R N14 I/O2L P14 N15 P15 I/O0L I/O0R R14 OPTR T14 A 0R N16 I/O1R I/O2R R15 NC T15 NC P16 I/O1L R16 NC T16 NC 5679 drw 02f NOTES: 1. All VDD pins must be connected to 2.5V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 3 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (Input) R/WL R/WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A18L A0R - A18R Address (Input) I/O0L - I/O35L I/O0R - I/O35R Data Input/Output SEML SEMR Semaphore Enable (Input) INTL INTR Interrupt Flag (Output) BUSYL BUSYR Busy Input BE0L - BE3L BE0R - BE3R Byte Enables (9-bit bytes) (Input) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1) (Input) OPTL OPTR Option for selecting V DDQX(1,2) (Input) ZZL ZZR Sleep Mode Pin(3) (Input) VDD Power (2.5V)(1) (Input) VSS Ground (0V) (Input) TDI Test Data Input TDO Test Data Output TCK Test Logic Clock (10MHz) (Input) TMS Test Mode Select (Input) TRST Reset (Initialize TAP Controller) (Input) NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundary scan not be operated during sleep mode. 5679 tbl 01 4 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control(1,2) OE SEM CE0 CE1 BE3 BE2 BE1 BE0 R/W ZZ Byte 3 I/O27-35 Byte 2 I/O18-26 Byte 1 I/O9-17 Byte 0 I/O0-8 MODE X H H X X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down X H X L X X X X X L High-Z High-Z High-Z High-Z Deselected–Power Down X H L H H H H H X L High-Z High-Z High-Z High-Z All Bytes Deselected X H L H H H H L L L High-Z High-Z High-Z DIN Write to Byte 0 Only X H L H H H L H L L High-Z High-Z DIN High-Z Write to Byte 1 Only X H L H H L H H L L High-Z DIN High-Z High-Z Write to Byte 2 Only X H L H L H H H L L DIN High-Z High-Z High-Z Write to Byte 3 Only X H L H H H L L L L High-Z High-Z DIN DIN Write to Lower 2 Bytes Only X H L H L L H H L L DIN DIN High-Z High-Z Write to Upper 2 bytes Only X H L H L L L L L L DIN DIN DIN DIN Write to All Bytes L H L H H H H L H L High-Z High-Z High-Z DOUT Read Byte 0 Only L H L H H H L H H L High-Z High-Z DOUT High-Z Read Byte 1 Only L H L H H L H H H L High-Z DOUT High-Z High-Z Read Byte 2 Only L H L H L H H H H L DOUT High-Z High-Z High-Z Read Byte 3 Only L H L H H H L L H L High-Z High-Z DOUT DOUT Read Lower 2 Bytes Only L H L H L L H H H L DOUT DOUT High-Z High-Z Read Upper 2 Bytes Only L H L H L L L L H L DOUT DOUT DOUT DOUT H H L H L L L L X L High-Z High-Z High-Z High-Z Read All Bytes Outputs Disabled X X X X X X X X X H High-Z High-Z High-Z High-Z High-Z Sleep Mode NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. 5679 tbl 02 Truth Table II – Semaphore Read/Write Control(1) Inputs(1) Outputs CE(2) R/W OE BE3 BE2 BE1 BE0 SEM I/O1-8, I/O18-26 I/O0 H H L X L X L L DATAOUT DATAOUT H ↑ X X X X L L X DATAIN L X X X X X X L ______ ______ Mode Read Data in Semaphore Flag (3) Write I/O0 into Semaphore Flag Not Allowed 5679 tbl 03 NOTES: 1. There are eight semaphore flags written to I/O0 and read from the I/Os (I/O0-I/O08 and I/O18-I/O26). These eight semaphore flags are addressed by A0-A2. 2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL. 3. Each byte is controlled by the respective BEn. To read data BEn = VIL. 5 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Recommended DC Operating Conditions with VDDQ at 2.5V Symbol Ambient Temperature GND 0OC to +70OC Industrial VDD VDD 2.5V + 100mV 0V -40OC to +85OC 2.5V + 100mV 0V 5679 tbl 04 NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. Capacitance(1) (TA = +25°C, F = 1.0MHZ) PQFP ONLY Symbol CIN COUT(2) Parameter Input Capacitance Output Capacitance Conditions Max. Unit VIN = 0V 15 pF VOUT = 0V 10.5 pF VTERM (VDD) VDD Terminal Voltage with Respect to GND -0.5 to 3.6 V VDDQ Terminal Voltage with Respect to GND -0.3 to VDDQ + 0.3 V VTERM(2) (INPUTS and I/O's) Input and I/O Terminal Voltage with Respect to GND -0.3 to VDDQ + 0.3 V TBIAS(3) Temperature Under Bias TSTG TJN Storage Temperature Junction Temperature -65 to +150 +150 IOUT(For VDDQ = 3.3V) DC Output Current 50 IOUT(For VDDQ = 2.5V) DC Output Current 40 Max. Unit 2.5 2.6 V (3) 2.4 2.5 2.6 V 0 0 0 V 1.7 ____ VDDQ + 100mV(2) V 1.7 ____ VDD + 100mV (2) V VDD - 0.2V ____ VDD + 100mV (2) V (1) VDDQ I/O Supply Voltage VSS Ground VIH Input High Volltage (Address, Control & Data I/O Inputs)(3) VIH Input High Voltage JTAG VIH Input High Voltage ZZ, OPT _ V IL Input Low Voltage -0.3 ____ 0.7 V V IL Input Low Voltage ZZ, OPT -0.3(1) ____ 0.2 V Symbol Unit VTERM(2) (VDDQ) -55 to +125 Typ. 2.4 Recommended DC Operating Conditions with VDDQ at 3.3V Absolute Maximum Ratings(1) Commercial & Industrial Parameter 5679 tbl 05 5679 tbl 08 Rating Min. Core Supply Voltage NOTES: 1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less. 2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is less. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VSS(0V), and VDDQX for that port must be supplied as indicated above. NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. COUT also references CI/O. Symbol Industrial and Commercial Temperature Ranges o o o C C C Min. Typ. Max. Unit VDD Core Supply Voltage Parameter 2.4 2.5 2.6 V VDDQ I/O Supply Voltage (3) 3.15 3.3 3.45 V VSS Ground 0 0 0 V VIH Input High Voltage (Address, Control &Data I/O Inputs)(3) 2.0 ____ VDDQ + 150mV(2) V VIH Input High Voltage JTAG 1.7 ____ VDD + 100mV(2) V VIH Input High Voltage ZZ, OPT VDD - 0.2V ____ VDD + 100mV(2) V (1) ____ 0.8 V (1) ____ 0.2 V VIL Input Low Voltage VIL Input Low Voltage ZZ, OPT _ -0.3 -0.3 5679 tbl 06 NOTES: 1. VIL (min.) = -1.0V for pulse width less than tRC/2 or 5ns, whichever is less. 2. VIH (max.) = VDDQ + 1.0V for pulse width less than tRC/2 or 5ns, whichever is less. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated above. mA mA 5679 tbl 07 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed VDDQ during power supply ramp up. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected. 6 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV) 70T653M Symbol Parameter Test Conditions (1) Min. Max. Unit |ILI| Input Leakage Current VDDQ = Max., VIN = 0V to VDDQ ___ 10 µA |ILI| JTAG & ZZ Input Leakage Current(1,2) VDD = Max. , VIN = 0V to VDD ___ +60 µA CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ ___ 10 µA IOL = +4mA, VDDQ = Min. ___ 0.4 V IOH = -4mA, VDDQ = Min. 2.4 ___ V IOL = +2mA, VDDQ = Min. ___ 0.4 V IOH = -2mA, VDDQ = Min. 2.0 ___ (1,3) |ILO| Output Leakage Current (1) VOL (3.3V) Output Low Voltage VOH (3.3V) Output High Voltage (1) (1) VOL (2.5V) Output Low Voltage VOH (2.5V) Output High Voltage (1) V 5679 tbl 09 NOTES: 1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details. 2. Applicable only for TMS, TDI and TRST inputs. 3. Outputs tested in tri-state mode. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV) 70T653MS10 Com'l Only Symbol IDD (6) ISB1 ISB2(6) ISB3 ISB4(6) IZZ Parameter Test Condition Version 70T653MS12 Com'l & Ind 70T653MS15 Com'l Only Typ.(4) Max. Typ.(4) Max. Typ. (4) Max. Unit Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled f = fMAX(1) COM'L S 600 810 600 710 450 600 mA IND S ____ ____ 600 790 ____ ____ Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH f = fMAX(1) COM'L S 180 240 150 210 120 170 IND S ____ ____ 150 260 ____ ____ Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f = fMAX(1) COM'L S 400 530 360 460 300 400 IND S ____ ____ 360 510 ____ ____ Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V or VIN < 0.2V, f = 0(2) COM'L S 4 20 4 20 4 20 IND S ____ ____ 4 40 ____ ____ Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5) VIN > VDDQ - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L S 400 530 460 300 400 IND S ____ ____ 360 510 ____ ____ COM'L S 4 20 4 20 4 20 IND S ____ ____ 4 40 ____ ____ Sleep Mode Current (Both Ports - TTL Level Inputs) ZZL = ZZR = VIH f = fMAX(1) mA mA mA mA mA 5679 tbl 10 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input levels of GND to 3.3V. 2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 200mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V CEX > VDDQX - 0.2V means CE0X > VDDQX - 0.2V or CE1X < 0.2V. "X" represents "L" for left port or "R" for right port. 6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and /or ZZR = VIH. 7 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ - 3.3V/2.5V) GND to 3.0V / GND to 2.4V Input Pulse Levels 2ns Max. Input Rise/Fall Times Input Timing Reference Levels 1.5V/1.25V Output Reference Levels 1.5V/1.25V Figure 1 Output Load 5679 tbl 11 50Ω 50Ω DATAOUT 1.5V/1.25 10pF (Tester) 5679 drw 03 Figure 1. AC Output Test load. 4 3.5 3 Δ tAA/tACE (Typical, ns) 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 120 Δ Capacitance (pF) from AC Test Load 140 5679 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 8 160 , 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 70T653MS10 Com'l Only Symbol Parameter Min. Max. 70T653MS12 Com'l & Ind Min. Max. 70T653MS15 Com'l Only Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns tACE Chip Enable Access Time (3) ____ 10 ____ 12 ____ 15 ns tABE Byte Enable Access Time (3) ____ 5 ____ 6 ____ 7 ns tAOE Output Enable Access Time ____ 5 ____ 6 ____ 7 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time Chip Enable and Semaphore (1,2) 3 ____ 3 ____ 3 ____ ns 0 ____ 0 ____ 0 ____ ns 0 4 0 6 0 8 ns 0 ____ 0 ____ 0 ____ ns ____ 8 ____ 8 ____ 12 ns ____ 4 ____ 6 ____ 8 ns 2 10 2 12 2 15 ns ____ 5 ____ 6 ____ 7 tLZOB Output Low-Z Time Output Enable and Byte Enable (1,2) (1,2) tHZ Output High-Z Time tPU Chip Enable to Power Up Time (2) (2) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) tSAA Semaphore Address Access Time tSOE Semaphore Output Enable Access Time ns 5679 tbl 12 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(4) 70T653MS10 Com'l Only Symbol Parameter 70T653MS12 Com'l & Ind 70T653MS15 Com'l Only Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 10 ____ 12 ____ 15 ____ ns tEW Chip Enable to End-of-Write (3) 7 ____ 9 ____ 12 ____ ns tAW Address Valid to End-of-Write 7 ____ 9 ____ 12 ____ ns tAS Address Set-up Time (3) 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 7 ____ 9 ____ 12 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 5 ____ 7 ____ 10 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns ____ (1,2) tWZ Write Enable to Output in High-Z 4 ____ 6 ____ 8 ns tOW Output Active from End-of-Write (1,2) 3 ____ 3 ____ 3 ____ ns SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns SEM Flag Contention Window 5 ____ 5 ____ 5 ____ tSWRD tSPS ns 5679 tbl 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL. 4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details. 9 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Read Cycles(4) tRC ADDR (3) tAA (3) tACE (5) CE tAOE (3) OE tABE (3) BEn R/W tOH (1) tLZ/tLZOB DATAOUT VALID DATA (3) tHZ (2) . 5679 drw 06 NOTES: 1. Timing depends on which signal is asserted last, OE, CE or BEn. 2. Timing depends on which signal is de-asserted first CE, OE or BEn. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tABE. 4. SEM = VIH. 5. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL. Timing of Power-Up Power-Down CE tPU tPD ICC 50% 50% ISB . 5679 drw 07 10 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE CE or SEM tAW (9) tHZ (7) (9) BEn tAS (6) tWR(3) tWP (2) R/W (7) tLZ DATAOUT tWZ (7) tOW (4) (4) tDW tDH , DATA IN 5679 drw 10 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8) tWC ADDRESS tAW CE or SEM (9) (6) tAS tWR(3) tEW (2) BEn(9) R/W tDW tDH DATAIN . 5679 drw 11 . NOTES: 1. R/W or CE or BEn = VIH during all address transitions for Write Cycles 1 and 2. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE, BEn or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 1). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL. 11 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM RapidWrite Mode Write Cycle Industrial and Commercial Temperature Ranges Address inputs must be stable. Input data setup and hold times (tDW and tDH) will now be referenced to the ending address transition. In this RapidWrite Mode the I/O will remain in the Input mode for the duration of the operations due to R/W being held low. All standard Write Cycle specifications must be adhered to. However, tAS and tWR are only applicable when switching between read and write operations. Also, there are two additional conditions on the Address Inputs that must also be met to ensure correct address controlled writes. These specifications, the Allowable Address Skew (tAAS) and the Address Rise/Fall time (tARF), must be met to use the RapidWrite Mode. If these conditions are not met there is the potential for inadvertent write operations at random intermediate locations as the device transitions between the desired write addresses. Unlike other vendors' Asynchronous Random Access Memories, the IDT70T653M is capable of performing multiple back-to-back write operations without having to pulse the R/W, CE, or BEn signals high during address transitions. This RapidWrite Mode functionality allows the system designer to achieve optimum back-to-back write cycle performance without the difficult task of generating narrow reset pulses every cycle, simplifying system design and reducing time to market. During this new RapidWrite Mode, the end of the write cycle is now defined by the ending address transition, instead of the R/W or CE or BEn transition to the inactive state. R/W, CE, and BEn can be held active throughout the address transition between write cycles. Care must be taken to still meet the Write Cycle time (tWC), the time in which the Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3) (4) tWC tWC tWC ADDRESS (2) CE or SEM (6) tEW BEn tWR tWP R/W (5) (5) tWZ tOW DATAOUT tDH tDH tDW tDW tDH tDW DATAIN 5679 drw 08 NOTES: 1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence. 3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes. 5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 1). 6. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = VIL when CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL. 12 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics over the Operating Temperature Range and Supply Voltage Range for RapidWrite Mode Write Cycle(1) Symbol Parameter Min tAAS Allowable Address Skew for RapidWrite Mode ____ tARF Address Rise/Fall Time for RapidWrite Mode 1.5 Max Unit 1 ns ____ V/ns 5679 tbl 14 NOTE: 1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle. Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle A0 tARF tAAS A18 tARF 5679 drw 09 13 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW VALID ADDRESS tWR tACE tEW SEM(1) tOH tSOP tDW I/O DATAOUT(2) VALID DATA IN VALID tAS tWP tDH R/W tSWRD OE tSOE tSOP Write Cycle Read Cycle 5679 drw 12 . NOTES: 1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for appropriate BEn controls. 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8 and I/O18 - I/O26) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 5679 drw 13 . NOTES: 1. DOR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag. 14 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70T653MS10 Com'l Only Symbol Parameter 70T653MS12 Com'l & Ind 70T653MS15 Com'l Only Min. Max. Min. Max. Min. Max. Unit BUSY TIMING tWB BUSY Input to Write (4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 7 ____ 9 ____ 12 ____ ns ____ 14 ____ 16 ____ 20 ns ____ 14 ____ 16 ____ 20 PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ns 5679 tbl 15 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read. 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2,3) 70T65M3S10 Com'l Only Symbol Parameter 70T653MS12 Com'l & Ind 70T6539MS15 Com'l Only Min. Max. Min. Max. Min. Max. SLEEP MODE TIMING (ZZx=V IH) tZZS Sleep Mode Set Time 10 ____ 12 ____ 15 ____ tZZR Sleep Mode Reset Time 10 ____ 12 ____ 15 ____ tZZPD Sleep Mode Power Down Time (4) 10 ____ 12 ____ 15 ____ tZZPU Sleep Mode Power Up Time (4) ____ 0 ____ 0 ____ 0 5679 tbl 15a NOTES: 1. Timing is the same for both ports. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundary scan not be operated during sleep mode. 3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details. 4. This parameter is guaranteed by device characterization, but is not production tested. 15 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read(1,3) tWC MATCH ADDR"A" tWP R/W"A" tDH tDW VALID DATAIN "A" MATCH ADDR"B" (4) R/W"B" tWDD DATAOUT "B" VALID tDDD(3) NOTES: 1. CE0L = CE0R = VIL; CE1L = CE1R = VIH. 2. OE = VIL for the reading port. 3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 4. R/WB = VIH. . 5679 drw 14a Timing Waveform of Write with BUSY tWP R/W"A" tWB BUSY"B" tWH R/W"B" (1) (2) NOTES: 1. tWH must be met for BUSY input. 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 5679 drw 15 . AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2) 70T653MS10 Com'l Only Symbol Parameter 70T653MS12 Com'l & Ind 70T653MS15 Com'l Only Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 10 ____ 12 ____ 15 ns tINR Interrupt Reset Time ____ 10 ____ 12 ____ 15 ns NOTES: 1. Timing is the same for both ports. 2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details. 16 5679 tbl 16 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC (2) ADDR"A" INTERRUPT SET ADDRESS tWR (5) tAS(4) CE"A"(3) R/W"A" tINS (4) INT"B" 5679 drw 18 . tRC ADDR"B" INTERRUPT CLEAR ADDRESS tAS (2) (4) CE"B"(3) OE"B" tINR (4) INT"B" 5679 drw 19 . NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. Refer to Interrupt Truth Table. 3. CEX = VIL means CE0X = VIL and CE1X = VIH. CEX = VIH means CE0X = VIH and/or CE1X = VIL. 4. Timing depends on which enable signal (CE or R/W) is asserted last. 5. Timing depends on which enable signal (CE or R/W) is de-asserted first. Truth Table III — Interrupt Flag(1,4) Left Port R/WL L CEL L OEL X Right Port A18L-A0L 7FFFF INTL X R/WR X CER X OER X A18R-A0R X INTR Function (2) Set Right INTR Flag (3) L X X X X X X L L 7FFFF H Reset Right INTR Flag X X X X L(3) L L X 7FFFE X Set Left INTL Flag X L L 7FFFE H(2) X X X X X Reset Left INTL Flag 5679 tbl 17 NOTES: 1. Assumes BUSYL = BUSYR =VIH. CE0X = VIL and CE1X = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTL and INTR must be initialized at power-up. 17 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table IV — Example of Semaphore Procurement Sequence(1,2,3) D0 - D8 Left D18 - D26 Left D0 - D8 Right D18 - D26 Right No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Functions Status NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T653M. 2. There are eight semaphore flags written to via I/O0 and read from I/Os (I/O0-I/O8 and I/O18-I/O26). These eight semaphores are addressed by A0 - A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Functional Description 5679 tbl 19 semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, with both ports being completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE0 and CE1, the DualPort RAM chip enables, and SEM, the semaphore enable. The CE0, CE1, and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. Systems which can best use the IDT70T653M contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70T653Ms hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70T653M does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. The IDT70T653M provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70T653M has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location 7FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 7FFFF. The message (36 bits) at 7FFFE or 7FFFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FFFE and 7FFFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. Busy Logic The BUSY pin operates as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. Semaphores The IDT70T653M is an extremely fast Dual-Port 512K x 36 CMOS Static RAM with an additional 8 address locations dedicated to binary 18 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70T653M in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE0, CE1,R/W and BEn) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table IV). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE signals need to be active. (Please refer to Truth Table II). Furthermore, the read value is latched into one side’s output register when that side's semaphore select (SEM, BEn) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the 19 Industrial and Commercial Temperature Ranges subsequent read (see Table IV). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q SEMAPHORE REQUEST FLIP FLOP Q SEMAPHORE READ D D0 WRITE SEMAPHORE READ 5679 drw 21 Figure 4. IDT70T653M Semaphore Logic of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. If the opposite side semaphore request latch has been written to zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first request latch. The opposite side flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. 20 NOTES: 1. CE1 = V IH. 2. All timing is same for Left and Right ports. IDD DATA ADDRESS ZZ CE0 VALIDDATA VALIDADDRESS Normal Operation tZZS tZZPD Nonewreadsor writesallowed Timing Waveform of Sleep Mode(1,2) IZZ SleepMode tZZPU tZZR Noreadsor writesallowed , 5679drw22 Normal Operation 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Sleep Mode The IDT70T653M is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode. For a period of time prior to sleep mode and after recovering from sleep mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read JTAG Functionality and Configuration Industrial and Commercial Temperature Ranges operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal buffer. All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected and will not perform any reads or writes. Register Sizes, and System Interface Parameter tables. Specifically, commands for Array B must precede those for Array A in any JTAG operations sent to the IDT70T653M. Please reference Application Note AN-411, "JTAG Testing of Multichip Modules" for specific instructions on performing JTAG testing on the IDT70T653M. AN-411 is available at www.idt.com. The IDT70T653M is composed of two independent memory arrays, and thus cannot be treated as a single JTAG device in the scan chain. The two arrays (A and B) each have identical characteristics and commands but must be treated as separate entities in JTAG operations. Please refer to Figure 5. JTAG signaling must be provided serially to each array and utilizes the information provided in the Identification Register Definitions, Scan IDT70T653M TDI Array A TDOA TDIB Array B TDO TCK TMS TRST 5679 drw 23 Figure 5. JTAG Configuration for IDT70T653M 21 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tJF tJCL tJCYC tJR tJCH TCK Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO tJDC tJH tJRSR tJCD TRST x 5679 drw 24 tJRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, TCK and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics(1,2,3,4,5) 70T653M Symbol Parameter Min. Max. Units tJCYC JTAG Clock Input Period 100 ____ ns tJCH JTAG Clock HIGH 40 ____ ns tJCL JTAG Clock Low 40 ____ ns tJR JTAG Clock Rise Time ____ 3(1) ns tJF JTAG Clock Fall Time ____ (1) 3 ns tJRST JTAG Reset 50 ____ ns tJRSR JTAG Reset Recovery 50 ____ ns tJCD JTAG Data Output ____ 25 ns tJDC JTAG Data Output Hold 0 ____ ns tJS JTAG Setup 15 ____ ns tJH JTAG Hold 15 ____ ns NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 5. JTAG cannot be tested in sleep mode. 5679 tbl 20 22 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Array B Value Array B Revision Number (31:28) 0x0 Instruction Field Array A Value Description Array A Revision Number (63:60) 0x0 Reserved for Version number IDT Device ID (27:12) 0x33B IDT Device ID (59:44) 0x33B Defines IDT Part number IDT JEDEC ID (11:1) 0x33 IDT JEDEC ID (43:33) 0x33 Allows unique identification of device vendor as IDT ID Register Indicator Bit (Bit 0) 1 ID Register Indicator Bit (Bit 32) 1 Indicates the presence of an ID Register 5679 tbl 21 Scan Register Sizes Bit Size Array A Bit Size Array B Bit Size 70T653M Instruction (IR) 4 4 8 Bypass (BYR) 1 1 2 32 32 64 Note (3) Note (3) Note (3) Register Name Identification (IDR) Boundary Scan (BSR) 5679 tbl 22 System Interface Parameters Instruction Code Description EXTEST 00000000 Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between TDI and TDO. BYPASS 11111111 Places the bypass register (BYR) between TDI and TDO. IDCODE 00100010 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. 01000100 Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. HIGHZ CLAMP 00110011 SAMPLE/PRELOAD 00010001 RESERVED Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. Several combinations are reserved. Do not use codes other than those identified above. All Other Codes NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, TCK and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 23 5679 tbl 23 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tray Tape and Reel Blank I(1) Commercial (0 C to +70 C) Industrial (-40 C to +85 C) G(2) Green BC 256-ball BGA (BC256, BCG256) 10 12 15 Commercial Only Commercial & Industrial Commercial Only S Standard Power 70T653M 18Mbit (512K x 36) Asynchronous Dual-Port RAM Speed in nanoseconds 5679 drw 25 NOTES: 1. Contact your local sales office for additional industrial temp range speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are Obsolete excluding BGA. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 10 12 Pkg. Code Pkg. Type Temp. Grade 70T653MS10BC BC256 CABGA C 70T653MS10BC8 BC256 CABGA C 70T653MS10BCG BCG256 CABGA C 70T653MS12BC BC256 CABGA C 70T653MS12BC8 BC256 CABGA C 70T653MS12BCGI BCG256 CABGA I BC256 CABGA I Orderable Part ID 70T653MS12BCI 15 70T653MS12BCI8 BC256 CABGA I 70T653MS15BC BC256 CABGA C 70T653MS15BC8 BC256 CABGA C 24 70T653M High-Speed 2.5V 512K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History: 10/08/03: 10/20/03: 09/28/04: 06/30/05: 07/25/08: 01/19/09: 06/15/15: 12/08/17: 06/27/19: Initial Datasheet Page 1 Added "Includes JTAG functionality" to features Page 13 Corrected tARF to 1.5V/ns Min Removed "Preliminary" status Page 11 Updated Timing Waveform of Write Cycle No. 1, R/W Controlled Timing Page 21 Added JTAG Configuration and JTAG Functionality descriptions Page 1 & 24 Replaced old ® logo with the new TM logo Page 1 Added green availability to features Page 24 Added green indicator to ordering information Page 7 Corrected a typo in the DC Chars table Page 24 Removed "IDT" from orderable part number Page 3 Removed the date from the BC256 pin configuration Page 24 Added Tape and Reel indicators and added footnote annotations to the Ordering Information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 3 & 24 Updated BC-256 to BC256 and BCG256 Page 24 Added Orderable Part Information table CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 25 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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