70V05S/L
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V05L
Active: 380mW (typ.)
Standby: 660μW (typ.)
IDT70V05 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆
◆
◆
◆
◆
◆
◆
◆
◆
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PLCC and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
,
I/O0L- I/O7L
I/O
Control
I/O0R-I/O7R
I/O
Control
(1,2)
(1,2)
BUSYL
A12L
A0L
BUSYR
Address
Decoder
MEMORY
ARRAY
13
CEL
OEL
R/WL
SEML
(2)
INTL
Address
Decoder
A12R
A0R
13
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/WR
SEMR
INTR(2)
2942 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
JUNE 2019
1
DSC 2941/12
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT70V05 is designed to be used as a stand-alone 64K-bit Dual-Port
SRAM or as a combination MASTER/SLAVE Dual-Port SRAM for 16-bitor-more word systems. Using the IDT MASTER/SLAVE Dual-Port SRAM
approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices typically operate on only 400mW of power.
The IDT70V05 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
I/O6R
I/O5R
I/O4R
I/O3R
VDD
I/O2R
I/O1R
I/O0R
VSS
VDD
I/O7L
I/O6L
VSS
I/O5L
I/O4L
I/O3L
I/O2L
Pin Configurations(1,2,3)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
27
8
28
7
29
6
30
5
31
3
2
1
68
68-Pin PLCC
Top View
67
66
65
38
39
40
64
63
41
42
62
61
43
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
A4L
A3L
A2L
A1L
2941 drw 02
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
49
31
50
30
51
29
52
28
53
27
54
55
26
70V05
25
56
(4)
PNG64
57
24
58
23
64-Pin TQFP
22
59
Top View
21
60
61
20
19
62
18
63
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A5L
A6L
A7L
A8L
A9L
A10L
A11L
A12L
VDD
N/C
CEL
SEML
R/WL
OEL
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
VSS
I/O6L
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
A3R
A4R
70V05
PLG68(4)
BUSYL
VSS
M/S
BUSYR
INTR
A0R
A1R
A2R
36
37
4
6.42
2
I/O7L
VDD
VSS
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
35
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
N/C
N/C
VDD
A12L
A11L
A10L
A9L
A8L
A7L
A6L
A0L
INTL
32
33
34
A4R
A3R
A2R
A1R
A0R
INTR
BUSYR
M/S
VSS
BUSYL
INTL
A0L
A1L
A2L
A3L
A4L
A5L
I/O7R
N/C
OER
R/WR
SEMR
CER
N/C
N/C
VSS
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
A5R
A6R
A7R
A8R
A9R
A10R
A11R
A12R
GND
N/C
CER
SEMR
R/WR
OER
I/O7R
I/O6R
2941 drw 03
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Pin Configurations
12/03/01
Industrial and Commercial Temperature Ranges
(1,2,3)
(con't.)
51
50
A4L
48
A2L
46
44
42
40
38
A0L BUSYL M/S INTR A1R
36
A3R
49
A3L
47
A1L
45
43
INTL VSS
35
A4R
34
A5R
11
A5L
53
A7L
52
10
55
A9L
54
09
A8L
32
A7R
33
A6R
08
57
56
A11L A10L
30
A9R
31
A8R
07
59
VDD
28
29
A11R A10R
A6L
41
39
37
BUSYR A0R A2R
58
IDT70V05G
G68-1(4)
A12L
61
60
06 N/C
N/C
68-Pin PGA
Top View(5)
26
VSS
27
A12R
24
N/C
25
N/C
05
63
62
SEML CEL
04
65
64
OEL R/WL
22
23
SEMR CER
03
67
66
I/O0L N/C
20
21
OER R/WR
02
1
3
68
I/O1L I/O2L I/O4L
2
4
I/O3L I/O5L
01
A
B
5
VSS
7
9
I/O7L VSS
6
8
I/O6L
VDD
D
E
C
11
I/O1R
13
15
VDD I/O4R
10
12
14
16
I/O0R I/O2R I/O3R I/O5R
F
G
H
18
19
I/O7R
N/C
17
I/O6R
J
K
L
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking.
2941 drw 04
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enab le
R/WL
R/WR
Re ad /Write Enab le
OEL
OER
Outp ut Enab le
A0L - A12L
A0R - A12R
Ad d re ss
I/O0L - I/O7L
I/O0R - I/O7R
Data Inp ut/Outp ut
SEML
SEMR
Se map ho re Enab le
INTL
INTR
Inte rrup t Flag
BUSYL
BUSYR
Busy Flag
M/ S
Maste r o r Slave Se le ct
VDD
Po we r (3.3v)
VSS
Gro und (0v)
2941 tb l 00
6.42
3
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
CE
R/W
OE
SEM
I/O0-7
Mode
H
X
X
H
Hig h-Z
De se le cte d : Po we r-Do wn
L
L
X
H
DATAIN
Write to Me mo ry
L
H
L
H
DATAOUT
X
X
H
X
Hig h-Z
Re ad Me mo ry
Outp uts Disab le d
2941 tb l 02
NOTE:
1. A0L — A12L≠ A0R — A12R
Truth Table II: Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE
R/W
OE
SEM
I/O0-7
Mode
H
H
L
L
DATAOUT
Re ad Data in Se map ho re Flag
H
↑
X
L
DATAIN
Write I/O0 into Se map ho re Flag
L
X
X
L
____
No t Allo we d
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 -I/O7. These eight semaphores are addressed by A0-A2.
6.42
4
2941 tb l 03
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Maximum Operating Temperature
and Supply Voltage(1)
Absolute Maximum Ratings
(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
VTERM(2)
Te rminal Vo ltag e
with Re sp e ct
to GND
-0.5 to +4.6
V
TBIAS
Te mp e rature
Und e r Bias
-55 to +125
o
TSTG
Sto rag e
Te mp e rature
-65 to +150
IOUT
DC Outp ut
Curre nt
0OC to +70OC
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
o
50
C
2941 tb l 05
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
C
mA
Parameter(1)
Inp ut Cap acitance
Outp ut Cap acitance
Recommended DC Operating
Conditions
Symbol
Conditions
Max.
Unit
VIN = 3d V
9
pF
VOUT = 3d V
10
Parameter
VDD
Sup p ly Vo ltag e
VSS
Gro und
VIH
Inp ut Hig h Vo ltag e
VIL
Capacitance (TA = +25°C, f = 1.0MHz)
COUT
VDD
Ind ustrial
2941 tb l 04
CIN
GND
Co mme rcial
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 0.3V.
Symbol
Ambient Temperature
M i n.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
2.0
____
(1)
Inp ut Lo w Vo ltag e
-0.5
V
(2)
VDD+0.3
0.8
____
V
V
2941 tb l 06
NOTES:
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD +0.3V.
pF
2941 tb l 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitznce when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V05S
Symbol
Parameter
(1)
Test Conditions
70V05L
Min.
Max.
Min.
Max.
Unit
10
___
5
μA
|ILI|
Inp ut Le akag e Curre nt
VDD = 3.6V, VIN = 0V to VDD
___
|ILO|
Outp ut Le akag e Curre nt
VOUT = 0V to VDD
___
10
___
5
μA
VOL
Outp ut Lo w Vo ltag e
IOL = +4mA
___
0.4
___
0.4
V
VOH
Outp ut Hig h Vo ltag e
IOH = -4mA
2.4
___
2.4
___
V
2941 tb l 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
6.42
5
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
70V05X15
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Op e rating
Curre nt
(Bo th Po rts Active )
Stand b y Curre nt
(Bo th Po rts - TTL
Le ve l Inp uts)
Stand b y Curre nt
(One Po rt - TTL
Le ve l Inp uts)
Full Stand b y Curre nt
(Bo th Po rts CMOS Le ve l Inp uts)
Full Stand b y Curre nt
(One Po rt CMOS Le ve l Inp uts)
Test Condition
Version
70V05X20
Com'l
& I nd
70V05X25
Com'l Only
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
COM' L
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
IND
S
L
____
____
225
195
____
____
140
130
____
____
____
____
mA
COM' L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
IND
S
L
____
____
45
40
____
____
20
15
____
____
____
____
mA
COM' L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
mA
IND
S
L
____
____
130
115
____
____
80
75
____
____
____
____
mA
Bo th Po rts CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V o r
VIN < 0.2V, f = 0(4)
SEMR = SEML > VDD - 0.2V
COM' L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
IND
S
L
____
____
15
5
____
____
1.0
0.2
____
____
____
____
mA
One Po rt CEL o r
CER > VDD - 0.2V
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V o r VIN < 0.2V
Active Po rt Outp uts Disab le d ,
f = fMAX(3)
COM' L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
IND
S
L
____
____
____
____
80
75
130
115
____
____
____
____
CE = VIL, Outp uts Disab le d
SEM = VIH
f = fMAX(3)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CEL o r CER = VIH
Active Po rt Outp uts Disab le d ,
f=fMAX(3)
mA
mA
2941 tb l 09a
70V05X35
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70V05X55
Com'l Only
Typ.(2)
Max.
Typ.(2)
Max.
Unit
Dynamic Op e rating
Curre nt
(Bo th Po rts Active )
CE = VIL, Outp uts Disab le d
SEM = VIH
f = fMAX(3)
COM' L
S
L
120
115
180
155
120
115
180
155
mA
IND
S
L
120
115
200
170
120
115
200
170
mA
Stand b y Curre nt
(Bo th Po rts - TTL
Le ve l Inp uts)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM' L
S
L
13
11
25
20
13
11
25
20
mA
IND
S
L
13
11
40
35
13
11
40
35
mA
Stand b y Curre nt
(One Po rt - TTL
Le ve l Inp uts)
CEL o r CER = VIH
Active Po rt Outp uts Disab le d ,
f=fMAX(3)
COM' L
S
L
70
65
100
90
70
65
100
90
mA
IND
S
L
70
65
120
105
70
65
120
105
mA
Full Stand b y Curre nt
(Bo th Po rts CMOS Le ve l Inp uts)
Bo th Po rts CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V o r
VIN < 0.2V, f = 0(4)
SEMR = SEML > VDD - 0.2V
COM' L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
IND
S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
Full Stand b y Curre nt
(One Po rt CMOS Le ve l Inp uts)
One Po rt CEL o r
CER > VDD - 0.2V
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V o r VIN < 0.2V
Active Po rt Outp uts Disab le d ,
f = fMAX(3)
COM' L
S
L
65
60
100
85
65
60
100
85
mA
IND
S
L
65
60
115
100
65
60
115
100
mA
2941 tb l 09b
NOTES:
1. “X” in part number indicates power rating (S or L)
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 115mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
6.42
6
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
3.3V
3.3V
GND to 3.0V
Inp ut Pulse Le ve ls
Inp ut Rise /Fall Time s
Inp ut Timing Re fe re nce Le ve ls
1.5V
Outp ut Re fe re nce Le ve ls
1.5V
Outp ut Lo ad
590Ω
590Ω
3ns Max.
DATAOUT
BUSY
INT
DATAOUT
435Ω
30pF
435Ω
5pF*
Fig ure s 1 and 2
2941 tb l 10
2941 drw 05
Figure 1. AC Output Test Load
Timing of Power-Up Power-Down
CE
ICC
tPU
tPD
50%
50%
ISB
2941 drw 06
6.42
7
Figure 2. Output Test Load
*Including scope and jig.
(For tLZ, tHZ, tWZ, tOW)
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V05X15
Com'l Only
Symbol
Parameter
70V05X20
Com'l
& Ind
70V05X25
Com'l Only
M i n.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Re ad Cycle Time
15
____
20
____
25
____
ns
tAA
Ad d re ss Acce ss Time
____
15
____
20
____
25
ns
tACE
Chip Enab le Acce ss Time (3)
____
15
____
20
____
25
ns
tAOE
Outp ut Enab le Acce ss Time (3)
____
10
____
12
____
13
ns
tOH
Outp ut Ho ld fro m Ad d re ss Chang e
3
____
3
____
3
____
ns
tLZ
Outp ut Lo w-Z Time (1,2)
3
____
3
____
3
____
ns
tHZ
Outp ut Hig h-Z Time (1,2)
____
10
____
12
____
15
ns
tPU
Chip Enab le to Po we r Up Time (1,2)
0
____
0
____
0
____
ns
tPD
Chip Disab le to Po we r Do wn Time (1,2)
____
15
____
20
____
25
ns
tSOP
Se map ho re Flag Up d ate Pulse (OE o r SEM)
10
____
10
____
10
____
ns
tSAA
Se map ho re Ad d re ss Acce ss(3)
____
15
____
20
____
25
ns
2941 tb l 11a
70V05X35
Com'l Only
Symbol
Parameter
70V05X55
Com'l Only
M i n.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Re ad Cycle Time
35
____
55
____
ns
tAA
Ad d re ss Acce ss Time
____
35
____
55
ns
____
35
____
55
ns
____
20
____
30
ns
3
____
3
____
ns
3
____
3
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
35
____
50
ns
(3)
tACE
Chip Enab le Acce ss Time
tAOE
Outp ut Enab le Acce ss Time (3)
tOH
Outp ut Ho ld fro m Ad d re ss Chang e
(1,2)
tLZ
Outp ut Lo w-Z Time
tHZ
Outp ut Hig h-Z Time (1,2)
tPU
Chip Enab le to Po we r Up Time (1,2)
(1,2)
tPD
Chip Disab le to Po we r Do wn Time
tSOP
Se map ho re Flag Up d ate Pulse (OE o r SEM)
15
____
15
____
ns
tSAA
Se map ho re Ad d re ss Acce ss(3)
____
35
____
55
ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
6.42
8
2941 tb l 11b
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles
(5)
tRC
ADDR
(4)
CE
tAA
(4)
tACE
tAOE
(4)
OE
R/W
tLZ
DATAOUT
tOH
(1)
VALID DATA
(4)
tHZ
(2)
BUSYOUT
(3,4)
tBDD
2941 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V05X20
Com'l
& Ind
70V05X15
Com'l Only
Symbol
Parameter
70V05X25
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
15
____
20
____
25
____
ns
tEW
Chip Enab le to End -o f-Write
(3)
12
____
15
____
20
____
ns
tAW
Ad d re ss Valid to End -o f-Write
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
tWC
Write Cycle Time
(3)
tAS
Ad d re ss Se t-up Time
tWP
Write Pulse Wid th
12
____
15
____
20
____
ns
tWR
Write Re co ve ry Time
0
____
0
____
0
____
ns
tDW
Data Valid to End -o f-Write
10
____
15
____
15
____
ns
____
10
____
12
____
15
ns
tHZ
Outp ut Hig h-Z Time
tDH
Data Ho ld Time
tWZ
(1,2)
(4)
0
____
0
____
0
____
ns
(1,2)
____
10
____
12
____
15
ns
(1,2,4)
0
____
0
____
0
____
ns
Write Enab le to Outp ut in Hig h-Z
tOW
Outp ut Active fro m End -o f-Write
tSWRD
SEM Flag Write to Re ad Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Co nte ntio n Wind o w
5
____
5
____
5
____
ns
2941 tb l 12a
70V05X35
Com'l Only
Symbol
Parameter
70V05X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
35
____
55
____
ns
tEW
Chip Enab le to End -o f-Write
(3)
30
____
45
____
ns
tAW
Ad d re ss Valid to End -o f-Write
30
____
45
____
ns
tAS
Ad d re ss Se t-up Time (3)
0
____
0
____
ns
tWP
Write Pulse Wid th
25
____
40
____
ns
tWR
Write Re co ve ry Time
0
____
0
____
ns
tDW
Data Valid to End -o f-Write
15
____
30
____
ns
____
15
____
25
ns
0
____
ns
25
ns
WRITE CYCLE
tWC
tHZ
tDH
tWZ
Write Cycle Time
Outp ut Hig h-Z Time
Data Ho ld Time
(1,2)
(4)
0
____
(1,2)
____
15
____
(1,2,4)
0
____
0
____
ns
ns
Write Enab le to Outp ut in Hig h-Z
tOW
Outp ut Active fro m End -o f-Write
tSWRD
SEM Flag Write to Re ad Time
5
____
5
____
tSPS
SEM Flag Co nte ntio n Wind o w
5
____
5
____
ns
2941 tb l 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization but is not production tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. “X” in part number indicates power rating (S or L).
6.42
10
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE
or SEM
(9)
tAS (6)
tWP
(3)
(2)
tWR
R/W
tWZ (7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
2941 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tEW
tWR (3)
(2)
R/W
tDW
tDH
DATAIN
2941 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
11
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
tOH
VALID ADDRESS
tACE
tWR
tEW
SEM
tDW
DATA0
tSOP
DATA OUT
VALID(2)
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Write Cycle
Read Cycle
2941 drw 10
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
2941 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
6.42
12
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V05X15
Com'l Ony
Symbol
Parameter
70V05X20
Com'l
& Ind
70V05X25
Com'l Only
M i n.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY Acce ss Time fro m Ad d re ss Match
____
15
____
20
____
20
ns
BUSY Disab le Time fro m Ad d re ss No t Matche d
____
15
____
20
____
20
ns
BUSY Acce ss Time fro m Chip Enab le LOW
____
15
____
20
____
20
ns
BUSY Disab le Time fro m Chip Enab le HIGH
____
15
____
17
____
17
ns
5
____
5
____
5
____
ns
____
18
____
30
____
30
ns
12
____
15
____
17
____
ns
0
____
0
____
0
____
ns
12
____
15
____
17
____
ns
____
30
____
45
____
50
ns
____
25
____
35
____
35
ns
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
Arb itratio n Prio rity Se t-up Time
tBDD
BUSY Disab le to Valid Data(3)
tWH
Write Ho ld Afte r BUSY
(2)
(5)
BUSY TIMING (M/S = VIL)
BUSY Inp ut to Write (4)
tWB
tWH
Write Ho ld Afte r BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data De lay(1)
Write Data Valid to Re ad Data De lay
(1)
2941 tb l 13a
70V05X35
Com'l Only
Symbol
Parameter
70V05X55
Com'l Only
M i n.
Max.
Min.
Max.
Unit
BUSY Acce ss Time fro m Ad d re ss Match
____
20
____
45
ns
tBDA
BUSY Disab le Time fro m Ad d re ss No t Matche d
____
20
____
40
ns
tBAC
BUSY Acce ss Time fro m Chip Enab le LOW
____
20
____
40
ns
tBDC
BUSY Disab le Time fro m Chip Enab le HIGH
____
20
____
35
ns
tAPS
Arb itratio n Prio rity Se t-up Time (2)
5
____
5
____
ns
____
35
____
40
ns
25
____
25
____
ns
0
____
0
____
ns
25
____
25
____
ns
____
60
____
80
ns
____
45
____
65
BUSY TIMING (M/S = VIH)
tBAA
tBDD
tWH
(3)
BUSY Disab le to Valid Data
Write Ho ld Afte r BUSY
(5)
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Inp ut to Write (4)
Write Ho ld Afte r BUSY
(5)
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data De lay(1)
Write Data Valid to Re ad Data De lay
(1)
ns
2941 tb l 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to “Timing Waveform of Read With BUSY (M/S = VIH)” or “Timing Waveform of Write With PortTo-Port Delay (M/S = VIL)”.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. 'X' is part number indicates power rating (S or L).
6.42
13
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read with BUSY(2,4,5) (M/S=VIH)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
VALID
DATAIN "A"
tAPS
(1)
MATCH
ADDR"B"
tBDA
tBAA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD
(3)
2941 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE) then BUSY is input. For this example, BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the port opposite from Port “A”.
6.42
14
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH
R/W"B"
(1)
(2)
2941 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS
(2)
CE"B"
tBAC
tBDC
BUSY"B"
2941 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDRESS "N"
ADDR"A"
tAPS
(2)
MATCHING ADDRESS "N"
ADDR"B"
tBAA
tBDA
BUSY"B"
2941 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70V05X15
Com'l Only
Symbol
Parameter
70V05X20
Com'l
& Ind
70V05X25
Com'l Only
M i n.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Ad d re ss Se t-up Time
0
____
0
____
0
____
ns
tWR
Write Re co ve ry Time
0
____
0
____
0
____
ns
tINS
Inte rrup t Se t Time
____
15
____
20
____
20
ns
tINR
Inte rrup t Re se t Time
____
15
____
20
____
20
ns
2941 tb l 14a
70V05X35
Com'l Only
Symbol
Parameter
70V05X55
Com'l Only
M i n.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Ad d re ss Se t-up Time
0
____
0
____
ns
tWR
Write Re co ve ry Time
0
____
0
____
ns
tINS
Inte rrup t Se t Time
____
25
____
40
ns
tINR
Inte rrup t Re se t Time
____
25
____
40
ns
2941 tb l 14b
NOTES:
1. 'X' in part number indicates power rating (S or L).
6.42
16
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing
(1)
tWC
(2)
INTERRUPT SET ADDRESS
ADDR"A"
tAS
(3)
(4)
tWR
CE"A"
R/W"A"
(3)
tINS
INT"B"
2941 drw 16
tRC
INTERRUPT CLEAR ADDRESS
ADDR"B"
tAS
(2)
(3)
CE"B"
OE"B"
(3)
tINR
INT"B"
2941 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
17
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
R/WL
CEL
Right Port
A12L-A0L
OEL
INTL
R/WR
CER
OER
A12R-A0R
L
L
X
1FFF
X
X
X
X
X
X
X
X
X
X
X
L
L
(3)
L
L
(2)
X
X
X
X
X
X
L
X
L
L
1FFE
H
Function
INTR
(2)
L
Se t Rig ht INTR Flag
1FFF
H(3)
Re se t Rig ht INTR Flag
X
1FFE
X
Se t Le ft INTL Flag
X
X
X
Re se t Le ft INTL Flag
2941tb l 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
CEL
CER
A12L-A0L
A12R-A0R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
No rmal
H
X
MATCH
H
H
No rmal
X
H
MATCH
H
H
No rmal
L
L
MATCH
(2)
(2)
Write Inhib it(3)
2941 tb l 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V05 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. VIL if the inputs to the opposite port were stable prior to the address and enable inputs of this port. VIH if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving low regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Actio n
1
1
Se map ho re fre e
Le ft Po rt Write s "0" to Se map ho re
0
1
Le ft p o rt has se map ho re to ke n
Rig ht Po rt Write s "0" to Se map ho re
0
1
No chang e . Rig ht sid e has no write acce ss to se map ho re
Le ft Po rt Write s "1" to Se map ho re
1
0
Rig ht p o rt o b tains se map ho re to ke n
Le ft Po rt Write s "0" to Se map ho re
1
0
No chang e . Le ft p o rt has no write acce ss to se map ho re
Rig ht Po rt Write s "1" to Se map ho re
0
1
Le ft p o rt o b tains se map ho re to ke n
Le ft Po rt Write s "1" to Se map ho re
1
1
Se map ho re fre e
Rig ht Po rt Write s "0" to Se map ho re
1
0
Rig ht p o rt has se map ho re to ke n
Rig ht Po rt Write s "1" to Se map ho re
1
1
Se map ho re fre e
Le ft Po rt Write s "0" to Se map ho re
0
1
Le ft p o rt has se map ho re to ke n
Le ft Po rt Write s "1" to Se map ho re
1
1
Se map ho re fre e
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V05.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
6.42
18
2941 tb l 17
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
BUSY (L)
CE
MASTER
Dual Port
SRAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
MASTER
CE
Dual Port
SRAM
BUSY (L) BUSY (R)
SLAVE
CE
Dual Port
SRAM
BUSY (L) BUSY (R)
DECODER
Industrial and Commercial Temperature Ranges
BUSY (R)
2941 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V05 SRAMs.
Functional Description
The IDT70V05 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V05 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is set when the right port writes to memory location 1FFE
(HEX). The left port clears the interrupt by reading address location
1FFE. Likewise, the right port interrupt flag (INTR) is set when the left
port writes to memory location 1FFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 1FFF. The
message (8 bits) at 1FFE or 1FFF is user-defined. If the interrupt
function is not used, address locations 1FFE and 1FFF are not used
as mail boxes, but as part of the random access memory. Refer to
Truth Table III for the interrupt operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation. If the write inhibit function of
BUSY logic is not desirable, the BUSY logic can be disabled by placing
the part in slave mode with the M/S pin. Once in slave mode the BUSY
pin operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the BUSY pins HIGH. If desired, unintended
write operations can be prevented to a port by tying the BUSY pin for
that port LOW.
The BUSY outputs on the IDT 70V05 SRAM in master mode, are
push-pull type outputs and do not require pull up resistors to
operate. If these SRAMs are being expanded in depth, then the
BUSY indication for the resulting array requires the use of an external
AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V05 SRAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V05 SRAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Semaphores
The IDT70V05 is a fast Dual-Port 8K x 8 CMOS Static RAM with
an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the DualPort SRAM to claim a privilege over the other processor for functions
defined by the system designer’s software. As an example, the
semaphore can be used by one processor to inhibit the other from
accessing a portion of the Dual-Port SRAM or any other shared
resource.
The Dual-Port SRAM features a fast access time, and both ports are
6.42
19
70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or accessed, at the same time with the only possible conflict arising from
the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port SRAM. These devices
have an automatic power-down feature controlled by CE, the Dual-Port
SRAM enable, and SEM, the semaphore enable. The CE and SEM pins
control on-chip power down circuitry that permits the respective port to go
into standby mode when not selected. This is the condition which is shown
in Truth Table II where CE and SEM are both HIGH.
Systems which can best use the IDT70V05 contain multiple processors
or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70V05's hardware semaphores, which provide a lockout mechanism without requiring complex
programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V05 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active low. A token is requested by writing
a zero into a semaphore latch and is released when the same side
writes a one to that latch.
The eight semaphore flags reside within the IDT70V05 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which can
be accessed by either side through address pins A0 – A2. When accessing
the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a LOW level
is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero. When
a one is written into the same location from the same side, the flag will be
set to a one for both sides (unless a semaphore request from the other side
is pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processor writes a zero to the left port at a free semaphore location. On
a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no longer
needs the resource, the entire system can hang up until a one is written
into that semaphore request latch.
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70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V05’s Dual-Port SRAM. Say the
8K x 8 SRAM was to be divided into two 4K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
the lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 4K of Dual-Port
SRAM, the processor on the left port could write and then read a
zero in to Semaphore 0. If this task were successfully completed
(a zero was read back rather than a one), the left processor would
assume control of the lower 4K. Meanwhile the right processor was
attempting to gain control of the resource after the left processor, it
would read back a one in response to the zero it had attempted to
write into Semaphore 0. At this point, the software could choose to try
and gain control of the second 4K section by writing, then reading a zero
into Semaphore 1. If it succeeded in gaining control, it would lock out
the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could undo
its semaphore request and perform other tasks until it was able to write, then
read a zero into Semaphore 1. If the right processor performs a similar task
with Semaphore 0, this protocol would allow the two processors to swap
4K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-Port SRAM or other shared resources into eight parts. Semaphores
can even be assigned different meanings on different sides rather than
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
D
WRITE
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
2941 drw 19
Figure 4. IDT70V05 Semaphore Logic
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70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
999
A
Device
Type
Power
Speed
Package
A
A
A
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
PF
J
64-pin TQFP (PNG64)
68-pin PLCC (PLG68)
15
20
Commercial Only
Industrial Only
L
Low Power
70V05
64K (8K x 8) 3.3V Dual-Port RAM
Speed in nanoseconds
2941 drw 20
NOTE:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN#SP-17-02
Note that information regarding recently obsoleted parts is included in this datasheet for customer convenience.
Orderable Part Information
Speed
(ns)
15
20
Pkg.
Code
Pkg.
Type
Temp.
Grade
70V05L15JG
PLG68
PLCC
C
70V05L15JG8
PLG68
PLCC
C
70V05L15PFG
PNG64
TQFP
C
Orderable Part ID
70V05L15PFG8
PNG64
TQFP
C
70V05L20PFGI
PNG64
TQFP
I
70V05L20PFGI8
PNG64
TQFP
I
6.42
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70V05L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
03/11/99:
06/09/99:
11/10/99:
03/10/00:
05/26/00:
12/04/01:
07/27/06:
10/23/08:
06/14/12:
03/16/18:
06/14/19:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changed drawing format
Replaced IDT logo
Added 15 & 20ns speed grades
Upgraded DC parameters
Added Industrial Temperature information
Changed ±200mV to 0mV in notes
Page 5 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters2–changed wording from open to disabled
Page 2 & 3 Added date revision to pin configurations
Page 2, 3, 5 & 6 Changed naming conventions from VCC to VDD and from GND to VSS
Page 6, 8, 10, 13 & 16 Removed industrial temp for 25ns, 35ns and 55ns from DC & AC Electrical Characteristics
Page 22 Removed industrial temp from 25ns, 35ns and 55ns from ordering information
Page 1 & 22 Replaced TM logo with ® logo
Page 1 Added green availability to features
Page 22 Added green indicator to ordering information
Page 22 Removed "IDT" from orderable part number
Page 11 Corrected footnote 9 from VIN to VIH, to read "To access RAM, CE = VIL and SEM = VIH".Page
Page 22 Added T& R indicator to ordering information
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Page 1 & 22 Deleted obsolete Commercial speed grades 20/25/35/55ns in Features and Ordering Information
Page 2 Rotated PLG68 PLCC and PNG64 TQFP pin configurations to accurately reflect pin 1 orientation
Page 1 & 22 Removed GU68 PGA package
Page 22 Added Orderable Part Information
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6.42
23
for Tech Support:
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