70V3599/89S
HIGH-SPEED 3.3V 128/64K x 36
SYNCHRONOUS DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
◆
◆
◆
◆
◆
◆
◆
◆
Functional Block Diagram
BE3L
BE3R
BE2L
BE2R
BE1L
BE1R
BE0L
BE0R
FT/PIPEL
1/0
0a 1a
0b 1b
0c 1c
0d 1d
1d 0d
1c 0c
1b 0b
1a 0a
a
b
c
d
d
c
b
a
FT/PIPER
1/0
R/WL
R/WR
CE0L
CE1L
1
1
0
0
B B
WW
0 1
L L
1/0
OEL
B B B
WWW
2 3 3
L L R
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
B
W
2
R
B B
WW
1 0
R R
1/0
OER
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
1d 0d 1c 0c 1b 0b 1a 0a
FT/PIPEL
CE0R
CE1R
0a 1a 0b 1b
0c 1c 0d 1d
FT/PIPER
0/1
0/1
ab cd
d cba
128K x 36
MEMORY
ARRAY
I/O0L - I/O35L
Din_L
I/O0R - I/O35R
Din_R
CLKR
CLKL
A0L
REPEATL
ADSL
CNTENL
,
A16R(1)
A16L (1)
Counter/
Address
Reg.
Counter/
Address
Reg.
ADDR_R
ADDR_L
A0R
REPEATR
ADSR
CNTENR
5617 tbl 01
NOTE:
1. A16 is a NC for IDT70V3589.
TDI
JTAG
TDO
1
Feb.03.20
TCK
TMS
TRST
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Description:
The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3599/89 has been optimized for applications having unidirectional
Industrial and Commercial Temperature Ranges
or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3599/89 can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4,5)
A1
A2
IO19L IO18L
A3
VSS
A4
TDO
A5
NC
A7
A6
A16L(1
A12L
A8
A8L
A9
BE1L
A11
A10
A12
A13
CLKL CNTENL A4L
VDD
A14
A0L
A15
A17
A16
OPTL I/O17L
VSS
)
B1
B2
I/O20R
C1
B3
VSS I/O18R
C2
C3
B4
TDI
C4
B5
NC
C5
VDDQL I/O19R VDDQR PL/FTL
D1
D2
I/O22L
VSS
E2
E1
D3
D4
NC
D5
I/O21L I/O20L A15L
E3
B6
A13L
C6
A14L
D6
A11L
B7
A9L
C7
A10L
D7
A7L
B8
BE2L
C8
B9
CE0L
C9
BE3L CE1L
D8
BE0L
D9
VDD
B11
B10
ADSL
VSS
C11
C10
VSS
D10
R/WL
D11
OEL REPEATL
B12
A5L
C12
A6L
D12
A3L
B13
A1L
C13
A2L
D13
B14
VSS
C14
B15
C15
D14
D15
E4
E14
E15
F1
F14
F3
G1
G2
I/O26L VSS
H2
H1
G3
F4
G14
G4
J2
VDDQ
VDD
J3
VSS
J4
I/O28R
L1
K2
VSS
L2
K3
VDD
J14
VSS
208-Pin fpBGA
Top View(7)
K4
I/O27R VSS
L3
H14
VSS
L
K1
K14
M2
M3
L4
L14
I/O6R
M4
M14
VDDQL I/O29L I/O30R VSS
N1
I/O31L
P1
N2
N3
VSS
N4
N14
P3
P4
P5
P6
P7
I/O32R I/O32L VDDQR I/O35R TRST A16R(1) A12R
R1
VSS
T1
R2
R3
R4
I/O33L I/O34R TCK
T2
T3
T4
I/O33R I/O34L VDDQL TMS
U1
VSS
U2
U3
I/O35L PL/FTR
U4
NC
E17
VSS
F16
I/O13L
F17
G15
G16
G17
H15
IO9R
J15
VDD
K15
H16
H17
VSS
J16
L
L15
I/O7L
M15
R5
NC
T5
NC
U5
A15R
R6
A13R
T6
A14R
U6
A11R
R7
A9R
T7
A10R
U7
A7R
P8
A8R
R8
P9
BE1R
R9
BE2R CE0R
T8
T9
BE3R CE1R
U8
BE0R
U9
VDD
P10
VDD
R10
VSS
T10
VSS
U10
P11
P12
CLKR CNTEN
R11
ADSR
T11
R/WR
U11
R
R12
A5R
T12
A6R
U12
OER REPEATR A3R
P13
A4R
R13
A1R
T13
A2R
U13
A0R
P14
J17
K16
K17
L16
VSS
T14
VSS
U14
VDD
VSS
L17
VSS
M16
I/O8L
M17
I/O6L I/O5R VDDQR
N15
P15
I/O2L I/O3L
R14
I/O10R
VSS VDDQR
N16
N17
I/O3R VDDQL I/O4R
VSS I/O31R I/O30L
P2
F15
E16
I/O7R VDDQ I/O8R
I/O29R I/O28L VDDQR I/O27L
M1
D17
D16
I/O9L VDDQL I/O10L I/O11R
70V3599/89
BF208(6)
BFG208(6)
H4
VDD I/O26R VDDQR I/O25R
J1
VSS
VSS I/O12R I/O11L VDDQR
VSS
I/O25L I/O24R
H3
C17
VDD I/O17R VDDQL I/O14L I/O14R
I/O12L I/O13R
F2
C16
VDD I/O16R I/O15L
I/O23L I/O22R VDDQR I/O21R
VDDQL I/O23R I/O24L
B17
B16
VDDQR I/O16L I/O15R
R15
P16
I/O5L
P17
VSS
R16
I/O4L
R17
VDDQL I/O1R VDDQR
T15
I/O0R
U15
T17
T16
VSS
U16
I/O2R
U17
OPTR I/O0L I/O1L
,
5617 drw 02c
NOTES:
1. A16 is a NC for IDT70V3589.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
2
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Pin Configuration
(1,2,3,4,5)
Industrial and Commercial Temperature Ranges
(con't.)
70V3599/89
BC256(6)
BCG256(6)
256-Pin BGA
Top View(7)
A1
NC
B1
I/O18L
C1
A2
TDI
B2
NC
C2
I/O18R I/O19L
D1
D2
A3
NC
B3
TDO
C3
VSS
D3
A4
NC
B4
NC
C4
A5
A6
A14L
A11L
B5
A15L
C5
A16L(1) A13L
D4
D5
B6
A12L
C6
A10L
D6
A7
A8L
B7
A9L
C7
A7L
D7
A8
A9
BE2L
CE1L
B9
B8
BE3L
C8
A10
A11
B10
B11
CE0L R/WL REPEATL
C9
C10
C11
BE1L BE0L CLKL ADSL
D9
D8
A12
OEL CNTENL A5L
D10
D11
B12
A4L
C12
A6L
D12
A13
A2L
B13
A1L
C13
A3L
D13
A14
A0L
B14
VDD
C14
A15
A16
NC
B15
NC
B16
I/O17L
NC
C16
C15
OPTL I/O17R I/O16L
D14
D16
D15
I/O20R I/O19R I/O20L PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
E1
E2
E3
E4
I/O21R I/O21L I/O22L VDDQL
F1
F2
F3
F4
E5
VDD
F5
I/O23L I/O22R I/O23R VDDQL VDD
G1
G2
G3
G4
I/O24R I/O24L I/O25L VDDQR
H1
H2
H3
H4
G5
VSS
H5
I/O26L I/O25R I/O26R VDDQR VSS
J1
J2
J3
J4
I/O27L I/O28R I/O27R VDDQL
K1
K2
K3
K4
J5
VSS
K5
I/O29R I/O29L I/O28L VDDQL VSS
L1
L2
L3
L4
L5
I/O30L I/O31R I/O30R VDDQR VDD
M1
M2
M3
M4
I/O32R I/O32L I/O31L VDDQR
N1
N2
N3
N4
M5
VDD
N5
E6
VDD
F6
VSS
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
VSS
M6
VDD
N6
E7
VSS
F7
VSS
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
F9
F8
VSS
VSS
G9
G8
VSS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
VSS
K9
VSS
L8
VSS
L9
VSS
M8
VSS
M9
VSS
N8
VSS
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
F12
P2
P3
P4
P5
I/O35R I/O34L TMS A16R(1) A13R
R1
I/O35L
T1
NC
R2
NC
T2
TCK
R3
TRST
T3
NC
R4
NC
T4
NC
R5
A15R
T5
A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
P10
P11
BE1R BE0R CLKR ADSR
R8
R9
R10
R11
G12
VSS
H12
VSS
J12
T9
BE2R CE1R
T10
T11
E16
E15
F13
F14
F15
F16
G13
G14
G16
G15
VDDQL I/O10L I/O11L I/O11R
H13
H14
VDDQL I/O9R
J13
J14
H16
H15
IO9L I/O10R
J15
J16
VSS VDDQR I/O8R I/O7R I/O8L
K12
VSS
L12
VDD
M12
VDD
N12
P12
A6R
R12
BE3R CE0R R/WR REPEATR A4R
T8
E14
VDD VDDQR I/O12R I/O13R I/O12L
I/O33L I/O34R I/O33R PIPE/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
P1
E13
VDD VDDQR I/O13L I/O14L I/O14R
T12
OER CNTENR A5R
K13
K14
K15
K16
VDDQR I/O6R I/O6L I/O7L
L13
L14
VDDQL I/O5L
M13
M14
VDDQL I/O3R
N13
VDD
P13
A3R
R13
A1R
T13
A2R
N14
I/O2L
P14
L16
L15
I/O4R I/O5R
M16
M15
I/O3L I/O4L
N16
N15
I/O1R I/O2R
P15
P16
I/O0L I/O0R
R14
OPTR
T14
A0R
I/O1L
R16
R15
NC
T15
NC
,
T16
NC
NC
5617 drw 02d
,
NOTES:
1. A16 is a NC for IDT70V3589.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
6.42
3
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(con't.)
70V3599/89
DRG208(6)
208-Pin PQFP
Top View
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
VSS
I/O21L
I/O21R
I/O22L
I/O22R
VDDQR
VSS
I/O23L
I/O23R
I/O24L
I/O24R
VDDQL
VSS
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
VSS
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
VSS
I/O33R
I/O33L
I/O34R
I/O34L
VSS
VDDQR
I/O17R
I/O17L
OPTL
VSS
VDD
VDD
A0L
A1L
A2L
A3L
A4L
A5L
A6L
REPEATL
CNTENL
ADSL
R/WL
OEL
CLKL
VSS
VSS
VDD
VDD
CE0L
CE1L
BE0L
BE1L
BE2L
BE3L
A7L
A8L
A9L
A10L
A11L
A12L
A13L
A14L
A15L
A16L(1)
NC
NC
NC
TDO
TDI
PL/FTL
VSS
I/O18L
I/O18R
VDDQ
VSS
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
I/O16L
I/O16R
I/O15L
I/O15R
VSS
VDDQL
I/O14L
I/O14R
I/O13L
I/O13R
VSS
VDDQR
I/O12L
I/O12R
I/O11L
I/O11R
VSS
VDDQL
I/O10L
I/O10R
I/O9L
I/O9R
VSS
VDDQR
VDD
VDD
VSS
VSS
VSS
VDDQL
I/O8R
I/O8L
I/O7R
I/O7L
VSS
VDDQR
I/O6R
I/O6L
I/O5R
I/O5L
VSS
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
Pin Configuration
(1,2,3,4,5)
VSS
VDDQL
I/O0R
I/O0L
OPTR
VSS
VSS
VDD
A0R
A1R
A2R
A3R
A4R
A5R
A6R
REPEATR
CNTENR
ADSR
R/WR
OER
CLKR
VSS
VSS
VDD
VDD
CE0R
CE1R
BE0R
BE1R
BE2R
BE3R
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R(1)
NC
NC
NC
TRST
TCK
TMS
PL/FTR
I/O35L
I/O35R
VDDQL
VSS
5617 drw 02
NOTES:
1.
2.
3.
4.
5.
6.
A16 is a NC for IDT70V3589.
All VDD pins must be connected to 3.3V power supply.
All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V).
All VSS pins must be connected to ground supply.
Package body is approximately 28mm x 28mm x 3.5mm.
This package code is used to reference the package diagram.
6.42
4
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables(5)
R/WL
R/WR
Read/Write Enable
Output Enable
OER
OEL
(1)
(1)
A0L - A16L
A0R - A16R
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
CLKL
CLKR
Clock
PL/FTL
PL/FTR
Pipeline/Flow-Through
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
REPEATL
REPEATR
Counter Repeat(4)
BE0L - BE3L
BE0R - BE3R
Byte Enables (9-bit bytes)(5)
VDDQL
VDDQR
OPTL
OPTR
Address
Power (I/O Bus) (3.3V or 2.5V)(2)
(2,3)
Option for selecting VDDQX
(2)
VDD
Power (3.3V)
VSS
Ground (0V)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
5617 tbl 01
NOTES:
1. A16 is a NC for IDT70V3589.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
5
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control
(1,2,3,4)
OE
CLK
CE0
CE1
BE3
BE2
BE1
BE0
R/W
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
MODE
X
↑
H
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
H
H
L
L
High-Z
High-Z
High-Z
DIN
Write to Byte 0 Only
X
↑
L
H
H
H
L
H
L
High-Z
High-Z
DIN
High-Z
Write to Byte 1 Only
X
↑
L
H
H
L
H
H
L
High-Z
DIN
High-Z
High-Z
Write to Byte 2 Only
X
↑
L
H
L
H
H
H
L
DIN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
↑
L
H
H
H
L
L
L
High-Z
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
X
↑
L
H
L
L
H
H
L
DIN
DIN
High-Z
High-Z
Write to Upper 2 bytes Only
X
↑
L
H
L
L
L
L
L
DIN
DIN
DIN
DIN
Write to All Bytes
L
↑
L
H
H
H
H
L
H
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
↑
L
H
H
H
L
H
H
High-Z
High-Z
DOUT
High-Z
Read Byte 1 Only
L
↑
L
H
H
L
H
H
H
High-Z
DOUT
High-Z
High-Z
Read Byte 2 Only
L
↑
L
H
L
H
H
H
H
DOUT
High-Z
High-Z
High-Z
Read Byte 3 Only
L
↑
L
H
H
H
L
L
H
High-Z
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
L
↑
L
H
L
L
H
H
H
DOUT
DOUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
↑
L
H
L
L
L
L
H
DOUT
DOUT
DOUT
DOUT
H
↑
L
H
L
L
L
L
X
High-Z
High-Z
High-Z
High-Z
Read All Bytes
Outputs Disabled
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5617 tbl 02
Truth Table II—Address Counter Control(1,2)
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS
CNTEN
REPEAT(6)
I/O(3)
X
X
An
↑
X
X
L(4)
DI/O(0)
Counter Reset to last valid ADS load
(4)
MODE
An
X
An
↑
L
X
H
DI/O (n)
External Address Used
An
Ap
Ap
↑
H
H
H
DI/O(p)
External Address Blocked—Counter disabled (Ap reused)
H
DI/O(p+1)
X
Ap
Ap + 1
↑
H
(5)
L
Counter Enabled—Internal Address generation
5617 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
6
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Recommended DC Operating
Conditions with VDDQ at 2.5V
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Commercial
Industrial
Industrial and Commercial Temperature Ranges
Symbol
Parameter
Min.
Typ.
Max.
Unit
3.15
3.3
3.45
V
2.4
2.5
2.6
V
0
0
0
Input High Voltage
(Address & Control Inputs)
1.7
____
VDDQ + 100mV
(2)
V
Input High Voltage - I/O(3)
1.7
____
VDDQ + 100mV(2)
V
____
0.7
V
Ambient
Temperature
GND
VDD
VDD
Core Supply Voltage
0OC to +70OC
0V
3.3V + 150mV
VDDQ
I/O Supply Voltage
(3)
-40OC to +85OC
0V
3.3V + 150mV
VSS
Ground
VIH
VIH
5617 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
VIL
(1)
Input Low Voltage
-0.3
V
5617 tb l 05a
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 100mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied
as indicated above.
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6
V
TBIAS(3)
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-65 to +150
o
C
Symbol
TJN
Junction Temperature
+150
o
C
VDD
VDDQ
I/O Supply Voltage
VSS
Ground
VIH
VIH
IOUT
DC Output Current
50
Recommended DC Operating
Conditions with VDDQ at 3.3V
mA
5617 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
VIL
Min.
Typ.
Max.
Unit
Core Supply Voltage
3.15
3.3
3.45
V
(3)
3.15
3.3
3.45
V
0
0
0
Input High Voltage
(Address & Control Inputs)(3)
2.0
____
VDDQ + 150mV
(2)
V
Input High Voltage - I/O(3)
2.0
____
VDDQ + 150mV(2)
V
____
0.8
V
Input Low Voltage
(1)
-0.3
V
5617 tbl 05b
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
7
Feb.03.20
Parameter
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
CIN
COUT(3)
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
V IN = 3dV
8
pF
VOUT = 3dV
10.5
pF
5617 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3599/89S
Symbol
|ILI|
|ILO|
Parameter
Input Leakage Current(1)
(1)
Output Leakage Current
Test Conditions
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to V DDQ
___
10
µA
10
µA
CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ
___
VOL (3.3V)
Output Low Voltage
(2)
IOL = +4mA, VDDQ = Min.
___
0.4
V
VOH (3.3V)
Output High Voltage (2)
IOH = -4mA, VDDQ = Min.
2.4
___
V
VOL (2.5V)
(2)
IOL = +2mA, VDDQ = Min.
___
0.4
V
(2)
IOH = -2mA, VDDQ = Min.
2.0
___
V
VOH (2.5V)
Output Low Voltage
Output High Voltage
5617 tbl 08
NOTE:
1. At VDD < 2.0V leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
6.42
8
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70V3599/89S166
Com'l Only
70V3599/89S133
Com'l
& Ind
Typ. (4)
Max.
Typ.(4)
Max.
Unit
mA
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
S
370
500
320
400
IND
S
____
____
320
480
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH,
Outputs Disabled,
f = fMAX(1)
COM'L
S
125
200
115
160
IND
S
____
____
115
195
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
250
350
220
290
IND
S
____
____
220
350
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports Outputs Disabled
CEL and CER > VDDQ - 0.2V,
VIN > VDDQ - 0.2V or VIN < 0.2V,
f = 0(2)
COM'L
S
15
30
15
30
IND
S
____
____
15
40
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
VIN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
f = fMAX(1)
COM'L
S
250
350
220
290
IND
S
____
____
220
350
(5)
mA
mA
mA
mA
5617 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
9
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2.5V
833Ω
2ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
DATAOUT
5pF*
770Ω
Figures 1 and 2
5617 tbl 10
,
3.3V
590Ω
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
,
DATAOUT
435Ω
5pF*
5617 drw 03
Figure 1. AC Output Test load.
5617 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
ΔtCD
(Typical, ns) 3
2
•
1
•
20.5
•
30
•
50
80
100
200
-1
Capacitance (pF)
5617 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
10
Feb.03.20
,
,
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV)
70V3599/89S166
Com'l Only
Symbol
tCYC1
tCYC2
Parameter
Clock Cycle Time (Flow-Through)(1)
Clock Cycle Time (Pipelined)
(1)
(1)
tCH1
Clock High Time (Flow-Through)
tCL1
Clock Low Time (Flow-Through)(1)
tCH2
Clock High Time (Pipelined)
(2)
(1)
70V3599/89S133
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
20
____
25
____
ns
6
____
7.5
____
ns
6
____
7
____
ns
6
____
7
____
ns
2.1
____
2.6
____
ns
2.1
____
2.6
____
ns
ns
tCL2
Clock Low Time (Pipelined)
tSA
Address Setup Time
1.7
____
1.8
____
tHA
Address Hold Time
0.5
____
0.5
____
ns
tSC
Chip Enable Setup Time
1.7
____
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
ns
tSB
Byte Enable Setup Time
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
ns
tSW
R/W Setup Time
1.7
____
1.8
____
ns
tHW
R/W Hold Time
0.5
____
0.5
____
ns
tSD
Input Data Setup Time
1.7
____
1.8
____
ns
tHD
Input Data Hold Time
0.5
____
0.5
____
ns
ADS Setup Time
1.7
____
1.8
____
ns
ns
tSAD
ADS Hold Time
0.5
____
0.5
____
tSCN
CNTEN Setup Time
1.7
____
1.8
____
ns
tHCN
CNTEN Hold Time
0.5
____
0.5
____
ns
REPEAT Setup Time
1.7
____
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.0
____
4.2
ns
tOLZ
Output Enable to Output Low-Z
1
____
1
____
ns
tOHZ
Output Enable to Output High-Z
tHAD
tSRPT
tCD1
Clock to Data Valid (Flow-Through)
(1)
(1)
1
3.6
1
4.2
ns
____
12
____
15
ns
____
3.6
____
4.2
ns
____
1
____
ns
tCD2
Clock to Data Valid (Pipelined)
tDC
Data Output Hold After Clock High
1
tCKHZ
Clock High to Output High-Z
1
3
1
3
ns
tCKLZ
Clock High to Output Low-Z
1
____
1
____
ns
5
____
6
____
ns
Port-to-Port Delay
tCO
Clock-to-Clock Offset
5617 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
6.42
11
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tSB
tHB
BEn
R/W
ADDRESS
(4)
tSW
tHW
tSA
tHA
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
tOE
5617 drw 06
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
(3)
CE1
tSB
tHB
BEn
tSB
R/W
tHB
tSW tHW
tSA
ADDRESS
tHC
(4)
tHA
An
An + 1
tCD1
An + 2
tCKHZ
Qn
DATAOUT
Qn + 2 (5)
Qn + 1
tCKLZ
OE
An + 3
tDC
tOHZ
tOLZ
tDC
(1)
tOE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
12
Feb.03.20
5617 drw 07
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
Q0
DATAOUT(B1)
tCKHZ
tSA
Q3
tCKLZ
tDC
tCKHZ
tHA
A0
tSC
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
tCD2
Q1
tDC
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
5617 drw 08
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
tCH1
tCYC1
tCL1
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC
tHC
tSC
tCD1
tHC
tCD1
tCKHZ
D0
DATAOUT(B1)
tSC
tCD1
D3
tCKLZ
tDC
A1
(1)
D5
tCKHZ (1)
tCKLZ
(1)
A6
A5
A4
A3
A2
tSC
CE0(B2)
tCD1
tHA
A0
ADDRESS(B2)
(1)
D1
tDC
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
5617 drw 09
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3599/89 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W and REPEAT = VIH.
6.42
13
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A"
ADDRESS"A"
tSD
DATAIN"A"
NO
MATCH
MATCH
tHD
VALID
tCO(3)
CLK"B"
tCD2
R/W"B"
ADDRESS"B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
DATAOUT"B"
VALID
tDC
5617 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1 and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW
tHW
tSA
tHA
R/W "A"
ADDRESS "A"
tSD
DATAIN "A"
NO
MATCH
MATCH
tHD
VALID
tCO
(3)
CLK "B"
tCD1
R/W "B"
ADDRESS "B"
tSW
tHW
tSA
tHA
NO
MATCH
MATCH
tCD1
DATAOUT "B"
VALID
VALID
tDC
tDC
5617 drw 11
NOTES:
1. CE0, BEn, and ADS = VIL; CE1 and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
14
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
tCYC2
(OE = VIL)(2)
tCH2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
READ
NOP
(4)
WRITE
READ
5617 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1 and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Qn
DATAOUT
An + 4
An + 5
tHD
Dn + 2
tCD2
(1)
An + 3
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
5617 drw 13
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1 and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
15
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(1)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKLZ
tCKHZ
READ
NOP
(5)
Qn + 3
tDC
READ
WRITE
6517 drw 14
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
BEn
tSW tHW
tSW tHW
R/W
(3)
An
tSA tHA
ADDRESS
An +1
DATAIN
(1)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
An + 4
tOE
tCD1
Qn
tCKLZ
tOHZ
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
5617 drw 15
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1 and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
16
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5617 drw 16
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA tHA
ADDRESS
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5617 drw 17
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
17
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5617 drw 18
Timing Waveform of Counter Repeat(2)
tCH2
tCYC2
tCL2
CLK
tSA tHA
(4)
An
ADDRESS
INTERNAL(3)
ADDRESS
LAST ADS LOAD
Ax
An + 2
An + 1
LAST ADS +1
An
An + 1
tSW tHW
R/W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRPT tHRPT
REPEAT
tSD
tHD
D0
DATAIN
(5)
QLAST
DATAOUT
(6)
EXECUTE
REPEAT
WRITE
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS
READ
LAST ADS
ADDRESS + 1
QLAST+1
READ
ADDRESS n
Qn
READ
ADDRESS n+1
5617 drw 19
NOTES:
1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
18
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Functional Description
Depth and Width Expansion
The IDT70V3599/89 provides a true synchronous Dual-Port Static
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse is independent of the LOW to HIGH transition of the clock
signal.
An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3599/89s for depth
expansion configurations. Two cycles are required with CE0 LOW and
CE1 HIGH to re-activate the outputs.
The IDT70V3599/89 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V3599/89 can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 72-bits or wider.
A17/A16(1)
IDT70V3599/89
CE0
CE1
IDT70V3599/89
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V3599/89
CE0
IDT70V3599/89
CE1
CE1
CE0
CE0
Control Inputs
Control Inputs
5617 drw 20
Figure 4. Depth and Width Expansion with IDT70V3599/89
NOTE:
1. A17 is for IDT70V3599, A16 is for IDT70V3589.
6.42
19
Feb.03.20
BE,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
5617 drw 21
tJRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70V3599/89
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
(1)
tJR
JTAG Clock Rise Time
____
3
ns
tJF
JTAG Clock Fall Time
____
3(1)
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
5617 tbl 12
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
20
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x0
Reserved for version number
IDT Device ID (27:12)
0x0312(1)
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Defines IDT part number
Allows unique identification of device vendor as IDT
1
Indicates the presence of an ID register
5617 tbl 13
NOTE:
1. Device ID for IDT70V3589 is 0x0313.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
5617 tbl 14
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the bound ary scan cells onto the device outputs (1).
Places the boundary scan registe r (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass registe r (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0011
Places the bypass register (BYR) be tween TDI and TDO. Forces all
device output drivers to a High-Z state.
0001
Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the b oundary scan cells via the TDI.
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
HIGHZ
SAMPLE/PRELOAD
RESERVED
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
21
Feb.03.20
5617 tbl 15
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
XXXXX
A
999
A
Device
Type
Power
Speed
Package
A
A
Process/
Temperature
Range
Blank
8
Tray
Tape and Reel
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(1)
Green
BF
DR
BC
208-pin fpBGA (BF208, BFG208)
208-pin PQFP (DRG208)
256-pin BGA (BC256, BCG256)
166
133
Commercial Only
Speed in Megahertz
Commercial & Industrial
S
Standard Power
70V3599 4Mbit (128K x 36-Bit) Synchronous Dual-Port RAM
70V3589 2Mbit (64K x 36-Bit) Synchronous Dual-Port RAM
5617 drw 22
NOTE:
1. Green parts available. For specific speeds, packages and powers contact your local sales office.
LEAD FINISH (containing SnPb) are obsolete excluding BGA and Hermetic packages.
Note; the information regarding recently obsoleted parts is included in this datasheet for customer convenience. Please see the Orderable Parts Table for the
current, active part list.
ORDERABLE PART INFORMATION
133
Pkg.
Type
Temp.
Grade
70V3589S133BC
BC256
CABGA
C
C
70V3589S133BC8
BC256
CABGA
C
I
70V3589S133BCI
BC256
CABGA
I
I
70V3589S133BCI8
BC256
CABGA
I
CABGA
I
70V3589S133BF
BF208
CABGA
C
CABGA
C
70V3589S133BF8
BF208
CABGA
C
BF208
CABGA
C
70V3589S133BFI
BF208
CABGA
I
BFG208
CABGA
I
70V3589S133BFI8
BF208
CABGA
I
DRG208
PQFP
C
DRG208
PQFP
I
70V3589S166BC
BC256
CABGA
C
BC256
CABGA
C
BCG256
CABGA
C
Pkg.
Type
Temp.
Grade
Speed
(MHz)
BC256
CABGA
C
133
70V3599S133BC8
BC256
CABGA
70V3599S133BCGI
BCG256
CABGA
70V3599S133BCI
BC256
CABGA
70V3599S133BCI8
BC256
70V3599S133BF
BF208
70V3599S133BF8
70V3599S133BFGI
Orderable Part ID
70V3599S133BC
Orderable Part ID
BFG208
CABGA
I
70V3589S133DRG
70V3599S133BFI
BF208
CABGA
I
70V3589S133DRGI
70V3599S133BFI8
BF208
CABGA
I
70V3599S133BFGI8
166
DRG208
PQFP
I
70V3589S166BC8
70V3599S166BC
BC256
CABGA
C
70V3589S166BCG
70V3599S166BC8
BC256
CABGA
C
70V3589S166BF
BF208
CABGA
C
BF208
CABGA
C
BFG208
CABGA
C
70V3599S133DRGI
166
Pkg.
Code
Pkg.
Code
Speed
(MHz)
BCG256
CABGA
C
70V3589S166BF8
70V3599S166BF
BF208
CABGA
C
70V3589S166BFG
70V3599S166BF8
BF208
CABGA
C
70V3589S166BFG8
BFG208
CABGA
C
70V3589S166DRG
DRG208
PQFP
C
70V3599S166BCG
70V3599S166BFG
BFG208
CABGA
C
70V3599S166BFG8
BFG208
CABGA
C
70V3599S166DRG
DRG208
PQFP
C
6.42
22
Feb.03.20
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History:
06/02/00:
07/12/00:
07/30/01:
11/20/01:
Page 20
Page 9
Pages 2, 3 & 4
Page 11
Pages 1 & 22
Page 10
07/01/02:
Pages 1 & 5
Page 7
Page 9
Page 11
05/19/03:
01/10/06:
07/25/08:
01/19/09:
07/26/10:
Page 11
Page 22
Page 1
Page 5
Page 22
Page 9
Page 22
Page 11
Pages 13-16
10/14/14:
06/21/18:
Page 22
03/07/19:
11/05/19:
Pages 1, 22
Pages 2 - 4
Page 4
Page 23
Pages 1 - 24
Page 22
02/03/20:
Initial Public Offering
Added mux to functional block diagram
Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns
Added Industrial Temperature DC Parameters
Added date revision for pin configurations
Changed tOE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05
Replaced TM logo with ® logo
Changed AC Test Conditions Input Rise/Fall Times
Consolidated multiple devices into one datasheet
Added DCD capability for Pipelined Outputs
Clarified TBIAS and added TJN
Changed DC Electrical Parameters
Removed Clock Rise & Fall Time from AC Electrical Characteristics Table
Removed Preliminary status
Added Byte Enable SetupTime & Byte Enable Hold Time to AC Electrical Characteristics Table
Added IDT Clock Solution Table
Added green availability to features
Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = VIH to ADS, CNTEN, REPEAT = X
Added green indicator to ordering information
Corrected a typo in the DC Chars table
Removed "IDT" from orderable part number
In order to correct the header notes of the AC Elect Chars Table and align them with the Industrial temp range
values located in the table, the commercial TA header note has been removed
In order to correct the footnotes of timing diagrams, CNTEN has been removed to reconcile the
footnotes with the CNTEN logic definition found in Truth Table II - Address Counter Control
Added Tape & Reel to Ordering Information
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Added orderable part information table. Updated EOL note to obsolete status.
Updated package codes
Rotated DRG208 TQFP pin configuration to accurately reflect pin 1 orientation
Deleted IDT Clock Solution table
Rebranded as Renesas datasheet
Corrected "ns" to "MHz" in the header of the Orderable Part Information tables
6.42
23
Feb.03.20
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