70V5388S166BCI

IDT70V5388/78 3.3V 64/32K X 18 OBSOLETE PARTS SYNCHRONOUS FOURPORT™ STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ True four-ported memory cells which allow simultaneous access of the same memory location Synchronous Pipelined device – 64/32K x 18 organization Pipelined output mode allows fast 200MHz operation High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x 4 ports) LVTTL I/O interface High-speed clock to data access 3.0ns (max.) 3.3V Low operating power Interrupt flags for message passing Width and depth expansion capabilities Counter readback on address lines ◆ ◆ ◆ ◆ ◆ Counter wrap-around control – Internal mask register controls counter wrap-around – Counter-Interrupt flags to indicate wrap-around Mask register readback on address lines Global Master reset for all ports Dual Chip Enables on all ports for easy depth expansion Separate upper-word and lower-word controls on all ports 272-BGA package (27mm x 27mm 1.27mm ball pitch) and 256-BGA package (17mm x 17mm 1.0mm ball pitch) Commercial and Industrial temperature ranges JTAG boundary scan MBIST (Memory Built-In Self Test) controller Green parts available, see ordering information S OR T R F A P ED E D T N S E E N L M G O I S M S B O E O EC D W R E T N O N ◆ ◆ ◆ ◆ Port - 1 Logic Block Diagram(2) R/WP1 0 1 1/0 UBP1 CE 0P1 CE 1P1 LBP1 OEP1 I/O9P1 - I/O17P1 Port 1 I/O Control I/O0P1 - I/O8P1 TRST TMS TCK TDI CLKMBIST Addr. Read Back JTAG Controller TDO MBIST Port 1 Readback Register MRST A0P1 - A15P1(1) CNTRDP1 MKRDP1 MKLDP1 CNTINCP1 CNTLDP1 CNTRSTP1 CLK P1 MRST CNTINTP1 Port 1 Mask Register , Port 1 Address Decode Priority Decision Logic 64KX18 Memory Array Port 1 Counter/ Address Register R/WP1 CE0P1 CE1P1 CLKP1 MRST NOTE: 1. A15x is a NC for IDT70V5378. 2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks. Port 1 Interrupt Logic INTP1 5649 drw 01 OCTOBER 2008 1 ©2008 Integrated Device Technology, Inc. DSC-5649/5 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Description The IDT70V5388/78 is a high-speed 64/32Kx18 bit synchronous FourPort RAM. The memory array utilizes FourPort memory cells to allow simultaneous access of any address from all four ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register and integrated burst counters, the 70V5388/78 has been optimized for applications having unidirectional or bi-directional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT70V5388/78 provides a wide range of func- tions specially designed to facilitate system operations. These include full-boundary, maskable address counters with associated interrupts for each port, mailbox interrupt flags on each port to facilitate inter-port communications, Memory Built-In Self-Test (MBIST), JTAG support and an asynchronous Master Reset to simplify device initialization. In addition, the address lines have been set up as I/O pins, to permit the support of CNTRD (the ability to output the current value of the internal address counter on the address lines) and MKRD (the ability to output the current value of the counter mask register). For specific details on the device operation, please refer to the Functional Description and subsequent explanatory sections, beginning on page 21. 2 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Pin Configuration (4) 70V5388/78BG BG-272(2) 272-Pin BGA Top View(3) 09/25/02 1 2 3 4 5 6 7 8 9 A LB P1 I/O17 P2 I/O15 P2 I/O13 P2 I/O11 P2 I/O9 P2 I/O16 P1 I/O14 P1 B VDD UB P1 I/O16 P2 I/O14 P2 I/O12 P2 I/O10 P2 I/O17 P1 C A14 P1 A15(1) P1 CE1 P1 CE0 P1 R/W P1 I/O15 P1 D VSS A12 P1 A13 P1 OE P1 VDD VSS E A10 P1 A11 P1 F A7 P1 A8 P1 A9 P1 CNTINT P1 CNTINT P4 G VSS A5 P1 A6 P1 CNTINC P1 CNTINC P4 H A3 P1 A4 P1 J VDD A1 P1 A2 P1 VDD GND K A0 P1 INT P1 CNTRST P1 CLK P1 GND L A0 P2 INT P2 CNTRST VSS P2 GND M VDD A1 P2 CLK P2 GND N A3 P2 A4 P2 P VSS A5 P2 A6 P2 R A7 P2 A8 P2 A9 P2 T A10 P2 A11 P2 U VSS A12 P2 A13 P2 OE P2 VDD VSS VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD OE P3 V A14 P2 A15(1) P2 CE1 P2 CE0 P2 R/W P2 I/O6 P2 VSS VSS I/O0 P2 TRST NC I/O0 P3 VSS VSS I/O6 P3 R/W P3 W VDD UB P2 I/O7 P1 I/O5 P1 I/O3 P1 I/O1 P1 I/O8 P2 I/O4 P2 I/O2 P2 MRST CLKMBIST I/O2 P3 I/O4 P3 I/O8 P3 I/O1 P4 Y LB P2 I/O8 P1 I/O6 P1 I/O4 P1 I/O2 P1 I/O0 P1 I/O7 P2 I/O5 P2 I/O3 P2 I/O1 P2 I/O3 P3 I/O5 P3 I/O7 P3 I/O0 P4 1 2 3 4 5 6 7 8 9 . 10 11 12 13 14 15 16 17 18 19 20 I/O12 P1 I/O10 P1 I/O10 P4 I/O12 P4 I/O14 P4 I/O16 P4 I/O9 P3 I/O11 P3 I/O13 P3 I/O15 P3 I/O17 P3 LB P4 A I/O13 P1 I/O11 P1 TMS TDI I/O11 P4 I/O13 P4 I/O17 P4 I/O10 P3 I/O12 P3 I/O14 P3 I/O16 P3 UB P4 VDD B VSS VSS I/O9 P1 TCK TDO I/O9 P4 VSS VSS I/O15 P4 R/W P4 CE0 P4 CE1 P4 A15(1) P4 A14 P4 C VSS VDD VDD VSS VSS VDD VDD VSS VSS VDD OE P4 A13 P4 A12 P4 VSS D A11 P4 A10 P4 E A9 P4 A8 P4 A7 P4 F A6 P4 A5 P4 VSS G A4 P4 A3 P4 H A1 P4 VDD J CLK CNTRST INT P4 P4 P4 A0 P4 K CNTRST INT P3 P3 A0 P3 L A1 P3 VDD M CNTLD MKLD P3 P3 A4 P3 A3 P3 N CNTINC P2 CNTINC P3 A6 P3 A5 P3 VSS P CNTINT P2 CNTINT P3 A9 P3 A8 P3 A7 P3 R A11 P3 A10 P3 T A13 P3 A12 P3 VSS U CE0 P3 CE1 P3 A15(1) P3 A14 P3 V I/O3 P4 I/O5 P4 I/O7 P4 UB P3 VDD W I/O2 P4 I/O4 P4 I/O6 P4 I/O8 P4 LB P3 Y MKRD CNTRD P1 P1 CNTRD MKRD P4 P4 MKLD CNTLD P1 P1 A2 P2 CNTLD MKLD P4 P4 (5) GND (5) GND (5) GND (5) GND (5) GND (5) GND (5) GND (5) (5) GND (5) GND (5) GND (5) GND (5) VDD (5) (5) VSS CLK P3 (5) GND MKLD CNTLD P2 P2 A2 P4 A2 P3 CNTRD MKRD P3 P3 MKRD CNTRD P2 P2 I/O1 P3 10 11 12 13 14 15 16 17 18 19 20 5649 drw 03 NOTES: 1. A15x is a NC for IDT70V5378. 2. This package code is used to reference the package diagram. 3. This text does not indicate orientation of the actual part marking. 4. Package body is approximately 27mm x 27mm x 2.33mm, with 1.27mm ball-pitch. 5. Central balls are for thermal dissipation only. They are connected to device VSS. 3 6.42 , IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Pin Configuration Industrial and Commercial Temperature Ranges (2) 70V5388/78BC BC-256(3) 256-Pin BGA(4) Top View 09/25/02 1 2 3 4 5 6 7 8 A R/W OE LB I/O16 I/O13 I/O9 I/O14 I/O10 I/O9 P1 P1 P1 P2 P2 P2 P1 P1 P4 B A15(1) CE1 UB I/O17 P1 P1 P2 P2 C A14 A13 CE0 I/O15 I/O12 P1 P1 P1 P2 P2 D A10 A12 A11 A9 I/O11 P1 P1 P1 P1 P2 E A7 A8 A6 A5 P1 P1 P1 P1 F A3 A4 A2 A1 P1 P1 P1 P1 G CLK A0 P1 P1 H VSS CNTLD CNTRST CNTINT INT MKLD P1 P1 J CLK CNTRST INT K P1 P2 P1 P2 CNTRD CNTINC P1 P2 P1 P1 I/O14 I/O10 I/O15 P1 I/O17 I/O12 P1 P1 I/O16 I/O13 P1 P1 10 11 12 13 14 15 16 I/O12 I/O16 P4 P4 UB CE1 P3 P3 P4 P4 I/O15 I/O17 I/O16 LB R/W CE0 P4 P3 P4 P4 P4 I/O9 I/O11 A15(1) A14 P1 TMS TDO TCK P4 P3 I/O14 OE P4 P4 P3 P3 P4 P4 P4 I/O10 I/O14 I/O9 I/O13 A11 A12 A13 P4 P4 P3 P3 P4 P4 P4 A6 A7 A8 A10 A9 P4 P4 P4 P4 P4 A1 A2 A3 A5 A4 P4 P4 P4 P4 P4 CNTLD CNTINC CNTRD A0 CLK P4 P4 P4 I/O15 I/O10 VDD VDD VDD VDD VDD VDD VSS VSS VSS VDD VDD VDD VSS VSS VSS VSS VSS VSS P1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VSS CNTRD MKRD CNTINC CNTLD MKLD P3 I/O13 I/O17 I/O12 P1 VDD P1 I/O11 I/O11 TDI VDD VDD CNTINT MKRD P2 P2 9 VSS P4 CNTRST MKRD P4 VSS P4 CNTRST P3 P4 INT CNTINT MKLD P4 P4 P3 P3 CNTLD CNTINC MKRD A0 CNTRD P3 P3 P3 P3 A1 A3 A4 A2 P3 P3 P3 P3 A5 A7 A8 A6 P3 P3 P3 P3 P2 P2 P2 P2 L A3 A4 A2 A1 A0 P2 P2 P2 P2 P2 M A8 A9 A7 A6 A5 P2 P2 P2 P2 P2 VDD VDD VDD VDD VDD VDD VDD N A11 A12 A10 I/O5 I/O1 I/O6 I/O2 I/O7 I/O2 A9 A11 A12 A10 P2 P2 P1 P1 P2 P2 TRST I/O3 P2 P3 P3 P4 P3 P3 P3 P3 P A13 A14 R/W I/O7 I/O2 I/O7 I/O3 P2 P2 P2 P1 P1 P2 P2 R A15(1) CE1 UB I/O8 I/O4 I/O0 P2 P2 P1 P1 P1 T CE0 OE LB I/O6 I/O3 I/O8 P2 P2 P2 P1 P1 P2 3 4 P2 1 2 5 6 CLKMBIST VSS VDD VDD MRST I/O0 I/O4 I/O8 I/O3 I/O6 CE0 A14 A13 P3 P3 P3 P4 P4 P3 P3 P3 I/O5 I/O1 I/O2 I/O6 I/O1 I/O5 I/O7 UB CE1 A15(1) P2 P2 P3 P3 P4 P4 P4 P3 P3 P3 I/O4 I/O0 I/O1 I/O5 I/O0 I/O4 I/O8 LB OE R/W P2 P2 P3 P3 P4 P4 P4 P3 P3 P3 7 8 9 10 11 D E F G H CLK P2 VSS C VSS P3 P3 B P4 INT CNTINT MKLD P3 A J K L M N 12 13 14 15 16 5649 drw 04 NOTES: 1. A15x is a NC for IDT70V5378. 2. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 3. This package code is used to reference the package diagram. 4. This text does not indicate orientation of the actual part-marking. 4 P R T IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Pin Definitions Port 1 A0P1 - A 15P1(1) Port 2 A0P2 - A15P2(1) Port 3 A0P3 - A 15P3(1) Port 4 Description A0P4 - A15P4(1) Address Inputs. In the CNTRD and MKRD operations, these pins serve as outputs for the internal address counter and the internal counter mask register respectively. I/O0P1 - I/O17P1 I/O0P2 - I/O17P2 I/O0P3 - I/017P3 I/O0P4 - I/O17P4 Data Bus Input/Output. CLK P1 CLKP2 CLKP3 CLKP4 Clock Input. The maximum clock input rate is fMAX. The clock signal can be free running or strobed depending on system requirements. Master Reset Input. MRST is an asycnchronous input, and affects all ports. It must be asserted LOW (MRST = V IL) at initial power-up. Master Reset sets the internal value of all address counters to zero, and sets the counter mask registers for each port to 'unmasked'. It also resets the output flags for the mailboxes and the counter interrupts (INT = CNTINT = VIH) and deselects all registered control signals. MRST Chip Enable Inputs. To activate any port, both signals must be asserted to their active states (CE0 = V IL, CE 1 = VIH). A given port is disabled if either chip enable is deasserted (CE0 = V IH and/or CE 1 = VIL). CE0P1, CE1P1 CE0P2, CE1P2 CE0P3, CE 1P3 CE0P4, CE 1P4 R/WPI R/WP2 R/WP3 R/WP4 Read/Write Enable Input. This signal is asserted LOW (R/W = VIL) in order to write to the FourPort memory array, and it is asserted HIGH (R/W = VIH) in order to read from the array. LBP1 LBP2 LBP3 LBP4 Lower Byte Select Input (I/O0 - I/O8). Asserting this signal LOW (LB = VIL) enables read/write operations to the lower byte. For read operations, this signal is used in conjunction with OE in order to drive output data on the lower byte of the data bus. UBP1 UBP2 UBP3 UBP4 Upper Byte Select Input (I/O9 - I/O17). Asserting this signal LOW (LB = VIL) enables read/write operations to the upper byte. For read operations, this signal is used in conjunction with OE in order to drive output data on the upper byte of the data bus. OEP1 OEP2 OEP3 OEP4 Output Enable Input. Asserting this signal LOW (OE = VIL) enables the device to drive data on the I/O pins during read operation. OE is an asychronous input. CNTLDP1 CNTLDP2 CNTLDP3 CNTLDP4 CNTINCP1 CNTINCP2 CNTINCP3 CNTINCP4 CNTRDP1 CNTRDP2 CNTRDP3 CNTRDP4 CNTRSTP1 CNTRSTP2 CNTRSTP3 CNTRSTP4 Counter Reset Input. Asserting this signal LOW (CNTRST = VIL) resets the address counter for that port to zero. CNTINTP1 CNTINTP2 CNTINTP3 CNTINTP4 Counter Interrupt Flag Output. This signal is asserted LOW (CNTINT = VIL) when the internal address counter for that port 'wraps around' from max address [(the counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle)] to address min. as the result of counter increment (CNTINT = VIL). The signal goes LOW for one clock cycle, then automatically resets. Counter Load Input. Asserting this signal LOW (CNTLD = VIL) loads the address on the address lines (A 0 - A15(1)) into the internal address counter for that port. Counter Increment Input. Asserting this signal LOW (CNTINC = VIL) increments the internal address counter for that port on each rising edge of the clock signal. The counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle). Counter Readback Input. When asserted LOW (CNTRD = V IL) causes that port to output the value of its internal address counter on the address lines for that port. Counter readback is independent of the chip enables for that port. If the port is activated (CE0 = VIL and CE 1 = V IH), during the counter readback operation, then the data bus will output the data associated with that readback address in the FourPort memory array (assuming that the byte enables and output enables are also asserted). Truth Table III indicates the required states for all other counter controls during this operation. The specific operation and timing of this funcion is described in detail in the text. 5649 tbl 01 5 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Pin Definitions (con't.) Port 1 Port 2 Port 3 Port 4 Description Counter Mask Register Load Input. Asserting this signal LOW (MKLD = VIL) loads the address on the address lines (A0 - A15(1)) into the counter mask register for that port. Counter mask register operations are described in detail in the text. MKLDP1 MKLDP2 MKLDP3 MKLDP4 MKRDP1 MKRDP2 MKRDP3 MKRDP4 Counter Mask Register Readback Input. Asserting this signal LOW (MKRD = VIL) causes that port to output the value of its internal counter mask register on the address lines (A0 - A15(1)) for that port. Address Counter and Counter-Mask Operational Table indicates the required states for all other counter controls during this operation. Counter mask register readback is independent of the chip enables for that port. If the port is activated (CE0 = VIL and CE1 = VIH) during the counter mask register readback operation, then the data bus will output the data associated with that address in the FourPort memory array ( assuming that the byte enables and output enables are also asserted). The specific operation and timing of this function is described in detail in the text. INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output. The FourPort is equipped with mailbox functions: each port has a specific address wthin the memory array which, when written by any of the other ports, will generate an interrupt flag to that port. The port clears its interrupt by reading that address. The memory location is a valid address for data storage: a full 18-bit word can be stored for recall by the target port or any other port. The mailbox functions and associated interrupts are described in detail in the text. TMS JTAG Input: Test Mode Select TRST JTAG Input: Test Mode Reset (Intialize TAP Controller and reset the MBIST Controller) TCK JTAG Input: Test Clock TDI JTAG Input: Test Data Input (serial) TDO JTAG Output: Test Data Output (serial) CLKMBIST MBIST Input: MBIST Clock GND Thermal Grounds (should be treated like V SS) VDD Core Power Supply (3.3V) VSS Electrical Grounds (0V) 5649 tbl 02 NOTE: 1. A15x is a NC for IDT70V5378. 6 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control(1,2,3) OE CLK CE0 CE 1 UB LB R/W Upper Byte I/O9-17 Lower Byte I/O0-8 X ↑ H X X X X High-Z High-Z Deselected–Power Down X ↑ X L X X X High-Z High-Z Deselected–Power Down X ↑ L H H H X High-Z High-Z All Bytes Deselected X ↑ L H H L L High-Z DIN Write to Lower Byte Only X ↑ L H L H L DIN High-Z Write to Upper Byte Only X ↑ L H L L L DIN DIN L ↑ L H H L H High-Z DOUT Read Lower Byte Only L ↑ L H L H H DOUT High-Z Read Upper Byte Only L ↑ L H L L H DOUT DOUT Read Both Bytes H ↑ X X X X X High-Z High-Z Outputs Disabled MODE Write to Both Bytes 5649 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CNTLD, CNTINC, CNTRST = VIH. 3. OE is an asynchronous input signal. Truth Table II—Address Counter & Mask Control(1,2) External Address Previous Internal Address Internal Address Used CLK CNTLD CNTINC CNTRST MKLD I/O X X 0 ↑ X X L(3) X DI/O(0) Counter Reset to Address 0 An Ap Ap ↑ X X H L DI/O(p) Counter disabled (Ap reused) An X An An Ap Ap X Ap (5) Ap + 1 (3) MODE ↑ L X H H DI/O (n) External Address Used ↑ H H H H DI/O(p) External Address Blocked—Counter disabled (Ap reused) ↑ H (4) L H H (5) DI/O(p+1) Counter Enabled—Internal Address generation 5649 tbl 04 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, LB, UB and OE. 3. CNTLD and CNTRST are independent of all other memory control signals including CE0, CE1 and LB, UB. 4. The address counter advances if CNTINC = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, LB, UB. 5. The counter will increment as defined by the counter mask register for that port (default mode is to advance one address on each clock cycle). 7 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Address Counter and Counter-Mask Control Operational Table (Any Port)(1,2) CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD Mode Operation X L X X X X X X MasterReset Counter/Address Register Reset and Mask Register Set (resets chip as per reset state definition) ↑ H L X X X X X Reset Counter/Address Register Reset ↑ H H L X X X X Load Load of Address Lines into Mask Register ↑ H H H L X X X Load Load of Address Lines into Counter/Address Register ↑ H H H H L X X ↑ H X X X X L X Readback ↑ H X X X X H L Readback Readback Mask Register on Address Lines ↑ H H H(3) H H X X Hold Counter Hold Increment Counter Increment Readback Counter on Address Lines 5649 tbl 05 NOTES: 1. "X" = "don't care", "H" = VIH, "L" = VIL. 2. Counter operation and mask register operation is independent of Chip Enable. 3. MKLD = VIL will also hold the counter. Please refer to Truth Table II. Recommended DC Operating Conditions Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature GND VDD 0OC to +70OC 0V 3.3V + 150mV -40OC to +85OC 0V 3.3V + 150mV Symbol VDD VSS 5649 tbl 06 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Parameter Supply Voltage Ground VIH Input High Voltage (Address, Control & I/O Inputs) VIL Input Low Voltage Min. Typ. Max. Unit 3.15 3.3 3.45 V 0 0 0 2.0 ____ -0.3(1) ____ VDD + 150mV V (2) 0.8 V V 5649 tbl 07 NOTES: 1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed. 2. VTERM must not exceed VDD + 150mV. 8 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Capacitance(1) Absolute Maximum Ratings(1) Symbol Commercial & Industrial Unit Terminal Voltage with Respect to GND -0.5 to +4.6 V TBIAS(3) Temperature Under Bias -55 to +125 o TSTG Storage Temperature -65 to +150 o C TJN Junction Temperature +150 o C IOUT DC Output Current VTERM(2) Rating (TA = +25°C, F = 1.0MHZ) Symbol CIN Input Capacitance (3) 50 COUT C Parameter Output Capacitance Conditions(2) Max. Unit VIN = 3dV 8 pF VOUT = 3dV 10.5 pF 5649 tbl 09 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. mA 5623 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV. 3. Ambient Temperature under DC Bias. No AC conditions. Chip Deselected. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV) 70V5388/78S Symbol |ILI| |ILI| Parameter Test Conditions (1) Input Leakage Current (1,2) JTAG Input Leakage Current (1) Min. Max. Unit VDD = Max., VIN = 0V to V DD ___ 10 µA VDD = Max., VIN = 0V to V DD ___ 30 µA |ILO| Output Leakage Current VOUT = 0V to V DD, Outputs in tri-state mode ___ 10 µA VOL Output Low Voltage IOL = +4mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = -4mA, VDD = Min. 2.4 ___ V 5649 tbl 10 NOTE: 1. At VDD < 2.0V leakages are undefined. 2. Applicable only for TMS, TDI and TRST inputs. 9 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV) 70V5388/78S200 70V5388/78S166 70V5388/78S133 70V5388/78S100 Com'l Only Com'l Com'l Com'l & Ind & Ind & Ind Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Version Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Dynamic Operating Current (All Ports Active) CE1 = CE2 = CE3 = CE4(5) = VIL, Outputs Disabled, f = fMAX(1) COM'L S 405 470 340 395 275 320 205 240 IND S ___ ___ 340 400 275 325 205 245 Standby Current (All Ports - TTL Level Inputs) CE1 = CE2 = CE3 = CE4(5) = VIH, Outputs Disabled, f = fMAX(1) COM'L S 195 225 160 190 130 155 100 120 IND S ___ ___ 160 195 130 160 100 125 Standby Current (One Port - TTL Level Inputs) CEA = VIL and CEB = CEC = CED = VIH(5) Active Port, Outputs Disabled, f=fMAX(1) COM'L S 250 290 210 240 170 195 130 150 IND S ___ ___ 210 245 170 200 130 155 COM'L S 1.5 15 1.5 15 1.5 15 1.5 15 IND S ___ ___ 1.5 15 1.5 15 1.5 15 COM'L S 250 290 210 240 170 195 130 150 IND S ___ ___ 210 245 170 200 130 155 Full Standby Current (All All Ports Outputs Disabled, Ports - CMOS CE(5) > VDD - 0.2V, VIN > VDD - 0.2V Level Inputs) or VIN < 0.2V, f = 0(2) Full Standby Current (One Port - CMOS Level Inputs) CEA < 0.2V and CEB = CEC = CED > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V Active Port, Outputs Disabled, f = fMAX(1) Unit mA mA mA mA mA 5649 tbl 11 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Parameters are identical for all ports. 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V "X" represents indicator for appropriate port. 10 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ - 3.3V) Input Pulse Levels (Address & Controls) GND to 3.0V Input Pulse Levels (I/Os) GND to 3.0V Input Rise/Fall Times 2ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figure 1 5649 tbl 12 50Ω 50Ω DATAOUT 1.5V 10pF (Tester) 5649 drw 05 Figure 1. AC Output Test Load *(For tLZ, tHZ, tWZ, tOW) 7 6 ∆ tCD 5 (Typical, ns) 4 3 2 1 0 0 20 40 60 80 100 120 ∆ Capacitance (pF) from AC Test Load 140 5649 drw 07 Figure 2. Typical Output Derating (Lumped Capacitive Load). 11 6.42 160 , IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C) Symbol Parameter 70V5388/78S200 Com'l Only 70V5388/78S166 Com'l & Ind 70V5388/78S133 Com'l & Ind 70V5388/78S100 Com'l & Ind Min. Max. Min. Max. Min. Max. Min. Max. Unit ____ 200 ____ 166 ____ 133 ____ 100 MHz ns fMAX2 Maximum Frequency tCYC2 Clock Cycle Time 5 ____ 6 ____ 7.5 ____ 10 ____ tCH2 Clock HIGH Time 2.0 ____ 2.1 ____ 2.6 ____ 4 ____ ns tCL2 Clock LOW Time 2.0 ____ 2.1 ____ 2.6 ____ 4 ____ ns tSA Address Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns tSC Chip Enable Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns tHC Chip Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns tSW R/W Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns tHW R/W Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns tSD Input Data Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns tHD Input Data Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns tSB Byte Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns tHB Byte Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns ns CNTLD Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ tHCLD CNTLD Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns tSCINC CNTINC Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns tHCINC CNTINC Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns CNTRST Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns CNTRST Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns CNTRD Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns CNTRD Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns MKLD Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ ns MKLD Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns ns tSCLD tSCRST tHCRST tSCRD tHCRD tSMLD tHMLD tSMRD MKRD Setup Time 1.5 ____ 1.7 ____ 1.8 ____ 2 ____ tHMRD MKRD Hold Time 0.5 ____ 0.5 ____ 0.5 ____ 0.7 ____ ns tOE Output Enable to Data Valid ____ 4.0 ____ 4.0 ____ 4.2 ____ 5 ns 1 ____ 1 ____ 1 ____ 1 ____ ns tOLZ (1,5) OE to LOW-Z tOHZ OE to HIGH-Z (1,5) 1 3.4 1 3.6 1 4.2 1 4.5 ns 3.6 ns tCD2 Clock to Data Valid ____ 3.0 ____ 3.2 ____ 3.4 ____ tCA2 Clock to Counter Address Readback Valid ____ 3.4 ____ 3.6 ____ 4.2 ____ 5 ns tCM2 Clock to Mask Register Readback Valid ____ 3.4 ____ 3.6 ____ 4.2 ____ 5 ns tDC Data Output Hold After Clock HIGH 1 ____ 1 ____ 1 ____ 1 ____ ns tCKHZ (1,2,5) Clock HIGH to Output HIGH-Z 1 3 1 3 1 3 1 3 ns tCKLZ Clock HIGH to Output LOW-Z 1 ____ 1 ____ 1 ____ 1 ____ (1,2,5) ns 5649 tbl 13a 12 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C) Symbol Parameter 70V5388/78S200 Com'l Only 70V5388/78S166 Com'l & Ind 70V5388/78S133 Com'l & Ind 70V5388/78S100 Com'l & Ind Min. Max. Min. Max. Min. Max. Min. Max. Unit Interrupt Timing tSINT Clock to INT Set Time ____ 5 ____ 6 ____ 7.5 ____ 10 ns tRINT Clock to INT Reset Time ____ 5 ____ 6 ____ 7.5 ____ 10 ns tSCINT Clock to CNTINT Set Time ____ 5 ____ 6 ____ 7.5 ____ 10 ns tRCINT Clock to CNTINT Reset Time ____ 5 ____ 6 ____ 7.5 ____ 10 ns ns Master Reset Timing tRS Master Reset Pulse Width 7.5 ____ 7.5 ____ 7.5 ____ 10 ____ tRSR Master Reset Recovery Time 7.5 ____ 7.5 ____ 7.5 ____ 10 ____ ns tROF Master Reset to Output Flags Reset Time ____ 6.5 ____ 6.5 ____ 6.5 ____ 8 ns Clock-to-Clock Setup Time 4.5 ____ 5 ____ 6.5 ____ 9 ____ ns fJTAG Maximum JTAG TAP Controller Frequency ____ 10 ____ 10 ____ 10 ____ 10 MHz tTCYC TCK Clock Cycle Time 100 ____ 100 ____ 100 ____ 100 ____ ns tTH TCK Clock High Time 40 ____ 40 ____ 40 ____ 40 ____ ns tTL TCK Clock Low Time 40 ____ 40 ____ 40 ____ 40 ____ ns tJS JTAG Setup 20 ____ 20 ____ 20 ____ 20 ____ ns tJH JTAG Hold 20 ____ 20 ____ 20 ____ 20 ____ ns tJCD TCK Clock Low to TDO Valid (JTAG Data Output) ____ 20 ____ 20 ____ 20 ____ 20 ns tJDC TCK Clock Low to TDO Invalid (JTAG Data Output Hold) 0 fBIST Maximum CLKMBIST Frequency tBH Port to Port Delays tCCS(3) (4) JTAG Timing ____ 0 ____ 0 ____ 0 ____ ns ____ 200 ____ 166 ____ 133 ____ 100 MHz CLKMBIST High Time 2 ____ 2.5 ____ 3 ____ 4 ____ ns tBL CLKMBIST Low Time 2 ____ 2.5 ____ 3 ____ 4 ____ ns tJRST JTAG Reset 50 ____ 50 ____ 50 ____ 50 ____ ns tJRSR JTAG Reset Recovery 50 ____ 50 ____ 50 ____ 50 ____ ns 5649 tbl 13b NOTES: 1. Guaranteed by design (not production tested). 2. Valid for both data and address outputs. 3. This parameter defines the time necessary for one port to complete a write and have valid data available at that address for access from the other port(s). Attempting to read data before tCCS has elapsed will result in the output of indeterminate data. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 5. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 1). 13 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Switching Waveforms Timing Waveform of Read Cycle(2) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC tHC (3) CE1 tSB tHB tSB LB, UB R/W ADDRESS tSW tHW tSA tHA (4) An An + 1 (1 Latency) An + 2 An + 3 tDC tCD2 DATAOUT Qn tCKLZ OE tHB (5) Qn + 1 Qn + 2 (5) (1) tOHZ tOLZ (1) tOE NOTES: 1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 5649 drw 08 2. CNTLD = VIL, CNTINC and CNTRST = VIH. 3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, LB, UB = VIH following the next rising edge of the clock. Refer to Truth Table I. 4. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If LB, UB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). , Timing Waveform of a Multi-Device Read(1,2) tCH2 tCYC2 tCL2 CLK tSA tHA A0 ADDRESS(B1) tSC tHC CE0(B1) tSC tHC tCD2 tCD2 Q0 DATAOUT(B1) tCKHZ A1 tSC tCKHZ A6 A5 A4 A3 A2 tSC CE0(B2) Q3 tCKLZ tDC tHA A0 ADDRESS(B2) tCD2 Q1 tDC tSA A6 A5 A4 A3 A2 A1 tHC tHC tCD2 tCKHZ tCD2 , DATAOUT(B2) Q4 Q2 tCKLZ NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V5388/78 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. LB, UB, OE, and CNTLD = VIL; CE1(B1), CE1(B2), R/W, CNTINC, and CNTRST = VIH. 14 tCKLZ 5649 drw 09 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Port A Write to Port B Read(1,2,4) CLK"A" tSW tHW tSA tHA R/W"A" ADDRESS"A" NO MATCH MATCH tSD DATAIN"A" tHD VALID tCCS(3) CLK"B" tCD2 R/W"B" ADDRESS"B" tSW tHW tSA tHA NO MATCH MATCH DATAOUT"B" VALID tDC 5649 drw 10 NOTES: 1. CE0, LB, UB, and CNTLD = VIL; CE1, CNTINC, CNTRST, MRST, MKLD, MKRD and CNTRD = VIH. 2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to. 3. If tCCS < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCCS + 2 tCYC2 + tCD2). If tCCS > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCCS + tCYC2 + tCD2). 4. All timing is the same for all ports. Port "A" may be any port. Port "B" is any other port on the device. Timing Waveform of Read-to-Write-to-Read (OE = VIL)(2) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 LB, UB tSW tHW R/W (3) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 3 An + 2 An + 4 tSD tHD DATAIN Dn + 2 (1) tCD2 tCD2 tCKHZ Qn DATAOUT READ Qn + 3 tCKLZ NOP (4) WRITE READ 5649 drw 11 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CNTLD = VIL; CNTINC, and CNTRST, MRST, MKLD, MKRD and CNTRD = VIH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 15 6.42 , IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read-to-Write-to-Read ( OE Controlled)(2) tCH2 tCYC2 tCL2 CLK CE0 tSC tHC tSB tHB CE1 LB, UB tSW tHW R/W (3) ADDRESS tSW tHW An tSA tHA An +1 An + 2 tSD DATAIN Dn + 2 tCD2 (1) Qn DATAOUT An + 4 An + 3 An + 5 tHD Dn + 3 tCD2 (4) Qn + 4 tCKLZ tOHZ OE READ WRITE READ 5649 drw 12 , NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CNTLD = VIL; CNTINC, CNTRST, MRST, MKLD, MKRD and CNTRD = VIH. 3. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows. Timing Waveform of Read with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSCLD tHCLD CNTLD tSCLD tHCLD CNTINC tSCLD tHCLD tCD2 DATAOUT Qx - 1(2) , Qn + 2(2) Qn + 1 Qn Qx Qn + 3 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 5649 drw 13 NOTES: 1. CE0, LB and UB = VIL; CE1, CNTRST, MRST, MKLD, MKRD and CNTRD = VIH. 2. If there is no address change via CNTLD = VIL (loading a new address) or CNTINC = VIL (advancing the address), i.e. CNTLD = VIH and CNTINC = VIH, then the data output remains constant for subsequent clocks. 16 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 An + 4 An + 3 tSCLD tHCLD CNTLD tSCINC tHCINC CNTINC tSD tHD Dn + 1 Dn DATAIN WRITE EXTERNAL ADDRESS Dn + 1 Dn + 4 Dn + 3 Dn + 2 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 5649 drw 14 Timing Waveform of Counter Reset(2) tCH2 tCYC2 tCL2 CLK tSA tHA (4) An ADDRESS INTERNAL(3) ADDRESS Ax A1 A0 An + 2 An + 1 An An + 1 tSW tHW R/W CNTLD tSCLD tHCLD CNTINC tSCRST tHCRST CNTRST tSCINC tHCINC tSD tHD D0 DATAIN (5) Q1 Q0 DATAOUT EXECUTE CNTRST (6) WRITE A0 READ A0 READ A1 READ ADDRESS n Qn READ ADDRESS n+1 5649 drw 15 NOTES: 1. CE0, LB, UB, and R/W = VIL; CE1 and CNTRST, MRST, MKLD, MKRD, and CNTRD = vIH. 2. CE0, LB, UB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when CNTLD = VIL and equals the counter value when CNTLD = VIH. 4. Addresses do not have to be accessed sequentially since CNTLD = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during CNTRST operation. A READ or WRITE cycle may be coincidental with the counter CNTRST cycle: Address 0000h will be accessed. Extra cycles are shown here simply for clarification. For more information on CNTRST function refer to Truth Table II. 7. CNTINC = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 17 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Master Reset(1) tCYC2 tCH2 tCL2 CLK tRS MRST tROF ALL ADDRESS/ DATA LINES tRSR tS(2) ALL OTHER INPUTS INACTIVE ACTIVE CNTINT INT 5649 drw 16 NOTES: 1. Master Reset will reset the device. For JTAG and MBIST reset please refer to the JTAG Timing specification. 2. tS is the set-up time required for all input control signals. 18 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Load and Read Address Counter(1,2,3) tCYC2 tCH2 tCL2 (2) (3) CLK tSA A0 - A15 tCA2 tCKLZ tHA tCKHZ An+2(4) An tSCLD tHCLD CNTLD CNTINC tSCINC tHCINC tHCRD tSCRD CNTRD INTERNAL ADDRESS An+1 An tCD2 DATAOUT Qx Qx-1 LOAD EXTERNAL ADDRESS An+2 An+2 An+2 , tDC Qn+1 Qn Qn+2 Qn+2 Qn+2 READ INTERNAL ADDRESS READ DATA WITH COUNTER 5649 drw 17 NOTES: 1. CE0, OE, LB and UB = VIL; CE1, R/W, CNTRST, MRST, MKLD and MKRD = VIH. 2. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle. 3. Address in input mode. Host can drive address bus after tCKHZ. 4. This is the value of the address counter being read out on the address lines. Timing Waveform of Load and Read Mask Register(1,2,3,4) tCYC2 tCH2 tCL2 (2) (1) CLK tSA A0 - A15 tHA tCKLZ tCA2 tCKHZ An(4) An tSMLD tHMLD MKLD tSMRD tHMLD MKRD MASK INTERNAL VALUE An An An An An An READ MASK-REGISTER VALUE LOAD MASK REGISTER VALUE 5649 drw 18 NOTES: 1. Address in output mode. Host must not be driving address bus after time tCKLZ in next clock cycle. 2. Address in input mode. Host can drive address bus after tCKHZ. 3. CE0, OE, LB and UB = VIL; CE1, R/W, CNTRST, MRST, CNTLD, CNTRD and CNTINC = VIH. 4. This is the value of the mask register being read out on the address lines. 19 6.42 , IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Counter Interrupt(1,3) tCYC2 tCH2 tCL2 CLK EXTERNAL ADDRESS 007Fh tSMLD xx7Dh tHMLD MKLD tSCLD tHCLD CNTLD tSCINC tHCINC CNTINC COUNTER INTERNAL ADDRESS An xx7Eh xx7Dh xx7Fh xx00h xx00h , tRCINT tSCINT (2) CNTINT 5649 drw 19 Timing Waveform of Mailbox Interrupt Timing(4,6) tCYC2 tCH2 tCL2 CLKP1 tSA tHA PORT-1 ADDRESS INTP2 FFFE An (5) An+1 An+2 An+3 tSINT (7) tRINT tCYC2 tCH2 tCL2 CLKP2 tSA tHA PORT-2 ADDRESS Am Am+1 FFFE (5) Am+3 Am+4 5649 drw 20 , NOTES: 1. CE0, OE, LB and UB = VIL; CE1, R/W, CNTRST, MRST, CNTRD and MKRD = VIH. 2. CNTINT is always driven. 3. CNTINT goes LOW as the counter address increments (via CNTINC = VIL) past the maximum value programmed into the mask register and 'wraps around' to xx00h CNTINT stays LOW for one cycle, then resets. In this example, the mask register was programmed at xx7Fh ('x' indicates "Don't Care"). The Counter Mask Register operations are detailed on page 24. 4. CNTRST, MRST, CNTRD CNTINC , MKRD and MKLD = VIH. The mailbox interrupt circuitry relies on the state of the chip enables, the read/write signal, and the address location to generate or clear interrupts as appropriate - other control signals such as OE, LB and UB are "Don't Care". Please refer to Truth Table III (page 22) for further explanation. 5. Address FFFEh is the mailbox location for Port 2 of IDT70V5388. Refer to Truth Table III for mailbox location of other Ports (page 22). 6. Port 1 is configured for a write operation (setting the interrupt) in this example, and Port 2 is configured for a read operation (clearing the interrupt). Ports 1 and 2 are used for an example: any port can set an interrupt to any other port per the operations in Truth Table III (page 22). 7. The interrupt flag is always set with respect to the rising edge of the writing port's clock, and cleared with respect to the rising edge of the reading port's clock. 20 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT70V5388/78 provides a true synchronous FourPort Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal and the duration of the R/W input signal. This is done in order to offer the fastest possible cycle times and highest data throughput. At 200 MHz, the device supports a cycle time of 5 ns, and provides a pipelined data output of 3.0 ns from clock edge to data valid. Four ports operating at 200 MHz, each with a bus width of 18 bits, results in a data throughput rate of nearly 14 Gbps. As a true synchronous device, the IDT70V5388/78 provides the flexibility to clock each port independently: the ports may run at different frequencies and/or out of synchronization with each other. As a true FourPort device, the IDT70V5388/78 is capable of performing simultaneous reads from all ports on the same address location. Care should be taken when attempting to write and read address locations simultaneously: the timing diagrams depict the critical parameter tCCS, which determines the amount of time needed to ensure that the write has successfully been completed and so valid data is available for output. Violation of tCCS may produce indeterminate data for the read. Two or more ports attempting to write the same address location simultaneously will result in indeterminate data recorded at that address. Each port is equipped with dual chip enables, CE0 and CE1. A HIGH on CE0 or a LOW on CE1 for one clock cycle on any port will power down the internal circuitry on that port in order to reduce static power consumption. The multiple chip enables also allow easier banking of multiple IDT70V5388/78s for depth expansion configurations. One cycle is required with chip enables reasserted to reactivate the outputs. Depth and Width Expansion The IDT70V5388/78 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V5388/78 can also be used in applications requiring expanded width, as indicated in Figure 3. Through combining the control signals, the devices can be grouped as necessary to accommodate applications requiring 36-bits or wider. A16/A15(1) IDT70V5388/78 CE0 CE1 IDT70V5388/78 CE1 VDD VDD Control Inputs Control Inputs IDT70V5388/78 CE0 IDT70V5388/78 CE1 CE1 CE0 CE0 Control Inputs Control Inputs UB, LB R/W, OE, CLK, CNTLD, CNTRST, CNTINC 5649 drw 21 Figure 3. Depth and Width Expansion with IDT70V5388/78 NOTE: 1. A16 is for IDT70V5388, A15 is for IDT70V5378. 21 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Mailbox Interrupts The IDT70V5388/78 supports mailbox interrupts, facilitating communication among the devices attached to each port. If the user chooses the interrupt function, then each of the upper four address locations in the memory array are assigned as a mailbox for one of the ports: FFFFh (7FFFh for IDT70V5378) is the mailbox for Port 1, FFFEh (7FFEh for IDT70V5378) is the mailbox for Port 2, FFFDh (7FFDh for IDT70V5378) is the mailbox for Port 3, and FFFCh (7FFCh for IDT70V5378) is the mailbox for Port 4. Truth Table III details the operation of the mailbox interrupt functions. A given port’s interrupt is set (i.e., INT goes LOW) whenever any other port on the device writes to the given port’s address. For example, Port 1’s INT will go LOW if Port 2, Port 3, or Port 4 write to FFFFh (7FFFh for IDT70V5378). The INT will go LOW in relation to the clock on the writing port (see also the Mailbox Interrupt Timing waveform on page 20). If a port writes to its own mailbox, no interrupt is generated. The mailbox location is a valid memory address: the user can store an 18-bit data word at that location for retrieval by the target port. In the event that two or more ports attempt to set an interrupt to the same port at the same time, the interrupt signal will go LOW, but the data actually stored at that location will be indeterminate. The actual interrupt is generated as a result of evaluating the state of the address pins, the chip enables, and the R/W pin: if the user wishes to set an interrupt to a specific port without changing the data stored in that port’s mailbox, it is possible to do so by disabling the byte enables during that write cycle. Once INT has gone LOW for a specific port, that port can reset the INT by reading its assigned mailbox. In the case of Port 1, it would clear its INT signal by reading FFFFh (7FFFh for IDT70V5378). As stated previously, the interrupt operation executes based on the state of the address pins, the chip enables, and the R/W pin: it is possible to clear the interrupt by asserting a read to the appropriate location while keeping the output enable (OE) or the byte enables deasserted, and so avoid having to drive data on the I/O bus. The INT is reset, or goes HIGH again, in relation to the reading port’s clock signal. Master Reset The IDT70V5388/78 is equipped with an asynchronous Master Reset input, which can be asserted independently of all clock inputs and will take effect per the Master Reset timing waveform on page 18. The Master Reset sets the internal value of all address counters to zero, and sets the counter mask register on each port to all ones (i.e., completely unmasked). It also resets all mailbox interrupts and counter interrupts to HIGH (i.e., non-asserted) and sets all registered control signals to a deselected state. A Master Reset operation must be performed after power-up, in order to initialize the various registers on the device to a known state. Master Reset will reset the device. For JTAG and MBIST reset please refer to the JTAG Section on page 25. —Mailbox Interrupt Flag Operations Truth Table III— Port 1(1,2) Port 2(1,2) Port 3(1,2) Port 4(1,2) R/W CE A15-A 0(4) INT R/W CE A15-A 0(4) INT R/W CE A15-A 0(4) INT R/W CE A15-A 0(4) INT X X X L L L FFFF X L L FFFF X L L FFFF X Set Port 1 INT Flag (3) H L FFFF H X X X X X X X X X X X X Reset Port 1 INT Flag L L FFFE X X X X L L L FFFE X L L FFFE X Set Port 2 INT Flag (3) X X X X H L FFFE H X X X X X X X X Reset Port 2 INT Flag L L FFFD X L L FFFD X X X X L L L FFFD X Set Port 3 INT Flag (3) X X X X X X X X H L FFFD H X X X X Reset Port 3 INT Flag L L FFFC X L L FFFC X L L FFFC X X X X L Set Port 4 INT Flag (3) X X X X X X X X X X X X H L FFFC H Reset Port 4 INT Flag Function 5649 tbl 14 NOTES: 1. The status of OE is a "Don't Care" for the interrupt logic circuitry. If it is desirable to reset the interrupt flag on a given port while keeping the I/O bus in a tri-state condition, then this can be accomplished by setting OE = VIH while the read access is asserted to the appropriate address location. 2. The status of the LB and UB controls are "Don't Care" for the interrupt circuitry. If it is desirable to set the interrupt flag to a specific port without overwriting the data value already stored at the mailbox location, then this can be accomplished by setting LB = UB = VIH during the write access for that specific mailbox. Similarly, if it desirable to reset the interrupt flag on a given port while keeping the I/O bus in a tri-state condition, then this can be accomplished by setting LB = UB = VIH while the read access is asserted to the appropriate address location. 3. The interrupt to a specific port can be set by any one of the other three ports. The appropriate control states for the other three ports are depicted above. In the event that two or more ports attempt to set the same interrupt flag simultaneously via a valid data write, the data stored at the mailbox location will be indeterminate. 4. A15 is a NC for IDT70V5378, therefore Mailbox Interrupt Addresses are 7FFF, 7FFE, 7FFD and 7FFC. Address comparison will be for A0 - A14. 22 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Address Counter Control Operations Each port on the IDT70V5388/78 is equipped with an internal address counter, to ease the process of bursting data into or out of the device. Truth Table II depicts the specific operation of the counter functions, to include the order of priority among the signals. All counter controls are independent of chip enables. The device supports the ability to load a new address value on each access, or to load an address value on a given clock cycle via the CNTLD control and then allow the counter to increase that value by preset increments on each successive clock via the CNTINC control (see also the Counter Mask Operations section that follows). The counter can be suspended on any clock cycle by disabling the CNTINC, and it can be reset to zero on any clock cycle by asserting the CNTRST control. CNTRST only affects the address value stored in the counter: it has no effect on the counter mask register. When the counter reaches the maximum value in CNTRD MKRD the array (i.e., address FFFFh for IDT70V5388 and address 7FFFh for IDT70V5378) or it reaches the highest value permitted by the Counter Mask Register, it then ‘wraps around’ to the beginning of the array. When Address Min is reached via counter increment (i.e., not as a result of an external address load), then the CNTINT signal for that port is driven low for one clock cycle, automatically resetting on the next cycle. When the CNTRD control is asserted, the IDT70V5388/78 will output the current address stored in the internal counter for that port as noted in the Load and Read Address Counter timing waveform on page 19. The address will be output on the address lines. During this output, the data I/Os will be driven in accordance with the settings of the chip enables, byte enables, and the output enable on that port: the device does not automatically tri-state these pins during the address readback operation. Read Back Register Addr. Read Back MKLD Address (I/O) CNTLD CNTINC CNTRST CLK Mask Register Memory Array Counter/ Address Register , 5649 drw 22 Figure 4. Logic Block Diagram for Read Back Operations 23 6.42 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Counter-Mask Register CNTINT STEP 1 Load Counter-Mask Register = FF H 0 0 0's A15(2)A14 0 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Masked Address STEP 2 Load Address Counter = FD H 0 0 0's A15(2) A14 STEP 3 Max Address Register H X X Max + 1 Address Register L X X 0 1 1 1 1 1 1 0 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 X's A15(2)A14 STEP 4 Counter Address , X 1 1 1 1 1 1 1 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 X's A15(2)A14 X 0 0 0 0 0 0 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 5. Programmable Counter-Mask Register Operation (1) 5649 drw 23 NOTE: 1. The "X's" in this diagram represent the upper bits of the counter. 2. A15 is a NC for IDT70V5378. The internal address counter on each port has an associated Counter Mask Register that allows for configuration of the internal address counter on that port. Truth Table III groups the operations of the address counter with those of the counter mask register, to include Master Reset and applicable readback operations. Each bit in the mask register controls the corresponding bit in the internal address counter: writing a “1” to a bit in the mask register allows that bit to increment in response to CNTINC, while writing a “0” to a bit masks it (i.e., locks it at whatever value is loaded via CNTLD). The mask register is extremely flexible: every bit can be controlled independently of every other bit. The counter simply concatenates those bits that have not been masked, giving the user great selectivity in determining which portions of the memory array are available to a particular port for burst operations. Figure 5 illustrates the operation of the Counter Mask Register in simply constraining a port to a selected portion of the array, specifically addresses 0000h to 00FFh. In step one, the mask register is loaded with 00FFh via MKLD (see also the Load and Read Mask Register timing waveform on page 19). In step two, a starting address of 00FD is asserted for the start point of a burst, and the CNTINC control is enabled. Step three indicates the address counter incrementing to 00FFh. In step four, the internal counter determines that all address values greater than 00FFh have been masked, and so it increments past this ‘max’ value to 0000h. As a result of reaching 0000h via the CNTINC operation, the CNTINT output for this port is automatically triggered – it will go low for one clock cycle and then reset. The example depicted in Figure 5 is a very simple one: it is also possible to mask non-contiguous bits, such as loading 5555h in the mask register. As stated previously, the address counter simply concatenates all bits that have not been masked and continues to increment those bits in accordance with the CNTINC control: in this fashion, if the mask register is set at 5555h and a start address of 0007h is asserted via CNTLD, the next value the counter will increment to in response to the CNTINC control is 0012h, then 0013h, then 0016h, etc. Besides supporting precise control of which portions of the array are available to a particular port in burst operations, the independent control on the mask register bits also provides excellent flexibility in determining the value by which the counter will increment. For example, setting bit 0 of the mask register to “0” masks it from counter operation, effectively configuring that port to count by increments of two. This can be very useful in configuring two ports to work in combination, effectively creating a single 36-bit port. Thus, Port 1 can be configured to count by two starting on even addresses (the start point is asserted via CNTLD), and Port 2 can be configured to count by two starting on odd addresses (again via CNTLD). The two ports together will operate on 36-bit data words, storing half of each word in an even-numbered address, the other half in an odd-numbered address. Setting bits 1 and 0 of the mask register on a given port to “0” configures that port to count 24 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges in increments of four: masking bits 2, 1, and 0 configures that port to count in increments of eight, and so on. The ability to set the increments by which the counters will advance gives the user the ability to interleave memory operations among the ports, minimizing the concerns that a given address might be written by more than one port at any given point in time (an operation that would have indeterminate results). JTAG Support The IDT70V5388/78 provides a serial boundary scan test access port . The JTAG tables starting on page 29 provide the specific details for the JTAG implementation on this device. The IDT70V5388/78 executes a JTAG test logic reset upon power-up. This power-up reset will initialize the TAP controller and MBIST controller. In most power environments no further action is required. However, if the user has any concern about the system’s voltage states during power-up, then the user can use the optional TRST input as part of a board’s power on reset sequence. The TRST pin also provides an alternate means of resetting the JTAG test logic when required, and is available for use by external JTAG controllers as an asynchronous reset signal. If the user does not plan to rely on the optional TRST pin, but wants to use JTAG functionality, the TRST pin should either be tied HIGH (preferred implementation) or left floating. If JTAG operations are not desired, the user has a number of options for disabling the JTAG functions. One would be to simply tie TCK LOW, leaving all other JTAG pins floating (alternatively, TDI and TMS could be tied HIGH). Since the device executes a JTAG reset upon power-up: with TCK tied LOW, no further clocking of the TAP will occur and no JTAG operations will take place. Alternatively, the user can opt to tie TRST LOW (either in lieu of or in addition to tying TCK LOW) and the TAP will be locked in a reset condition, blocking all JTAG operations. Memory Built-In-Test Operations Go-NoGo Testing The IDT70V5388/78 is equipped with a self-test function that can be run by the user as the result of a single instruction, implemented via the JTAG TAP interface. If multiple FourPort devices are used on the same board, all can execute MBIST simultaneously, facilitating board checkout. The MBIST function executes a Go-NoGo test within the device, which then captures pass-fail information and failure count in a special register called the MBIST Result Register (MRR). Upon completion of the test, the MRR can be scanned out via the JTAG interface, using the internal scan operation. Bit zero of the MRR (MRR[0]) is a don't care. Bit one of the MRR (MRR[1])indicates the pass/ fail status: a "0" indicates some sort of failure was noted, 25 6.42 while a "1" indicates that the memory array passed. The rest of the MRR contains the total number of failed read cycles in the entire MBIST sequence. The IDT70V5388/78 MBIST function has been supplemented with the ability for the user to force a failure report from the device. This allows the user the flexibility of validating the MBIST function itself, by verifying that the device is able to report faults as well as passing results. The two modes of operation, normal MBIST testing and forced error reporting, are controlled via the JTAG TAP interface using the instruction PROGRAM_MBIST_MODE_SELECT. For further detail, please refer to the System Interface Parameters table on page 28. The MBIST function executes once the RUNBIST instruction is input via the JTAG interface. The entire MBIST test will be performed with a deterministic number of TCK cycles depending on the TCK and CLKMBIST frequency. This can be calculated by using the following formula: tCYC = tCYC[CLKMBIST] tCYC[TCK] x m + SPC, where: tCYC is the total number of TCK cycles required to run MBIST. SPC is the synchronization padding cycles (typically 4-6 cycles, to accommodate state machine overhead, turnaround cycles, etc.) m is a constant that represents the number of read and write operations required to run the internal MBIST algorithms (14,811,136) for both IDT70V5388 and IDT70V5378. IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges JTAG/BIST TAP Controller Block Diagram 0 Bypass Register (BYR) 1 0 MBIST Mode Select Register (MSR) 3 2 1 0 Instruction Register (IR) 25 24 TDI 1 X MBIST Result Register (MRR) 31 30 29 0 Identification Register (IDR) 391 Selection Circuitry TDO (MUX) 0 Boundary Scan Register (BSR) CLKMBIST MBIST CONTROLLER TAP CONTROLLER TCK TMS TRST MEMORY CELL 5649 drw 25 26 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tTCYC tTL tTH TCK Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO tJDC tJH tJRSR tJCD TRST 5649 drw 26 tJRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. 3. To reset the test (JTAG) port without resetting the device, TMS must be held LOW for 5 cycles, or TRST must be held LOW for one cycle. 27 6.42 , IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Value Revision Number (31:28) Description 0x0 IDT Device ID (27:12) 0x31D(1) IDT JEDEC ID (11:1) 0x33 ID Register Indicator Bit (Bit 0) Reserved for version number Defines IDT part number Allows unique identification of device vendor as IDT 1 Indicates the presence of an ID register 5649 tbl 15 NOTE: 1. Device ID for IDT70V5378 is 0x31E. Scan Register Sizes Register Name Bit Size Instruction (IR) 4 MBIST Mode Select Register (MSR) 2 Bypass (BYR) 1 Identification (IDR) Boundary Scan (BSR) MBIST Result (MRR) 32 392 Note (3) 26 System Interface Parameters Instruction EXTEST 5649 tbl 16 Code Description Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between TDI and TDO. 0000 BYPASS 1111 Places the b ypass register (BYR) between TDI and TDO. IDCODE 0111 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. 0110 Places the bypass register (BYR) b etween TDI and TDO. Forces all device output drivers to a High-Z state. 0001 Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. HIGHZ SAMPLE/PRELOAD 1010 Places the MBIST Mode Register between TDI and TDO. A value of '00' written into this register will allow MBIST to run in standard memory test mode, outputting valid results as appropriate via the MBIST Result Register. A value of '11' written into the MBIST Mode Register will force the MBIST Result Register (MRR) to report a result of 'FAIL'., with 8E0000 failed read cycles noted (i.e., the MRR content = (8E0000h, 0, x). The value of the MBIST Mode Register is no t guaranteed at power-up and is not affected b y Master reset and JTAG reset. RUNBIST 1000 Invokes MBIST. Internally updates MBIST result register with Go-NoGo information and number of is sues. PROGRAM_MBIST_MODE_REGISTER must be run prior to executing RUNBIST in order to ensure valid results. There is no need to repeat this instructio n unless the mode of operation is changed: the MMR will re tain its programmed value until overwritten or the device is powered down. INT_SCAN 0100 Scans out partial information. Places MBIST result register (MRR) between TDI & TDO. CLAMP 0101 Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the Bypass reg ister (BYR) between TDI & TDO. 0010, 0011 Several combinations are reserved. Do not use codes other than those identified above. MBIST_MODE_SELECT RESERVED PRIVATE 1001, 1011, 1100, 1101, 1110 Several combinations arePRIVATE (for IDT internal use). Do not use codes other than those identified above. NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 28 5649 tbl 17 IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Type Power Speed Package A A Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G(2) Green BG BC 272-ball BGA (BG272-1) 256-ball BGA (BC256-1) 200 166 133 100 Commercial Only Commercial & Industrial Commercial & Industrial Speed in MHZ Commercial & Industrial S Standard Power 70V5388 1152K (64K x 18) 3.3V FourPort™ RAM 70V5378 576K (32K x 18) 3.3V FourPort™ RAM 5649 drw 27 NOTES: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. Datasheet Document History 08/20/02: 09/25/02: 08/20/03: 01/31/06: 10/23/08: 11/21/14: 07/29/15: Initial Public Datasheet Added 0.5M Density to Datasheet Page 10 Changed power numbers in DC Electrical Characteristics table Removed Preliminary status Page 1 Added green availability to features Page 29 Added green indicator to ordering information Page 29 Removed "IDT" from orderable part number PDN CQ-14-08 issued. See IDT.com for PDN specifics 70V5388/78 Datasheet changed to Obsolete Status CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 29 6.42 for Tech Support: 408-284-2794 DualPortHelp@idt.com