70V631S12PRFI8

HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Supports JTAG features compliant to IEEE 1149.1 – Due to limited pin count, JTAG is not supported on the 128-pin TQFP package. LVTTL-compatible, single 3.3V (±150mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 128-pin Thin Quad Flatpack, 208-ball fine pitch Ball Grid Array, and 256-ball Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V631 easily expands data bus width to 36 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports 70V631S ◆ ◆ ◆ ◆ ◆ ◆ ◆ Functional Block Diagram UBL UBR LBL LBR R/WL R/WR B E 0 L CE0L CE1L B E 1 L B E 1 R B E 0 R CE0R CE1R OER OEL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R 256K x 18 MEMORY ARRAY Din_L I/O0L- I/O17L A17L A0L Address Decoder Din_R ADDR_L OEL CE0L CE1L I/O0R - I/O17R ARBITRATION INTERRUPT SEMAPHORE LOGIC R/WL A17R Address Decoder ADDR_R A0R OER CE0R CE1R R/WR BUSYR BUSYL SEML M/S SEMR INTL INTR TDI TDO JTAG NOTES: 1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). TMS TCK TRST 5622 drw 01 SEPTEMBER 2019 1 ©2019 Integrated Device Technology, Inc. DSC-5622/9 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Description The IDT70V631 is a high-speed 256K x 18 Asynchronous Dual-Port Static RAM. The IDT70V631 is designed to be used as a stand-alone 4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE DualPort RAM for 36-bit-or-more word system. Using the IDT MASTER/ SLAVE Dual-Port RAM approach in 36-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, Industrial and Commercial Temperature Ranges address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. The 70V631 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V. Pin Configurations(1,2,3,4) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A I/O9L NC VSS TDO NC A16L A12L A8L NC VDD SEML INTL A4L A0L OPTL NC VSS A B NC VSS NC TDI A17L A13L A9L NC CE0L VSS BUSYL A5L A1L VSS VDDQR I/O8L NC B C VDDQL I/O9R VDDQR VDD NC A14L A10L UBL CE1L VSS R/WL A6L A2L VDD I/O8R NC VSS C D NC VSS I/O10L NC A15L A11L A7L LBL VDD OEL NC A3L VDD NC VDDQL I/O7L I/O7R D E I/O11L NC VDDQR I/O10R I/O6L NC VSS NC E F VDDQL I/O11R NC VSS VSS I/O6R NC VDDQR F G NC VSS I/O12L NC NC VDDQL I/O5L NC G H VDD NC VDDQR I/O12R VDD NC VSS I/O5R H J VDDQL VDD VSS VSS VSS VDD VSS VDDQR J I/O3R VDDQL I/O4R VSS K 70V631 BF208(5) BFG208(5) 208-Ball BGA Top View(6) K I/O14R VSS I/O13R VSS L NC I/O14L VDDQR I/O13L NC I/O3L VSS I/O4L L M VDDQL NC I/O15R VSS VSS NC I/O2R VDDQR M N NC VSS NC I/O15L I/O1R VDDQL NC I/O2L N P I/O16R I/O16L VDDQR NC TRST A16R A12R A8R NC VDD SEMR INTR A4R NC I/O1L VSS NC P R VSS NC I/O17R TCK A17R A13R A9R NC CE0R VSS BUSYR A5R A1R VSS VDDQL I/O0R VDDQR R T NC I/O17L VDDQL TMS NC A14R A10R UBR CE1R VSS R/WR A6R A2R VSS NC VSS NC T U VSS NC VDD NC A15R A11R A7R LBR VDD OER M/S A3R A0R VDD OPTR I/O0L U NC 5622 tbl 02b NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V) and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground. 4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 2 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges VDDQL VSS IO10L IO10R VDDQR VSS IO11L IO11R IO12L IO12R VDD VDD VSS VSS IO13R IO13L IO14R IO14L IO15R IO15L VDDQL VSS IO16R IO16L VDDQR VSS IO17R IO17L A17R A16R A15R A14R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 70V631 PKG128(5) 128-Pin TQFP Top View(6) 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A14L A15L A16L A17L IO9L IO9R 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 A13L A12L A11L A10L A9L A8L A7L UBL LBL CE1L CE0L VDD VDD VSS VSS SEML OEL R/WL BUSYL INTL NC A6L A5L A4L A3L A2L Pin Configurations(1,2,3,4,7) (con't.) A1L A0L OPTL VSS IO8L IO8R NC VSS VDDQL IO7L IO7R VSS VDDQR IO6L IO6R IO5L IO5R VDD VDD VSS VSS IO4R IO4L IO3R IO3L IO2R IO2L VSS VDDQL IO1R IO1L VSS VDDQR IO0R IO0L OPTR A0R A1R A13R A12R A11R A10R A9R A8R A7R UBR LBR CE1R CE0R VDD VDD VSS VSS SEMR OER R/WR BUSYR INTR M/S A6R A5R A4R A3R A2R . 5622 drw 02a NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V) and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground. 4. Package body is approximately 14mm x 20mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 7. Due to the restricted number of pins, JTAG is not supported in the PK-128 package. 3 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3,4) (con't.) 70V631 BC256(5) BCG256(5) 256-Pin BGA Top View(6) A1 NC B1 NC C1 NC D1 NC E1 A2 TDI B2 NC C2 I/O9L D2 I/O9R E2 I/O10R I/O10L F1 I/O11L G1 NC H1 NC J1 F2 NC G2 NC H2 I/O12R J2 A3 NC B3 TDO C3 VSS D3 NC E3 NC F3 A4 A5 A6 A17L A14L A11L B4 NC C4 A16L D4 VDD E4 VDDQL F4 I/O11R VDDQL G3 G4 I/O12L VDDQR H3 NC J3 H4 VDDQR J4 I/O13L I/O14R I/O13R VDDQL K1 NC L1 I/O15L M1 K2 NC L2 NC M2 I/O16R I/O16L N1 NC P1 NC R1 NC T1 NC N2 I/O17R P2 K3 I/O14L VDDQL L3 NC T2 TCK L4 I/O15R VDDQR M3 NC N3 NC P3 I/O17L TMS R2 K4 R3 TRST T3 NC M4 VDDQR N4 VDD P4 A16R R4 NC T4 A17R B5 A15L C5 A13L D5 B6 A12L C6 A10L D6 A7 A8L B7 A9L C7 A7L D7 A8 A9 NC CE1L B9 B8 UBL C8 LBL D9 D8 OEL B10 CE0L R/WL C9 NC A10 C10 A11 INTL B11 NC C11 SEML BUSYL D10 D11 A12 A5L B12 A4L C12 A6L D12 VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR E5 VDD F5 VDD G5 VSS H5 VSS J5 VSS K5 VSS L5 VDD M5 VDD N5 E6 VDD F6 VSS G6 VSS H6 VSS J6 VSS K6 VSS L6 VSS M6 VDD N6 E7 VSS F7 VSS G7 VSS H7 VSS J7 VSS K7 VSS L7 VSS M7 VSS N7 E8 E9 VSS VSS F9 F8 VSS VSS G9 G8 VSS H8 VSS H9 VSS J8 VSS J9 VSS K8 VSS K9 VSS L8 VSS L9 VSS M8 VSS M9 VSS N8 VSS N9 E10 VSS F10 VSS G10 VSS H10 VSS J10 VSS K10 VSS L10 VSS M10 VSS N10 E11 VDD F11 VSS G11 VSS H11 VSS J11 VSS K11 VSS L11 VSS M11 VDD N11 E12 A13R R5 A15R T5 A14R P6 A10R R6 A12R T6 A11R P7 A7R R7 A9R T7 A8R P8 P9 NC LBR R9 R8 UBR NC CE1R P11 SEMR BUSYR R10 CE0R R/WR T9 T8 P10 T10 OER R11 M/S T11 INTR A2L B13 A1L C13 A3L D13 VDD E13 VDD VDDQR F12 VDD G12 VSS H12 VSS J12 VSS K12 VSS L12 VDD M12 VDD N12 VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL P5 A13 P12 A6R R12 A4R T12 A5R F13 A14 A0L B14 NC C14 OPTL D14 NC E14 NC F14 VDDQR I/O6R G13 G14 VDDQL I/O5L H13 VDDQL J13 H14 NC J14 A15 A16 NC B15 B16 NC VDDQR L13 K14 NC L14 VDDQL I/O2L M13 M14 VDDQL I/O1R N13 VDD P13 A3R R13 A1R T13 A2R N14 NC P14 NC R14 OPTR T14 A0R NC C16 C15 NC I/O8L D16 D15 NC I/O8R E16 E15 I/O7L F15 I/O7R F16 NC G15 I/O6L G16 NC NC H16 H15 NC J15 I/O5R J16 VDDQR I/O4R I/O3R K13 NC K15 I/O4L K16 NC L15 I/O3L L16 NC I/O2R M16 M15 I/O1L NC N16 N15 I/O0R P15 NC P16 NC I/O0L R16 R15 NC T15 NC , T16 NC NC 5622 drw 02c NOTES: 1. All VDD pins must be connected to 3.3V power supply. 2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking. 4 , 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A17L A0R - A17R Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag UBL UBR Upper Byte Select LBL LBR Lower Byte Select VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1) OPTL OPTR Option for selecting VDDQX(1,2) M/S Master or Slave Select VDD Power (3.3V)(1) VSS Ground (0V) TDI Test Data Input TDO Test Data Output TCK Test Logic Clock (10MHz) TMS Test Mode Select TRST Reset (Initialize TAP Controller) NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on I/OX. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 5622 tbl 01 5 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control(1) OE SEM CE0 CE1 UB LB R/W Byte 1 I/O9-17 Byte 0 I/O0-8 X H H X X X X High-Z High-Z Deselected–Power Down X H X L X X X High-Z High-Z Deselected–Power Down X H L H H H X High-Z High-Z Both Bytes Deselected X H L H H L L High-Z DIN Write to Byte 0 Only X H L H L H L DIN High-Z Write to Byte 1 Only X H L H L L L DIN DIN Write to Both Bytes L H L H H L H High-Z DOUT Read Byte 0 Only L H L H L H H DOUT High-Z Read Byte 1 Only L H L H L L H DOUT DOUT Read Both Bytes H H L H L L X High-Z High-Z Outputs Disabled MODE 5622 tbl 02 NOTE: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. Truth Table II – Semaphore Read/Write Control(1) Inputs(1) Outputs CE R/W OE UB LB SEM I/O1-17 I/O0 H H L L L L DATAOUT DATAOUT Read Data in Semaphore Flag (3) H ↑ X X L L X DATAIN Write I/O0 into Semaphore Flag L X X X X L ______ ______ Mode Not Allowed NOTE: 1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O17). These eight semaphore flags are addressed by A0-A2. 2. CE = L occurs when CE0 = VIL and CE1 = VIH. 3. Each byte is controlled by the respective UB and LB. To read data UB and/or LB = VIL. 6 5622 tbl 03 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Recommended DC Operating Conditions with VDDQ at 2.5V Recommended Operating Temperature and Supply Voltage(1) GND VDD 0 C to +70 C 0V -40 C to +85 C 0V Commercial Industrial Symbol Ambient Temperature Grade O O O O Industrial and Commercial Temperature Ranges Parameter VDD Core Supply Voltage 3.3V + 150mV VDDQ I/O Supply Voltage (3) 3.3V + 150mV VSS Ground NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. 5622 tbl 04 (3) Min. Typ. Max. Unit 3.15 3.3 3.45 V 2.4 2.5 2.6 V 0 0 0 VDDQ + 100mV (2) V V V VIH Input High Voltage (Address & Control Inputs) 1.7 ____ VIH Input High Voltage - I/O(3) 1.7 ____ VDDQ + 100mV(2) ____ 0.7 VIL (1) Input Low Voltage -0.5 V 5622 tbl 06 NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDDQ + 100mV. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied as indicated above. Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +4.6 V TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -65 to +150 o C IOUT DC Output Current Recommended DC Operating Conditions with VDDQ at 3.3V Symbol 50 mA 5622 tbl 05 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV. Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 3.15 3.3 3.45 V VDDQ I/O Supply Voltage (3) 3.15 3.3 3.45 V VSS Ground 0 0 0 VIH Input High Voltage (Address & Control Inputs)(3) 2.0 ____ VDDQ + 150mV (2) V VIH Input High Voltage - I/O(3) 2.0 ____ VDDQ + 150mV(2) V ____ 0.8 VIL Input Low Voltage (1) -0.3 V V 5622 tbl 07 NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDDQ + 150mV. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be supplied as indicated above. Capacitance(1) (TA = +25°C, F = 1.0MHZ) TQFP ONLY Symbol CIN COUT(3) Parameter Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 8 pF VOUT = 3dV 10.5 pF 5622 tbl 08 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. 7 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV) 70V631S Symbol Parameter Test Conditions (1) Min. Max. Unit 10 µA |ILI| Input Leakage Current VDDQ = Max., VIN = 0V to V DDQ ___ |ILO| Output Leakage Current CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ ___ 10 µA VOL (3.3V) Output Low Voltage (2) IOL = +4mA, VDDQ = Min. ___ 0.4 V VOH (3.3V) (2) IOH = -4mA, VDDQ = Min. 2.4 ___ V (2) IOL = +2mA, VDDQ = Min. ___ 0.4 V (2) IOH = -2mA, VDDQ = Min. 2.0 ___ V VOL (2.5V) VOH (2.5V) Output High Voltage Output Low Voltage Output High Voltage 5622 tbl 09 NOTE: 1. At VDD < - 2.0V input leakages are undefined. 2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV) 70V631S10 Com'l Only Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Version 70V631S12 Com'l & Ind 70V631S15 Com'l Typ. (4) Max. Typ. (4) Max. Typ.(4) Max. Unit mA Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L S 340 500 315 465 300 440 IND S ____ ____ 365 515 ____ ____ Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH f = fMAX(1) COM'L S 115 165 90 125 75 100 IND S ____ ____ 115 150 ____ ____ (5) Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f=fMAX(1) COM'L S 225 340 200 325 175 315 IND S ____ ____ 225 365 ____ ____ Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V or VIN < 0.2V, f = 0(2) COM'L S 3 15 3 15 3 15 IND S ____ ____ 6 15 ____ ____ Full Standby Current (One Port - CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5) VIN > VDDQ - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L S 220 335 195 320 170 310 IND S ____ ____ 220 360 ____ ____ mA mA mA mA 5622 tbl 10 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V "X" represents "L" for left port or "R" for right port. 8 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ - 3.3V/2.5V) Input Pulse Levels 2.5V GND to 3.0V / GND to 2.5V Input Rise/Fall Times 2ns Max. Input Timing Reference Levels 1.5V/1.25V Output Reference Levels 1.5V/1.25V Output Load 833Ω DATAOUT Figures 1 and 2 5pF* 770Ω 5622 tbl 11 , Figure 2. Output Test Load 3.3V 590Ω 50Ω 50Ω DATAOUT 1.5V/1.25 10pF (Tester) , DATAOUT 435Ω 5pF* 5622 drw 03 Figure 1. AC Output Test load. 5622 drw 04 Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 10.5pF is the I/O capacitance of this device, and 10pF is the AC Test Load Capacitance. 7 6 5 4 ΔtAA (Typical, ns) 3 2 • 1 • 20.5 • 30 • 50 80 100 200 -1 Capacitance (pF) 5622 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 9 , , 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(5) 70V631S10 Com'l Only Symbol Parameter Min. Max. 70V631S12 Com'l & Ind Min. Max. 70V631S15 Com'l Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns Chip Enable Access Time (3) ____ 10 ____ 12 ____ 15 ns tABE Byte Enable Access Time (3) ____ 5 ____ 6 ____ 7 ns tAOE Output Enable Access Time ____ 5 ____ 6 ____ 7 ns tOH Output Hold from Address Change ns tACE Output Low-Z Time tLZ 3 ____ 3 ____ 3 ____ (1,2) 0 ____ 0 ____ 0 ____ ns (1,2) 0 4 0 6 0 8 ns 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time tPU Chip Enable to Power Up Time (2) tPD Chip Disable to Power Down Time (2) ____ 10 ____ 10 ____ 15 ns tSOP Semaphore Flag Update Pulse (OE or SEM) ____ 4 ____ 6 ____ 8 ns tSAA Semaphore Address Access Time 3 10 3 12 3 20 ns 5622 tbl 12 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 70V631S10 Com'l Only Symbol Parameter 70V631S12 Com'l & Ind 70V631S15 Com'l Min. Max. Min. Max. Min. Max. Unit 10 ____ 12 ____ 15 ____ ns tEW Chip Enable to End-of-Write (3) 8 ____ 10 ____ 12 ____ ns tAW Address Valid to End-of-Write 8 ____ 10 ____ 12 ____ ns 0 ____ 0 ____ 0 ____ ns ns WRITE CYCLE tWC Write Cycle Time (3) tAS Address Set-up Time tWP Write Pulse Width 8 ____ 10 ____ 12 ____ tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 6 ____ 8 ____ 10 ____ ns tDH Data Hold Time (4) tWZ tOW tSWRD tSPS 0 ____ 0 ____ 0 ____ ns (1,2) ____ 4 ____ 4 ____ 4 ns (1,2,4) 0 ____ 0 ____ 0 ____ ns SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns SEM Flag Contention Window 5 ____ 5 ____ 5 ____ ns Write Enable to Output in High-Z Output Active from End-of-Write 5622 tbl 13 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details. 10 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Read Cycles(5) tRC ADDR (4) tAA (4) tACE (6) CE tAOE (4) OE tABE (4) UB, LB R/W tLZ tOH (1) DATAOUT VALID DATA (4) tHZ (2) BUSYOUT tBDD (3,4) 5622 drw 06 NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB or UB. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD. 5. SEM = VIH. Timing of Power-Up Power-Down CE tPU tPD ICC 50% 50% ISB . 5622 drw 07 11 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE or SEM (9) (9) UB, LB tAS (6) tWP tWR (3) (2) R/W tWZ (7) tOW (4) DATAOUT (4) tDW tDH DATAIN 5622 drw 08 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM (9) (6) tAS tWR(3) tEW (2) UB, LB(9) R/W tDW tDH DATAIN 5622 drw 09 NOTES: 1. R/W or CE or BEn = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 12 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS VALID ADDRESS tAW tWR tACE tEW SEM/UB/LB(1) tOH tSOP tDW I/O DATA OUT(2) VALID DATAIN VALID tAS tWP tDH R/W tSWRD OE tAOE tSOP Write Cycle Read Cycle 5622 drw 10 NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate UB/LB controls. 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O17) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 5622 drw 11 NOTES: 1. DOR = DOL = VIL, CEL = CER = VIH. Refer also to Truth Table II for appropriate UB/LB controls. 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag. 13 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70V631S10 Com'l Only Symbol Parameter 70V631S12 Com'l & Ind 70V631S15 Com'l Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S=VIH) tBAA BUSY Access Time from Address Match ____ 10 ____ 12 ____ 15 ns tBDA BUSY Disable Time from Address Not Matched ____ 10 ____ 12 ____ 15 ns tBAC BUSY Access Time from Chip Enable Low ____ 10 ____ 12 ____ 15 ns tBDC BUSY Disable Time from Chip Enable High ____ 10 ____ 12 ____ 15 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ ns ____ 10 ____ 12 ____ 15 ns 8 ____ 10 ____ 12 ____ ns tBDD tWH (3) BUSY Disable to Valid Data (5) Write Hold After BUSY BUSY TIMING (M/S=VIL) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 8 ____ 10 ____ 12 ____ ns PORT-TO-PORT DELAY TIMING tWDD Write Pulse to Data Delay(1) ____ 22 ____ 25 ____ 30 ns tDDD Write Data Valid to Read Data Delay (1) ____ 20 ____ 22 ____ 25 ns 5622 tbl 14 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 14 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5) tWC MATCH ADDR"A" tWP R/W"A" tDW tDH VALID DATAIN "A" tAPS (1) MATCH ADDR"B" tBAA tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH R/W"B" (1) (2) 5622 drw 13 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the 'slave' version. 15 5622 drw 12 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 5622 drw 14 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M/S = VIH)(1) ADDR"A" ADDRESS "N" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 5622 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70V631S10 Com'l Only Symbol Parameter 70V631S12 Com'l & Ind 70V631S15 Com'l Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 10 ____ 12 ____ 15 ns tINR Interrupt Reset Time ____ 10 ____ 12 ____ 15 ns 5622 tbl 15 16 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1) tWC INTERRUPT SET ADDRESS ADDR"A" (2) tWR (4) tAS(3) CE"A" R/W"A" tINS (3) INT"B" 5622 drw 16 tRC ADDR"B" INTERRUPT CLEAR ADDRESS tAS (2) (3) CE"B" OE"B" tINR (3) INT"B" 5622 drw 17 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. Refer to Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. Truth Table III — Interrupt Flag(1,4) Left Port R/WL CEL L L X X X X X L Right Port OEL A17L-A0L X 3FFFF X X L INTL R/WR CER OER A17R-A0R INTR X X X X X L(2) (3) Function Set Right INTR Flag X X X L L 3FFFF H Reset Right INTR Flag X (3) L L X 3FFFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag 3FFFE L H 5622 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTL and INTR must be initialized at power-up. 17 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Truth Table IV — Address BUSY Arbitration Inputs Outputs CEL CER AOL-A17L AOR-A17R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 5622 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V631 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. Truth Table V — Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D17 Left D0 - D17 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V631. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O17). These eight semaphores are addressed by A0 - A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. Functional Description The IDT70V631 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT70V631 has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 18 5622 tbl 18 3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location 3FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 3FFFF. The message (18 bits) at 3FFFE or 3FFFF is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 3FFFE and 3FFFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation. 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Busy Logic address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT70V631 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. Semaphores A18 CE0 MASTER Dual Port RAM BUSYL BUSYR CE0 SLAVE Dual Port RAM BUSYL BUSYR CE1 MASTER Dual Port RAM CE1 SLAVE Dual Port RAM BUSYL BUSYL BUSYR BUSYR 5622 drw 18 Industrial and Commercial Temperature Ranges . Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V631 RAMs. Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT70V631 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT70V631 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration on a master is based on the chip enable and The IDT70V631 is an extremely fast Dual-Port 256K x 18 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, with both ports being completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. Systems which can best use the IDT70V631 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a performance increase offered by the IDT70V631s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT70V631 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very high-speed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then 19 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V631 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, R/W and LB/UB) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore, byte select (SEM, LB/UB) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. However, during reads LB and UB function only as an output for semaphore. They do not have any influence on the semaphore control logic. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table V). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE D Q SEMAPHORE REQUEST FLIP FLOP Q D SEMAPHORE READ D0 WRITE SEMAPHORE READ Figure 4. IDT70V631 Semaphore Logic 5622 drw 19 continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. 20 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tJF tJCL tJCYC tJR tJCH TCK Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO tJDC tJH tJRSR tJCD TRST x 5622 drw 20 tJRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics(1,2,3,4) Symbol Parameter Min. Max. Units tJCYC JTAG Clock Input Period 100 ____ ns tJCH JTAG Clock HIGH 40 ____ ns tJCL JTAG Clock Low 40 ____ ns tJR JTAG Clock Rise Time ____ (1) 3 ns tJF JTAG Clock Fall Time ____ 3(1) ns tJRST JTAG Reset 50 ____ ns tJRSR JTAG Reset Recovery 50 ____ ns tJCD JTAG Data Output ____ 25 ns tJDC JTAG Data Output Hold 0 ____ ns tJS JTAG Setup 15 ____ ns tJH JTAG Hold 15 ____ ns 5622 tbl 19 NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 21 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Value Revision Number (31:28) Description 0x0 Reserved for version number IDT Device ID (27:12) 0x304 Defines IDT part number IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register 5622 tbl 20 Scan Register Sizes Register Name Bit Size Instruction (IR) 4 Bypass (BYR) 1 Identification (IDR) Boundary Scan (BSR) 32 Note (3) 5622 tbl 21 System Interface Parameters Instruction Code Description EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan registe r (BSR) between TDI and TDO. BYPASS 1111 Places the bypass register (BYR) between TDI and TDO. IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. 0100 Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. HIGHZ Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. CLAMP 0011 SAMPLE/PRELOAD 0001 Places the boundary scan registe r (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. All other codes Several combinations are reserved. Do not use codes other than those identified above. RESERVED NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 22 5622 tbl 22 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tray Tape and Reel Blank I (1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G(2) Green BF PRF BC 208-ball fpBGA (BF208, BFG208) 128-pin TQFP (PKG128) 256-ball BGA (BC256, BCG256) 10 12 15 Commercial Only Commercial & Industrial Commercial Only S Standard Power Speed in nanoseconds 70V631 4608K (256K x 18) 3.3V Asynchronous Dual-Port RAM 5622 drw 21 NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available for specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are Obsolete excluding BGA & fpBGA. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 10 12 Orderable Part ID Pkg. Code Pkg. Type Temp. Grade Speed (ns) 15 Orderable Part ID Pkg. Code Pkg. Type Temp. Grade 70V631S10BC BC256 CABGA C 70V631S15BC BC256 CABGA C 70V631S10BC8 BC256 CABGA C 70V631S15BC8 BC256 CABGA C 70V631S10BCG BCG256 CABGA C 70V631S15BF BF208 CABGA C 70V631S10BCG8 BCG256 CABGA C 70V631S15BF8 BF208 CABGA C 70V631S10BF BF208 CABGA C 70V631S10BF8 BF208 CABGA C 70V631S10BFG BFG208 CABGA C 70V631S10BFG8 BFG208 CABGA C 70V631S10PRFG PKG128 TQFP C 70V631S12BC BC256 CABGA C 70V631S12BC8 BC256 CABGA C 70V631S12BCI BC256 CABGA I 70V631S12BCI8 BC256 CABGA I 70V631S12BF BF208 CABGA C 70V631S12BF8 BF208 CABGA C 70V631S12BFGI BFG208 CABGA I 70V631S12BFGI8 BFG208 CABGA I BF208 CABGA I BF208 CABGA I PKG128 TQFP I 70V631S12BFI 70V631S12BFI8 70V631S12PRFGI 23 70V631S High-Speed 3.3V 256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History 06/01/00: 08/07/00: 06/20/01: 08/08/01: 10/01/03: 07/25/08: 01/29/09: 10/23/13: 12/15/17: 09/18/19: Initial Public Offering Page 6, 13 & 20 Inserted additional LB and UB information Page 1 Added JTAG information for TQFP package Page 14 Increased BUSY TIMING parameters tBDA, tBAC, tBDC and tBDD for all speeds Page 21 Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns Page 3 Corrected pin 4 designation error from A17R to A17L on PK-128 pinout Removed Preliminary status Page 2, 3 & 4 Added date revision for pin configurations Page 8, 10, 14 & 16 Removed I-temp 15ns speed from DC & AC Electrical Characteristics Tables Page 23 Removed I-temp 15ns speed from ordering information Added I-temp footnote to ordering information Page 1 & 23 Replaced TM logo with ® logo Page 8 Corrected a typo in the DC Chars table Page 23 Removed "IDT" from orderable part number Page 1 Added green availability to Features Page 23 Added green and T&R indicators to ordering information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 2, 3 & 4 Updated package codes Page 23 Added Orderable Part Information table CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 24 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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