70V7339S
HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
◆
◆
◆
◆
◆
◆
◆
512K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
– 64 independent 8K x 18 banks
– 9 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
– Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
◆
◆
◆
◆
◆
◆
◆
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in 208-pin fine pitch Ball Grid Array (fpBGA) and
256-pin Ball Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
UBL
LBL
OEL
MUX
CONTROL
LOGIC
CONTROL
LOGIC
8Kx18
MEMORY
ARRAY
(BANK 0)
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
UBR
LBR
OER
MUX
I/O0L-17L
A12L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
MUX
I/O
CONTROL
I/O
CONTROL
8Kx18
MEMORY
ARRAY
(BANK 1)
ADDRESS
DECODE
ADDRESS
DECODE
MUX
BANK
DECODE
BANK
DECODE
MUX
I/O0R-17R
A12R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
8Kx18
MEMORY
ARRAY
(BANK 63)
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 18
for details.
MUX
,
TDI
TDO
JTAG
TMS
TCK
TRST
5628 drw 01
OCTOBER 2019
1
©2019 Integrated Device Technology, Inc.
DSC 5628/12
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
8Kx18 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 8Kx18 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data
register, the IDT70V7339 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power down
feature, controlled by CE0 and CE1, permits the on-chip circuitry of each
port to enter a very low standby power mode. The dual chip enables also
facilitate depth expansion.
The 70V7339 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(VDD) remains at 3.3V. Please refer also to the
functional description on page 18.
Pin Configuration(1,2,3,4)
A1
IO9L
B1
NC
C1
A2
NC
B2
VSS
C2
A3
VSS
B3
NC
C3
A4
TDO
B4
TDI
C4
A5
NC
B5
BA4L
C5
A6
BA3L
B6
BA0L
C6
VDDQL I/O9R VDDQR PL/FTL BA5L BA1L
D1
NC
E1
I/O11L
F1
D2
VSS
E2
NC
F2
VDDQL I/O11R
G1
NC
H1
VDD
J1
VDDQL
K1
I/O14R
L1
NC
M1
VDDQL
N1
NC
P1
G2
VSS
H2
NC
J2
VDD
K2
VSS
L2
D3
I/O10L
E3
VSS
T1
NC
U1
VSS
NC
D5
BA2L
D6
A11L
A12L
A9
A8L
B7
B9
B8
A9L
NC
C7
C8
D9
D8
D7
LBL
A7L
B11
ADSL
VSS
C11
C10
CE1L
VSS
D10
VDD
A12
A13
CLKL CNTENL A4L
VDD
B10
CE0L
C9
UBL
A10L
A11
A10
NC
R/WL
D11
OEL REPEATL
B12
A5L
C12
A6L
D12
A3L
B13
A1L
C13
A2L
D13
VDD
E4
F3
NC
G3
I/O12L
H3
VSS
K3
I/O13R
L3
NC
N2
VSS
P2
M3
I/O15R
N3
NC
P3
R2
NC
T2
R3
NC
70V7339
BF208(5)
BFG208(5)
J4
T3
VDD
J14
208-Pin fpBGA
Top View(6)
VSS
K14
U2
NC
U3
PL/FTR
L14
NC
M4
M14
VSS
VSS
N4
N14
I/O15L
U4
NC
A15
OPTL
B15
P6
TRST BA3R
R5
R6
BA4R BA0R
T5
T6
BA5R BA1R
U5
U6
BA2R A11R
P7
A12R
R7
A9R
T7
A10R
U7
A7R
P8
A8R
R8
NC
T8
UBR
U8
LBR
P9
P10
NC
VDD
R10
R9
CE0R
T9
VSS
T10
CE1R
U9
VSS
U10
VDD
NC
B16
VDDQR I/O8L
C15
I/O8R
D15
C16
NC
D16
VDDQL I/O7L
E15
NC
F15
I/O6R
G15
E16
VSS
F16
NC
G16
VDDQL I/O5L
H15
NC
J15
VDD
K15
L15
I/O3L
M15
NC
N15
I/O1R VDDQL
P5
A16
H16
VSS
J16
P11
P12
P13
CLKR CNTENR A4R
R11
ADSR
T11
R/WR
U11
R12
A5R
T12
A6R
U12
OER REPEATR A3R
R13
A1R
T13
A2R
U13
A0R
P14
NC
R14
VSS
T14
VSS
U14
VDD
P15
I/O1L
R15
A17
VSS
B17
NC
C17
VSS
D17
I/O7R
E17
NC
F17
VDDQR
G17
NC
H17
I/O5R
J17
VSS VDDQR
K16
I/O3R VDDQL I/O4R
L4
T4
NC
VSS
K4
I/O17L VDDQL TMS
D14
H14
VSS
I/O17R TCK
VDD
NC
H4
R4
C14
G14
G4
NC
VSS
VSS
VSS
P4
B14
F14
F4
I/O14L VDDQR I/O13L
M2
A0L
I/O6L
VDDQR I/O12R
J3
A14
E14
VDDQR I/O10R
I/O16R I/O16L VDDQR
R1
D4
A8
A7
L16
VSS
M16
K17
VSS
L17
I/O4L
M17
I/O2R VDDQR
N16
NC
P16
VSS
R16
N17
I/O2L
P17
NC
R17
VDDQL I/O0R VDDQR
T15
NC
U15
OPTR
T16
VSS
U16
NC
T17
NC
U17
I/O0L
5628 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Pin Configuration
(1,2,3,4)
Industrial and Commercial Temperature Ranges
(con't.)
70V7339
BC256(5)
BCG256(5)
256-Pin BGA
Top View(6)
A1
NC
B1
NC
C1
NC
D1
NC
E1
A2
TDI
B2
NC
C2
I/O9L
D2
I/O9R
E2
I/O10R I/O10L
F1
I/O11L
G1
NC
H1
NC
J1
F2
NC
G2
NC
H2
I/O12R
J2
A3
NC
B3
TDO
C3
VSS
D3
NC
E3
NC
F3
A4
B4
BA5L
C4
BA3L
D4
NC
L1
I/O15L
M1
K2
NC
L2
NC
M2
I/O16R I/O16L
N1
NC
P1
NC
R1
NC
T1
NC
N2
I/O17R
P2
NC
T2
TCK
BA2L
C5
BA0L
D5
E4
E5
VDDQL VDD
F4
F5
G4
G5
I/O12L VDDQR VSS
H3
NC
J3
K3
H4
H5
VDDQR VSS
J4
K4
J5
VSS
K5
I/O14L VDDQL VSS
L3
L4
L5
I/O15R VDDQR VDD
M3
NC
N3
NC
P3
I/O17L TMS
R2
B5
I/O11R VDDQL VDD
G3
R3
M4
VDDQR
N4
M5
VDD
NC
B6
A12L
C6
A10L
D6
A7
A 8L
B7
A 9L
C7
A7L
D7
A8
NC
B8
UBL
C8
A9
CE1L
B9
A11
C9
LBL
D9
A12
OEL CNTENL A5L
B10
B11
CE0L R/WL REPEATL
NC
D8
A10
C10
C11
CLKL ADSL
D10
D11
B12
A4L
C12
A6L
D12
N5
E6
VDD
F6
VSS
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
VSS
M6
VDD
N6
E7
VSS
F7
VSS
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
F8
VSS
F9
V SS
VSS
G8
G9
VSS
H8
VSS
H9
VSS
J8
VSS
J9
VSS
K8
V SS
K9
VSS
L8
V SS
L9
VSS
M8
V SS
M9
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
VSS
J10
VSS
K10
VSS
L10
VSS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
A13
A2L
B13
A1L
C13
A3L
D13
P4
P5
BA3R BA0R
R4
R5
T4
T5
BA4R BA1R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
LBR
NC
R8
UBR
T8
NC
R9
P10
P11
CLKR ADSR
R10
R11
F12
CE1R
T10
T11
F13
A14
A0L
B14
VDD
C14
OPTL
D14
NC
E14
NC
F14
VDD VDDQR I/O6R
G12
VSS
H12
VSS
J12
G13
G14
VDDQL I/O5L
H13
VDDQL
J13
H14
NC
J14
A15
A16
NC
NC
B16
B15
NC
NC
C16
C15
NC
I/O8L
D16
D15
NC
I/O8R
E16
E15
I/O7L I/O7R
F16
F15
NC
G15
I/O6L
G16
NC
NC
H16
H15
NC
I/O5R
J16
J15
VSS VDDQR I/O4R I/O3R I/O4L
K12
VSS
L12
VDD
M12
VDD
N12
P12
A6R
R12
CE0R R/WR REPEATR A4R
T9
E13
VDD VDDQR
PL/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
TRST BA 5R BA2R
T3
A6
PL/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
I/O13L I/O14R I/O13R VDDQL
K1
A5
BA4L BA1L A11L
T12
OER CNTENR A5R
K13
K14
VDDQR NC
L13
L14
VDDQL I/O2L
M13
M14
K15
K16
NC
L16
L15
NC
VDD
P13
A3R
R13
A1R
T13
A2R
N14
NC
P14
NC
R14
OPTR
T14
A0R
I/O2R
M16
M15
VDDQL I/O1R I/O1L
N13
I/O3L
NC
N16
N15
I/O0R
P15
NC
P16
NC
I/O0L
R16
R15
NC
T15
NC
T16
NC
NC
5628 drw 02d
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
BA0L - BA5L
BA0R - BA5R
Bank Address(4)
A0L - A12L
A0R - A12R
Address
I/O0L - I/O17L
I/O0R - I/O17R
Data Input/Output
CLKL
CLKR
Clock
PL/FTL
PL/FTR
Pipeline/Flow-Through
ADSL
ADSR
Address Strobe Enable
CNTENL
CNTENR
Counter Enable
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
(3)
REPEATL
REPEATR
Counter Repeat
LBL, UBL
LBR, UBR
Byte Enables (9-bit bytes)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(1)
OPTL
OPTR
Option for selecting VDDQX(1,2)
VDD
Power (3.3V)(1)
VSS
Ground (0V)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
5628 tbl 01
6.42
4
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Truth Table I—Read/Write and Enable Control
Industrial and Commercial Temperature Ranges
(1,2,3,4)
OE3
CLK
CE0
CE1
UB
LB
R/W
Upper Byte
I/O9-17
Lower Byte
I/O0-8
X
↑
H
X
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
X
L
X
X
X
High-Z
High-Z
Deselected–Power Down
X
↑
L
H
H
H
X
High-Z
High-Z
All Bytes Deselected
X
↑
L
H
H
L
L
High-Z
DIN
Write to Lower Byte Only
X
↑
L
H
L
H
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
L
L
L
DIN
DIN
L
↑
L
H
H
L
H
High-Z
DOUT
Read Lower Byte Only
L
↑
L
H
L
H
H
DOUT
High-Z
Read Upper Byte Only
L
↑
L
H
L
L
H
DOUT
DOUT
Read both Bytes
H
X
X
X
X
X
X
High-Z
High-Z
Outputs Disabled
MODE
Write to both Bytes
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5628 tbl 02
Truth Table II—Address and Address Counter Control(1,2,7)
Address
Previous
Address
Addr
Used
CLK
ADS
CNTEN
REPEAT(6)
I/O(3)
An
X
An
↑
L(4)
X
H
DI/O (n)
X
An
An + 1
↑
H
L(5)
H
DI/O(n+1)
Counter Enabled—Internal Address generation
X
An + 1
An + 1
↑
H
H
H
DI/O(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
X
(4)
DI/O(0)
X
X
An
↑
X
L
MODE
External Address Used
Counter Set to last valid ADS load
5628 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB/LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB/LB
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB/LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timing Waveform of Counter Repeat, page 17. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L
- BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 18 for details.
6.42
5
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Recommended DC OperatingConditions with VDDQ at 2.5V
Recommended Operating
Temperature and Supply Voltage(1)
Symbol
Parameter
Min.
Typ.
Max.
Unit
3.15
3.3
3.45
V
2.4
2.5
2.6
V
0
0
0
Input High Voltage
(Address & Control Inputs)
1.7
____
VDDQ + 100mV
(2)
V
Input High Voltage - I/O(3)
1.7
____
VDDQ + 100mV(2)
V
____
0.7
V
Ambient
Temperature
GND
VDD
VDD
Core Supply Voltage
0OC to +70OC
0V
3.3V + 150mV
VDDQ
I/O Supply Voltage
(3)
-40OC to +85OC
0V
3.3V + 150mV
VSS
Ground
VIH
VIH
Grade
Commercial
Industrial
Industrial and Commercial Temperature Ranges
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
5628 tbl 04
VIL
(1)
Input Low Voltage
-0.3
V
5628 tb l 05a
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 100mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied
as indicated above.
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
IOUT
DC Output Current
Recommended DC OperatingConditions with VDDQ at 3.3V
Symbol
50
mA
5628 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
6.42
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.15
3.3
3.45
V
VDDQ
I/O Supply Voltage
(3)
3.15
3.3
3.45
V
VSS
Ground
0
0
0
VIH
Input High Voltage
(Address & Control Inputs)(3)
2.0
____
VDDQ + 150mV
(2)
V
VIH
Input High Voltage - I/O(3)
2.0
____
VDDQ + 150mV(2)
V
____
0.8
V
VIL
Input Low Voltage
(1)
-0.3
V
5628 tbl 05b
NOTES:
1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
CIN
COUT(3)
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
V IN = 3dV
8
pF
VOUT = 3dV
10.5
pF
5628 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V7339S
Symbol
|ILI|
|ILO|
Parameter
Input Leakage Current(1)
(1)
Output Leakage Current
Test Conditions
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to V DDQ
___
10
µA
10
µA
CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ
___
VOL (3.3V)
Output Low Voltage
(2)
IOL = +4mA, VDDQ = Min.
___
0.4
V
VOH (3.3V)
Output High Voltage (2)
IOH = -4mA, VDDQ = Min.
2.4
___
V
VOL (2.5V)
(2)
IOL = +2mA, VDDQ = Min.
___
0.4
V
(2)
IOH = -2mA, VDDQ = Min.
2.0
___
V
VOH (2.5V)
Output Low Voltage
Output High Voltage
5628 tbl 08
NOTES:
1. At VDD < 2.0V leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 4 for details.
6.42
7
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(5) (VDD = 3.3V ± 150mV)
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Test Condition
Version
70V7339S200(7)
Com'l Only
70V7339S166(6)
Com'l
& Ind
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
70V7339S133
Com'l
& Ind
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L
S
815
950
675
790
550
645
IND
S
____
____
675
830
550
675
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
340
410
275
340
250
295
IND
S
____
____
275
355
250
310
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(3)
Active Port Outputs Disabled,
f=fMAX(1)
COM'L
S
690
770
515
640
460
520
IND
S
____
____
515
660
460
545
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CEL and CER > VDDQ - 0.2V,
VIN > VDDQ - 0.2V or VIN < 0.2V,
f = 0(2)
COM'L
S
10
30
10
30
10
30
IND
S
____
____
10
40
10
40
COM'L
S
690
770
515
640
460
520
IND
S
____
____
515
660
460
545
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V
VIN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
f = fMAX(1)
(5)
mA
mA
mA
mA
5628 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 166MHz Industrial Temperature not available in BF-208 package.
7. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade is available in BC-256 only.
6.42
8
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
GND to 3.0V/GND to 2.4V
Input Pulse Levels (I/Os)
GND to 3.0V/GND to 2.4V
Input Rise/Fall Times
2.5V
833Ω
2ns
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Output Load
DATAOUT
5pF*
770Ω
Figures 1 and 2
5628 tbl 10
,
3.3V
590Ω
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
,
DATAOUT
435Ω
5pF*
5628 drw 03
Figure 1. AC Output Test load.
5628 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
ΔtCD
(Typical, ns) 3
2
•
1
•
20.5
•
30
•
50
80
100
200
-1
Capacitance (pF)
5628 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42
9
,
,
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V7339S200(5)
Com'l Only
Symbol
tCYC1
Parameter
Clock Cycle Time (Flow-Through)
(1)
(1)
70V7339S166(3,4)
Com'l
& Ind
70V7339S133(3)
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
25
____
ns
ns
tCYC2
Clock Cycle Time (Pipelined)
5
____
6
____
7.5
____
tCH1
Clock High Time (Flow-Through)(1)
5
____
6
____
7
____
ns
tCL1
(1)
ns
ns
tCH2
5
____
6
____
7
____
Clock Low Time (Flow-Through)
(2)
2.0
____
2.1
____
2.6
____
(1)
ns
Clock High Time (Pipelined)
tCL2
Clock Low Time (Pipelined)
2.0
____
2.1
____
2.6
____
tR
Clock Rise Time
____
1.5
____
1.5
____
1.5
ns
tF
Clock Fall Time
____
1.5
____
1.5
____
1.5
ns
tSA
Address Setup Time
1.5
____
1.7
____
1.8
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tSC
Chip Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSB
Byte Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSW
R/W Setup Time
1.5
____
1.7
____
1.8
____
ns
tHW
R/W Hold Time
0.5
____
0.5
____
0.5
____
ns
tSD
Input Data Setup Time
1.5
____
1.7
____
1.8
____
ns
tHD
ns
Input Data Hold Time
0.5
____
0.5
____
0.5
____
tSAD
ADS Setup Time
1.5
____
1.7
____
1.8
____
ns
tHAD
ADS Hold Time
0.5
____
0.5
____
0.5
____
ns
tSCN
CNTEN Setup Time
1.5
____
1.7
____
1.8
____
ns
CNTEN Hold Time
0.5
____
0.5
____
0.5
____
ns
tSRPT
REPEAT Setup Time
1.5
____
1.7
____
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.0
____
4.0
____
4.2
ns
tOLZ
Output Enable to Output Low-Z
0.5
____
0.5
____
0.5
____
ns
tOHZ
Output Enable to Output High-Z
tHCN
tCD1
Clock to Data Valid (Flow-Through)
(1)
(1)
1
3.4
1
3.6
1
4.2
ns
____
10
____
12
____
15
ns
____
tCD2
Clock to Data Valid (Pipelined)
3.4
____
3.6
____
4.2
ns
tDC
Data Output Hold After Clock High
1
____
1
____
1
____
ns
tCKHZ
Clock High to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCKLZ
Clock High to Output Low-Z
0.5
____
0.5
____
0.5
____
ns
5.0
____
6.0
____
7.5
____
ns
Port-to-Port Delay
tCO
Clock-to-Clock Offset
5628 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPEX = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPEX. FT/PIPEX should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired operating voltage levels for each port.
4. 166MHz Industrial Temperature not available in BF-208 package.
5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only.
6.42
10
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(ADS Operation) (FT/PIPE'X' = VIH)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tSB
tHB
UB/LB
R/W
ADDRESS
tSW
tHW
tSA
tHA
(4)
An
An + 1
(1 Latency)
An + 2
An + 3
tDC
tCD2
DATAOUT
Qn
tCKLZ
OE
tHB
(5)
Qn + 1
Qn + 2
(5)
(1)
tOHZ
tOLZ
(1)
tOE
5628 drw 06
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tSC
tHC
tHC
(3)
CE1
tSB
tHB
BEn
tSB
tHB
(5)
R/W
tSW tHW
tSA
ADDRESS
(4)
tHA
An
An + 1
An + 2
tCD1
tCKHZ
Qn
DATAOUT
Qn + 2 (5)
Qn + 1
tCKLZ
OE
An + 3
tDC
tOHZ
tOLZ
tDC
(1)
tOE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB/LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB/LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
11
5628 drw 07
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
A0
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
tCD2
tCD2
tCKHZ
Q0
DATAOUT(B1)
tSA
A0
tSC
Q3
tCKLZ
tDC
tCKHZ
tHA
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
tCD2
Q1
tDC
ADDRESS(B2)
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD2
DATAOUT(B2)
tCKHZ
tCD2
Q4
Q2
tCKLZ
tCKLZ
5628 drw 08
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
tCH1
tCYC1
tCL1
CLK
tSA
A0
ADDRESS(B1)
CE0(B1)
tHA
tSC
tHC
tSC
tCD1
tHC
tCD1
tCKHZ
D0
DATAOUT(B1)
tSC
tCD1
D3
tCKLZ
tDC
(1)
D5
tCKHZ (1)
tCKLZ
(1)
A6
A5
A4
A3
A2
A1
tSC
CE0(B2)
tCD1
tHA
A0
ADDRESS(B2)
(1)
D1
tDC
tSA
A6
A5
A4
A3
A2
A1
tHC
tHC
tCD1
DATAOUT(B2)
tCKLZ
(1)
tCKHZ
(1)
tCD1
D2
tCKLZ
(1)
tCKHZ
(1)
D4
5628 drw 09
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V7339 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB/LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
12
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Port A Write to Pipelined Port B Read(1,2,4)
CLK"A"
tSW
tHW
tSA
tHA
R/W"A"
BANK ADDRESS
AND ADDRESS"A"
An
tSD
DATAIN"A"
tHD
Dn
tCO(3)
CLK"B"
tCD2
R/W"B"
BANK ADDRESS
AND ADDRESS"B"
tSW
tHW
tSA
tHA
An
DATAOUT"B"
Dn
tDC
5628 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle
(ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW tHW
R/W "A"
tSA
BANK ADDRESS
AND ADDRESS "A"
An
tSD
DATAIN "A"
tHA
tHD
Dn
tCO(3)
CLK "B"
tCD1
R/W "B"
BANK ADDRESS
AND ADDRESS "B"
tSW
tHW
tSA
tHA
An
DATAOUT "B"
Dn
tDC
tDC
5628 drw 11
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then operations from both ports are INVALID. If tCO ≥ minimum, then data from Port "B" read is available on first Port "B" clock cycle
(i.e., time from write to valid read on opposite port will be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
13
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
tCYC2
(OE = VIL)(2)
tCH2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB/LB
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
An + 3
An + 2
An + 4
tSD tHD
DATAIN
Dn + 2
tCD2
(1)
tCKHZ
tCKLZ
tCD2
Qn + 3
Qn
DATAOUT
READ
NOP
(4)
WRITE
READ
5628 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
tCH2
tCYC2
tCL2
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB/LB
tSW tHW
R/W
(3)
ADDRESS
tSW tHW
An
tSA tHA
An +1
An + 2
tSD
DATAIN
Qn
DATAOUT
An + 4
An + 5
tHD
Dn + 2
tCD2
(1)
An + 3
Dn + 3
tCKLZ
tCD2
Qn + 4
(4)
tOHZ
OE
READ
WRITE
READ
5628 drw 13
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
14
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCH1
tCYC1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB/LB
tSW tHW
R/W
tSW tHW
(3)
ADDRESS
tSA
An
tHA
An +1
An + 2
An + 4
An + 3
An + 2
tSD tHD
DATAIN
Dn + 2
tCD1
(1)
tCD1
Qn
DATAOUT
tCD1
tCD1
Qn + 1
tDC
tCKLZ
tCKHZ
READ
NOP
(4)
Qn + 3
tDC
READ
WRITE
5628 drw 14
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tSB
tHB
CE1
UB/LB
tSW tHW
tSW tHW
R/W
(3)
An
tSA tHA
ADDRESS
An +1
DATAIN
(1)
DATAOUT
An + 2
tSD tHD
An + 3
Dn + 2
Dn + 3
tDC
tCD1
An + 4
tOE
tCD1
Qn
tCKLZ
tOHZ
An + 5
tCD1
Qn + 4
tDC
OE
READ
WRITE
READ
5628 drw 15
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB/LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
15
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
DATAOUT
Qx - 1(2)
Qn + 2(2)
Qn + 1
Qn
Qx
Qn + 3
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5628 drw 16
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1
tCYC1
tCL1
CLK
tSA
ADDRESS
tHA
An
tSAD tHAD
ADS
tSAD tHAD
tSCN tHCN
CNTEN
tCD1
DATAOUT
Qx(2)
Qn + 1
Qn
Qn + 2
Qn + 3(2)
Qn + 4
tDC
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
READ
WITH
COUNTER
5628 drw 17
NOTES:
1. CE0, OE, UB/LB = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
data output remains constant for subsequent clocks.
6.42
16
the
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1,6)
tCH2
tCYC2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(5)
An + 2
An + 1
An + 4
An + 3
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 1
Dn
DATAIN
WRITE
EXTERNAL
ADDRESS
Dn + 1
Dn + 4
Dn + 3
Dn + 2
WRITE
WRITE
WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5628 drw 18
Timing Waveform of Counter Repeat for Flow Through Mode(2,6,7)
tCYC2
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An+2
An+1
An
An+2
An
An+1
An+2
An+2
tSAD tHAD
ADS
tSW tHW
R/W
tSCN tHCN
CNTEN
REPEAT
(4)
tSRPT tHRPT
tSD tHD
DATAIN
D0
D3
D2
D1
tCD1
An
DATAOUT
An+1
An+2
An+2
,
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
An+1
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
5628 drw 19
NOTES:
1. CE0, UB/LB, and R/W = VIL; CE1 and REPEAT = VIH.
2. CE0, UB/LB = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.
7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42
17
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Functional Description
Industrial and Commercial Temperature Ranges
The IDT70V7339 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide minimal setup and hold times on
address, data and all critical control inputs.
An asynchronous output enable is provided to ease asynchronous
bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory applications.
A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down
the internal circuitry on each port (individually controlled) to reduce static
power consumption. Dual chip enables allow easier banking of multiple
IDT70V7339s for depth expansion configurations. Two cycles are
required with CE0 LOW and CE1 HIGH to read valid data on the outputs.
The IDT70V7339 is a high-speed 512Kx18 (9 Mbit) synchronous
Bank-Switchable Dual-Ported SRAM organized into 64 independent
8Kx18 banks. Based on a standard SRAM core instead of a traditional true
dual-port memory core, this bank-switchable device offers the benefits of
increased density and lower cost-per-bit while retaining many of the
features of true dual-ports. These features include simultaneous, random
access to the shared array, separate clocks per port, 166 MHz operating
speed, full-boundary counters, and pinouts compatible with the IDT70V3319
(256Kx18) dual-port family.
The two ports are permitted independent, simultaneous access into
separate banks within the shared array. Access by the ports into specific
banks are controlled by the bank address pins under the user's direct
control: each port can access any bank of memory with the shared array
that is not currently being accessed by the opposite port (i.e., BA0L - BA5L
≠ BA0R - BA5R). In the event that both ports try to access the same bank
at the same time, neither access will be valid, and data at the two specific
addresses targeted by the ports within that bank may be corrupted (in the
case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
Depth and Width Expansion
The IDT70V7339 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V7339 can also be used in applications requiring expanded
width, as indicated in Figure 4. Through combining the control signals, the
devices can be grouped as necessary to accommodate applications
needing 36-bits or wider.
BA6(1)
IDT70V7339
CE0
CE1
CE0
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V7339
IDT70V7339
CE1
IDT70V7339
CE0
CE0
Control Inputs
CE1
Control Inputs
5628 drw 20
Figure 4. Depth and Width Expansion with IDT70V7339
BE,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
NOTE:
1. In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are
controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently
being accessed by the opposite port (i.e., BA0L - BA6L ≠ BA0R - BA6R). In the event that both ports try to access the same bank at the same time, neither
access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are
writing) or may result in invalid output (in the case that both ports are trying to read).
6.42
18
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
5628 drw 21
tJRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70V7339
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
(1)
ns
tJF
JTAG Clock Fall Time
____
(1)
3
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
3
5628 tbl 12
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
19
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x0
Reserved for version number
IDT Device ID (27:12)
0x301
Defines IDT part number
IDT JEDEC ID (11:1)
0x33
Allows unique identification of device vendor as IDT
ID Register Indicator Bit (Bit 0)
1
Indicates the presence of an ID register
5628 tbl 13
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
5628 tbl 14
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the bound ary scan cells onto the device outputs (1).
Places the boundary scan registe r (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass registe r (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) be tween TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the bypass registe r (BYR) between TDI and TDO.
CLAMP
0011
SAMPLE/PRELOAD
0001
Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the b oundary scan cells via the TDI.
All other codes
Several combinations are reserved. Do not use codes other than those
identified above.
RESERVED
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
20
5628 tbl 15
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
999
A
Device
Type
Power
Speed
Package
A
A
A
Process/
Temperature
Range
Blank
8
Tray
Tape and Reel
Blank
I(4)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(3)
Green
BF
BC
208-pin fpBGA (BF208, BFG208)
256-pin BGA (BC256, BCG256)
200
166
133
Commercial Only(1)
Commercial & Industrial(2) Speed in Megahertz
Commercial & Industrial
S
Standard Power
70V7339 9Mbit (512K x 18-Bit) Synchronous Bank-Switchable Dual-Port RAM
NOTES:
1. Available in BC-256 package only.
2. Industrial Temperature at 166MHz not available in the BF-208 package.
3. Green parts available. For specific speeds, packages and powers contact your local sales office.
4. Contact your local sales office for industrial temp range for other speeds, packages and powers
Orderable Part Information
Speed
(MHz)
133
166
200
Pkg.
Code
Pkg.
Type
Temp.
Grade
70V7339S133BC
BC256
CABGA
C
70V7339S133BC8
BC256
CABGA
C
70V7339S133BCI
BC256
CABGA
I
70V7339S133BCI8
BC256
CABGA
I
70V7339S133BF
BF208
CABGA
C
70V7339S133BF8
BF208
CABGA
C
70V7339S133BFI
BF208
CABGA
I
70V7339S133BFI8
BF208
CABGA
I
70V7339S166BC
BC256
CABGA
C
70V7339S166BC8
BC256
CABGA
C
70V7339S166BCGI
BCG256
CABGA
I
70V7339S166BCI
BC256
CABGA
I
70V7339S166BCI8
BC256
CABGA
I
Orderable Part ID
70V7339S166BF
BF208
CABGA
C
70V7339S166BF8
BF208
CABGA
C
70V7339S166BFG
BFG208
CABGA
C
70V7339S166BFG8
BFG208
CABGA
C
70V7339S200BC
BC256
CABGA
C
70V7339S200BC8
BC256
CABGA
C
6.42
21
5628 drw 22
70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
01/05/00:
06/20/01:
08/06/01:
11/20/01:
03/18/02:
12/04/02:
01/16/04:
07/25/08:
01/29/09:
04/20/10:
08/11/15:
06/22/18:
10/22/19:
Initial Public Offering
Page 1 Added JTAG information for TQFP package
Page 4 & 22 Changed TQFP package from DA to DD
Corrected Pin number on TQFP package from 100 to 110
Page 20 Increased tJCD from 20ns to 25ns
Page 4 Changed body size for DD package from 22mm x 22mm x1.6mm to 20mm x 20mm x 1.4mm
Page 9 Changed ISB3 values for commercial and industrial DC Electrical Characteristics
Page 2, 3 & 4 Added date revision for pin configurations
Page 11 Changed tOE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05
Page 1 & 22 Replaced TM logo with ® logo
Page 1, 9, 11 & 22 Added 200MHZ specification
Page 9 Tightened power numbers in DC Electrical Characteristics
Page 14 Changed waveforms to show INVALID operation if tCO < minimum specified
Page 1 - 22 Removed "Preliminary" status
Page 9, 11 & 22 Designated 200Mhz speed grade in BC-256 package only
Page 11 Added byte enable setup time and byte enable hold time parameters and values to all speed grades in the AC Electrical
Characteristics Table
Page 9 Corrected a typo in the DC Chars table
Page 22 Removed "IDT" from orderable part number
Page 1 Added green availability to features
Page 21 Added green indicator to ordering information
Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01
Page 2 & 3 Removed the date from all of the pin configurations BF208 & BC256
Page 21 Added T&R indicator and updated footnotes for Ordering Information
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Page 2 & 3 Updated package codes
Page 21 Added Orderable Part Information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
22
for Tech Support:
408-284-2794
DualPortHelp@idt.com
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