70V9369L9PF8

HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 9ns (max.) Low-power operation – IDT70V9369L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic ◆ ◆ ◆ ◆ ◆ 70V9369L Full synchronous operation on both ports – 4ns setup to clock and 1ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 9ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 15ns cycle time, 67MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Available in a 100-pin Thin Quad Flatpack (TQFP) Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR CE0L 1 0 0/1 CE1L CE0R 1 0 0/1 CE1R LBL OEL LBR OER FT/PIPEL 0/1 1b 0b b a 0a 1a 1a 0a a 0b 1b b 0/1 FT/PIPER I/O9R-I/O17R I/O9L-I/O17L I/O Control I/O Control I/O0L-I/O8L I/O0R-I/O8R A13R A13L A0L CLKL ADSL CNTENL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR CNTRSTL 5648 drw 01 NOVEMBER 2019 1 ©2019 Integrated Device Technology, Inc. DSC-5648/7 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Description: The IDT70V9369 is a high-speed 16K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. Industrial and Commercial Temperature Range With an input data register, the IDT70V9369 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 500mW of power. A8R A9R A10R A11R A12R A13R NC NC LBR UBR CE0R CE1R CNTRSTR R/WR VSS OER FT/PIPER I/O17R VSS I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R Pin Configuration(1,2,3) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 42 83 84 85 86 41 70V9369 PNG100(4) 87 88 89 100-Pin TQFP Top View 90 91 37 36 35 34 33 92 93 94 95 96 97 98 99 100 1 2 40 39 38 32 31 30 29 28 3 4 5 6 7 8 27 26 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A9L A10L A11L A12L A13L NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VDD FT/PIPEL I/O17L I/O16L VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L A7R A6R A5R A4R A3R A2R A1R A0R CNTENR CLKR ADSR Vss VSS ADSL CLKL CNTENL A0L A1L A2L A3L A4L A5L A6L A7L A8L NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 6.42 2 I/O10R I/O9R I/O8R I/O7R VDD I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R VSS I/O0L I/O1L VSS I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L VDD I/O8L I/O9L 5648 drw 02 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (2) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A13L A0R - A13R Address I/O0L - I/O17L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock UBL UBR Upper Byte Select(1) LBL LBR Lower Byte Select(1) ADSL ADSR Address Strobe Enable CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through / Pipeline VDD Power (3.3V) VSS Ground (0V) 5648 tbl 01 NOTES: 1. LB and UB are single buffered regardless of state of FT/PIPE. 2. CE0 and CE1 are single buffered when FT/PIPE = VIL, CE0 and CE1 are double buffered when FT/PIPE = VIH, i.e., the signals take two cycles to deselect. Truth Table I—Read/Write and Enable Control(1,2,3) OE CLK CE0 CE1 UB LB R/W Upper Byte I/O9-17(4) Lower Byte I/O0-8(5) X ↑ H X X X X High-Z High-Z Deselected–Power Down X ↑ X L X X X High-Z High-Z Deselected–Power Down X ↑ L H H H X High-Z High-Z Both Bytes Deselected X ↑ L H L H L DATAIN High-Z Write to Upper Byte Only X ↑ L H H L L High-Z DATAIN Write to Lower Byte Only X ↑ L H L L L DATAIN DATAIN Write to Both Bytes L ↑ L H L H H DATAOUT High-Z Read Upper Byte Only L ↑ L H H L H High-Z DATAOUT Read Lower Byte Only L ↑ L H L L H DATAOUT DATAOUT Read Both Bytes H X L H L L X High-Z High-Z Outputs Disabled MODE 5648 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 6.42 3 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Truth Table II—Address Counter Control(1,2,6) Address Previous Internal Address Internal Address Used CLK(6) An X An ↑ H H X An An + 1 ↑ X An + 1 An + 1 ↑ X X A0 ↑ ADS MODE CNTEN CNTRST I/O(3) X H DI/O (n) L H DI/O(n+1) Counter Enabled—Internal Address generation H H DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused) X (4) L(4) (5) X L External Address Used DI/O(0) Counter Reset to Address 0 5648 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily. Recommended DC Operating Conditions Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Symbol Ambient Temperature(1) GND VDD 0OC to +70OC 0V 3.3V + 0.3V -40OC to +85OC 0V 3.3V + 0.3V NOTE: 1. This is the parameter TA. This is the "instant on" case temperature. VDD Supply Voltage Vss Ground VIH 5648 tbl 04 Parameter VIL Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 Input High Voltage 2.0V Input Low Voltage (1) -0.3 ____ V VDD+0.3V ____ (2) 0.8 V 5648 tbl 05 NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDD +0.3V. Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +4.6 V TBIAS(3) Temperature Under Bias -55 to +125 o TSTG Storage Temperature -65 to +150 o C TJN Junction Temperature +150 o C IOUT DC Output Current 50 V Capacitance(1) (TA = +25°C, f = 1.0MHZ) Symbol CIN C Parameter Input Capacitance (2) COUT Output Capacitance Conditions Max. Unit VIN = 0V 9 pF VOUT = 0V 10 pF 5648 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. COUT also references CI/O. mA 5648 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD +0.3V. 3. Ambient Temperature Under DC Bias. No AC Conditions. Chip deselect. 6.42 4 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V) 70V9369L Symbol Parameter Test Conditions (1) Min. Max. Unit |ILI| Input Leakage Current VDD = 3.6V, VIN = 0V to VDD ___ 5 µA |ILO| Output Leakage Current CEO = VIH or CE1 = VIL, VOUT = 0V to VDD ___ 5 µA VOL Output Low Voltage IOL = +4mA ___ 0.4 V VOH Output High Voltage IOH = -4mA 2.4 ___ V 5648 tbl 08 NOTE: 1. At VDD < 2.0V input leakages are undefined. DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V) 70V9369L6 Com'l Only Symbol IDD ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Version 70V9369L7 Com'l & Ind 70V9369L9 Com'l Only 70V9369L12 Com'l Only Typ.(4) Max. Typ. (4) Max. Typ.(4) Max. Typ.(4) Max. Unit mA Dynamic Operating Current (Both Ports Active) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) COM'L L 220 350 200 290 180 225 150 205 IND L ____ ____ 200 335 ____ ____ ____ ____ Standby Current (Both Ports - TTL Level Inputs) CEL = CER = VIH COM'L L 70 130 65 100 50 65 40 50 f = fMAX(1) IND L ____ ____ 65 115 ____ ____ ____ ____ Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) COM'L L 150 250 140 210 110 150 100 140 IND L ____ ____ 140 240 ____ ____ ____ ____ Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) COM'L L 0.4 5 0.4 5 0.4 5 0.4 5 IND L ____ ____ 0.4 15 ____ ____ ____ ____ Full Standby Current (One Port - CMOS Level Inputs) COM'L CE"A" < 0.2V and CE"B" > VDD - 0.2V (5) IND VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) L 140 240 130 200 100 140 90 130 ____ ____ 130 230 ____ ____ ____ ____ L mA mA mA mA 5648 tbl 09 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6.42 5 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1, 2, and 3 5648 tbl 10 3.3V 3.3V 590Ω 590Ω DATAOUT DATAOUT 30pF 435Ω 5pF* 435Ω 5648 drw 03 5648 drw 04 Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig. Figure 1. AC Output Test load. 8 7 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 5 tCD1, tCD2 (Typical, ns) 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 5648 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 6 . 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VDD = 3.3V ± 0.3V) 70V9369L6 Com'l Only Symbol Parameter (2) 70V9369L7 Com'l Only & Ind 70V9369L9 Com'l Only 70V9369L12 Com'l Only Min. Max. Min. Max. Min. Max. Min. Max. Unit 19 ____ 22 ____ 25 ____ 30 ____ ns 10 ____ 12 ____ 15 ____ 20 ____ ns tCYC1 Clock Cycle Time (Flow-Through) tCYC2 Clock Cycle Time (Pipelined)(2) tCH1 Clock High Time (Flow-Through)(2) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns tCL1 (2) tCH2 Clock Low Time (Flow-Through) 6.5 ____ 7.5 ____ 12 ____ 12 ____ ns (2) 4 ____ 5 ____ 6 ____ 8 ____ ns (2) 4 ____ 5 ____ 6 ____ 8 ____ ns Clock High Time (Pipelined) tCL2 Clock Low Time (Pipelined) tR Clock Rise Time ____ 3 ____ 3 ____ 3 ____ 3 ns tF Clock Fall Time ____ 3 ____ 3 ____ 3 ____ 3 ns tSA Address Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHA Address Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSC Chip Enable Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHC Chip Enable Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSW R/W Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHW R/W Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSD Input Data Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHD Input Data Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns ns tSAD ADS Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ tHAD ADS Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tSCN CNTEN Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHCN CNTEN Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns CNTRST Setup Time 3.5 ____ 4 ____ 4 ____ 4 ____ ns tHRST CNTRST Hold Time 0 ____ 0 ____ 1 ____ 1 ____ ns tOE Output Enable to Data Valid ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns tOLZ Output Enable to Output Low-Z(1) 2 ____ 2 ____ 2 ____ 2 ____ ns tOHZ (1) tSRST tCD1 Output Enable to Output High-Z Clock to Data Valid (Flow-Through) (2) tCD2 Clock to Data Valid (Pipelined) tDC Data Output Hold After Clock High tCKHZ tCKLZ (2) 1 7 1 7 1 7 1 7 ns ____ 15 ____ 18 ____ 20 ____ 25 ns ____ 6.5 ____ 7.5 ____ 9 ____ 12 ns 2 ____ 2 ____ 2 ____ 2 ____ ns (1) 2 9 2 9 2 9 2 9 ns (1) 2 ____ 2 ____ 2 ____ 2 ____ ns Clock High to Output High-Z Clock High to Output Low-Z Port-to-Port Delay tCWDD Write Port Clock High to Read Data Delay ____ 24 ____ 28 ____ 35 ____ 40 ns tCCS Clock-to-Clock Setup Time ____ 9 ____ 10 ____ 15 ____ 15 ns 5648 tbl 11 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL. 6.42 7 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,7) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC tSB tHB tSC tHC tSB tHB CE1 UB, LB R/W tSW tHW tSA (5) ADDRESS tHA An An + 1 tCD1 DATAOUT An + 3 tCKHZ (1) Qn tCKLZ OE An + 2 tDC Qn + 1 Qn + 2 (1) (1) tOHZ tDC tOLZ (1) (2) tOE 5648 drw 06 Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,7) tCYC2 tCH2 tCL2 CLK CE0 tSC tSC tHC tHC (4) CE1 tSB tSB tHB R/W ADDRESS (5) tSW tHW tSA tHA An An + 1 (1 Latency) An + 2 An + 3 tDC tCD2 DATAOUT Qn (1) tCKLZ OE tHB (6) UB, LB Qn + 2(6) Qn + 1 tOHZ(1) tOLZ(1) (2) tOE 5648 drw 07 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Notes under Pin Names Table. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "X' here denotes Left or Right port. The diagram is with respect to that port. 6.42 8 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Timing Waveform of a Bank Select Pipelined Read(1,2) tCH2 tCYC2 tCL2 CLK tSA tHA A0 ADDRESS(B1) tSC tHC CE0(B1) tSC tHC Q0 DATAOUT(B1) tCD2 Q3 Q1 tDC tDC tSA tCKHZ(3) tCD2 tCD2 tCKLZ (3) tCKHZ (3) tHA A0 ADDRESS(B2) A6 A5 A4 A3 A2 A1 A1 A6 A5 A4 A3 A2 tSC tHC CE0(B2) tSC tHC tCD2 DATAOUT(B2) tCKLZ(3) tCKHZ (3) tCD2 Q2 tCKLZ (3) Q4 5648 drw 08 NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9369 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4) CLK"A" tSW tHW tSA tHA R/W"A " ADDRESS"A" tSD DATAIN"A" NO MATCH MATCH tHD VALID tCO(3) CLK"B" tCD2 R/W"B" ADDRESS"B" tSW tHW tSA tHA NO MATCH MATCH DATAOUT"B" VALID tDC , 5648 drw 09 NOTES: 1. CE0, BEn, and ADS = VIL; CE1 and REPEAT = VIH. 2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to. 3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2). 4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A" 6.42 9 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Timing Waveform with Port-to-Port Flow-Through Read(4,5,7) CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" NO MATCH MATCH tSD DATAIN "A" tHA tHD VALID tCCS (6) CLK "B" tCD1 R/W "B" tSW tHW tHA tSA ADDRESS "B" NO MATCH MATCH tCWDD (6) tCD1 DATAOUT "B" VALID VALID tDC tDC . 5648 drw 10 NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9369 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". 6.42 10 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3) tCYC2 tCH2 tCL2 CLK CE0 tSC tHC CE1 tSB tHB UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD2 (2) tCKHZ (1) (1) tCD2 tCKLZ Qn + 3 Qn DATAOUT (5) READ NOP WRITE READ . 5648 drw 11 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3) tCH2 tCYC2 tCL2 CLK CE0 tSC tHC CE1 tSB tHB UB, LB tSW tHW R/W (4) ADDRESS tSW tHW An tSA tHA An +1 An + 2 An + 3 An + 4 An + 5 tSD tHD DATAIN Dn + 3 Dn + 2 tCD2 (2) tCD2 tCKLZ(1) Qn DATAOUT Qn + 4 tOHZ(1) OE . READ WRITE READ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 11 5648 drw 12 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3) tCH1 tCYC1 tCL1 CLK CE0 tSC tHC CE1 tSB tHB UB, LB tSW tHW R/W tSW tHW (4) ADDRESS tSA An tHA An +1 An + 2 An + 4 An + 3 An + 2 tSD tHD DATAIN Dn + 2 tCD1 (2) tCD1 Qn DATAOUT tCD1 tCD1 Qn + 1 tDC tCKHZ READ NOP (1) Qn + 3 tDC (1) tCKLZ (5) READ WRITE 5648 drw 13 . Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSB tHB UB, LB tSW tHW tSW tHW R/W (4) An tSA tHA ADDRESS An +1 DATAIN (2) DATAOUT An + 2 tSD tHD An + 3 Dn + 2 Dn + 3 tDC tCD1 Qn tOE tCD1 (1) tCKLZ tOHZ(1) An + 5 An + 4 tCD1 Qn + 4 tDC . OE READ WRITE READ NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1 and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 12 5648 drw 14 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 tCYC2 tCL2 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qn + 2(2) Qn + 1 Qn Qx Qn + 3 . tDC READ EXTERNAL ADDRESS READ WITH COUNTER READ WITH COUNTER COUNTER HOLD 5648 drw 15 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCYC1 tCH1 tCL1 CLK tSA ADDRESS tHA An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) Qn Qn + 1 Qn + 2 Qn + 3(2) . Qn + 4 tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 5648 drw 16 NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 13 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1) tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL(3) ADDRESS An(7) An + 2 An + 1 An + 4 An + 3 tSAD tHAD ADS CNTEN(7) tSD tHD Dn + 1 Dn DATAIN WRITE EXTERNAL ADDRESS Dn + 1 Dn + 4 Dn + 3 Dn + 2 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER . 5648 drw 17 Timing Waveform of Counter Reset (Pipelined Outputs)(2) tCYC2 tCH2 tCL2 CLK tSA tHA An ADDRESS(4) INTERNAL(3) ADDRESS Ax(6) 0 1 An + 2 An + 1 An An + 1 tSW tHW R/W ADS tSA D CNTEN tHAD tSCN tHCN tSRST tHRST CNTRST tSD tHD D0 DATAIN DATAOUT(5) Q1 Q0 COUNTER RESET (6) Qn . WRITE ADDRESS 0 READ ADDRESS 0 READ ADDRESS 1 READ ADDRESS n READ ADDRESS n+1 NOTES: 5648 drw 18 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’ Address is written to during this cycle. 6.42 14 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Functional Description Depth and Width Expansion The IDT70V9369 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to staff the operation of the address counters for fast interleaved memory applications. CE0 = VIL and CE1 = VIH for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V9369's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 = VIL and CE1 = VIH to re-activate the outputs. The IDT70V9369 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V9369 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36-bit or wider applications. A14 IDT70V9369 CE0 CE1 Control Inputs IDT70V9369 IDT70V9369 CE1 VDD VDD Control Inputs CE1 IDT70V9369 CE1 CE0 CE0 Control Inputs CE0 Control Inputs 5648 drw 19 Figure 4. Depth and Width Expansion with IDT70V9369 6.42 15 CNTRST CLK ADS CNTEN R/W LB, UB OE 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Ordering Information XXXXX A 99 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tray Tape and Reel Blank Commercial (0°C to +70°C) G Green PF 100-pin TQFP (PNG100) 9 Commercial Only Speed in nanoseconds L Low Power 70V9369 288K (16K x 18-Bit) 3.3V Synchronous Dual-Port RAM 5648 drw 20 NOTES: LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 9 Pkg. Code Pkg. Type Temp. Grade 70V9369L9PFG PNG100 TQFP C 70V9369L9PFG8 PNG100 TQFP C Orderable Part ID 6.42 16 70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Range Datasheet Document History 01/08/02: 10/11/04: Page 4 Page 5 Page 7 10/23/08: 07/26/10: Page 9 Page 16 Page 1 & 16 Page 16 Page 1 Page 16 Page 7 Pages 8-12 06/20/15: Page 2 Page 2 Page 2 & 16 Page 6 Page 16 02/22/18: 11/14/19: Page 2 Page 16 Initial Public Release Removed "Preliminary" status Updated Truth Table II Updated Absolute Maximum Ratings Updated Capacitance table Added 6ns speed grade and 7ns I-temp, removed 9ns I-temp and updated DC power numbers in the DC Electrical Characteristics Table Added 6ns speed grade and 7ns I-temp and removed 9ns I-temp AC timing numbers from the AC Electrical Characteristics Table Updated tOE for 7ns and 9ns speed grades Added Timing Waveform of Left Port Write to Pipelined Right Port Read Added 6ns speed grade and 7ns I-temp and removed 9ns I-temp to ordering information Replaced old TM logo with new TM logo Removed "IDT" from orderable part number Added green parts availability to features Added green indicator to ordering information In order to correct the header notes of the AC Elect Chars Table and align them with the Industrial temp range values located in the table, the commercial TA header note has been removed In order to correct the footnotes of timing diagrams, CNTEN has been removed to reconcile the footnotes witht he CNTEN logic definition found in Truth Table II - Address Counter Control Removed IDT in reference to fabrication Removed date for the 100-PIN TQFP configuration The package code PN100-1 changed to PN100 to match standard package codes Corrected typo in the Typical Output Derating drawing Added Tape and Reel indicator to Ordering Information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Rotated PNG100 TQFP pin configuration to accurately reflect pin 1 orientation Added Orderable Part Information table CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 17 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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