71016S15PHGI8

CMOS Static RAM 1 Meg (64K x 16-Bit) Description Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 71016S The IDT71016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71016 has an output enable pin which operates as fast as 7ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71016 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71016 is packaged in a JEDEC standard 44-pin Plastic SOJ and 44-pin TSOP Type II. 64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times – Commercial : 12/15/20ns – Industrial: 15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTLcompatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Commercial and industrial product available in 44-pin Plastic SOJ package and 44-pin TSOP package Functional Block Diagram OE A0 - A15 Output Enable Buffer Address Buffers Row / Column Decoders I/O 15 CS 8 Chip Enable Buffer High Byte I/O Buffer 8 I/O 8 WE Write Enable Buffer 16 64K x 16 Memory Array Sense Amps and Write Drivers I/O 7 8 Low Byte I/O Buffer 8 I/O 0 BHE Byte Enable Buffers BLE 3210 drw 01 1 Jun.02.20 , 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Pin Configurations(1) Pin Descriptions A0 - A15 Address Inputs Input A4 1 44 A5 CS Chip Select Input A3 2 43 A6 A2 3 Write Enable Input A7 WE 42 A1 4 41 OE OE Output Enable Input BHE High Byte Enable Input BLE Low Byte Enable Input A0 5 40 BHE CS 6 39 BLE I/O 0 7 38 I/O 15 I/O 1 8 37 I/O 14 I/O0 - I/O15 Data Input/Output I/O VCC 5.0V Power Pwr VSS Ground Gnd 71016 PBG44 PHG44 I/O 2 9 36 I/O 13 I/O 3 10 35 I/O 12 VCC 11 34 VSS VSS 12 33 VCC I/O 4 13 32 I/O 11 I/O 5 14 31 I/O 10 I/O 6 15 30 I/O 9 I/O 7 16 29 I/O 8 WE 17 28 NC A15 18 27 A8 A14 19 26 A9 A13 20 25 A10 A12 21 24 A11 NC 22 23 NC SOJ/TSOP Top View 3210 tbl 01 , 3210 drw 02 NOTE: 1. This text does not indicate orientation of actual part-marking. Truth Table (1) CS OE WE BLE BHE I/O0 - I/O7 I/O8 - I/O15 Function H X X X X High-Z High-Z Deselected - Standby L L H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATAOUT High Byte Read L L H L L DATAOUT DATAOUT` Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled 3210 tbl 02 NOTE: 1. H = VIH, L = VIL, X = Don't care. 6.42 2 Jun.02.20 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Value Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -55 to +125 o C PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA Recommended Operating Temperature and Supply Voltage Grade Temperature GND VCC Commercial 0°C to +70°C 0V 5.0V ± 10% Industrial –40°C to +85°C 0V 5.0V ± 10% 3210 tbl 04 Recommended DC Operating Conditions Symbol 3210 tbl 03a NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. Parameter VCC Supply Voltage GND Ground Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VIH Input High Voltage 2.2 ____ VDD +0.5 V VIL Input Low Voltage -0.5(1) ____ 0.8 V 3210 tbl 05 NOTE: 1. VIL (min.) = –1.5V for pulse width less than tRC/2, once per cycle. Capacitance (TA = +25° C, f = 1.0MHz, SOJ/TSOP Package) Parameter(1) Symbol CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 3dV 6 pF VOUT = 3dV 7 pF 3210 tbl 06 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. DC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Temperature Range) Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC ___ 5 µA |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to VCC ___ 5 µA VOL Output Low Voltage IOL = 8mA, VCC = Min. ___ 0.4 V VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4 ___ V 3210 tbl 07 DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V) 71016S12 Symbol Parameter 71016S15 71016S20 Com'l. Com'l. Ind. Com'l. Ind. Unit ICC Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) 210 180 180 170 170 mA ISB Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VCC = Max., F = fMAX(2) 60 50 50 45 45 mA ISB1 Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, V CC = Max., f = 0(2) VIN < VLC or VIN > VHC 10 10 10 10 10 mA NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing . 6.42 3 Jun.02.20 3210 tbl 08 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges AC Test Conditions GND to 3.0V Input Pulse Levels Input Rise/Fall Times 1.5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V See Figure 1, 2 and 3 AC Test Load 3210 tbl 09 AC Test Loads 5V 5V 480Ω 480Ω DATA OUT 30pF* DATA OUT 255Ω 5pF* 255Ω , 3210 drw 03 3210 drw 04 *Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) Figure 1. AC Test Load 7 • 6 ΔtAA, tACS (Typical, ns) 5 4 • 3 • 2 • 1 • • • , 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) Figure 3. Output Capacitive Derating 6.42 4 Jun.02.20 3210 drw 05 , 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Range) 71016S12 (2) Symbol Parameter 71016S15 71016S20 Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 ____ 15 ____ 20 ____ ns tAA Address Access Time ____ 12 ____ 15 ____ 20 ns tACS Chip Select Access Time ____ 12 ____ 15 ____ 20 ns tCLZ(1) Chip Select Low to Output in Low-Z 4 ____ 5 ____ 5 ____ ns tCHZ(1) Chip Select High to Output in High-Z ____ 6 ____ 6 ____ 8 ns tOE Output Enable Low to Output Valid ____ 7 ____ 8 ____ 10 ns 0 ____ 0 ____ 0 ____ ns ____ 6 ____ 6 ____ 8 ns 4 ____ 4 ____ 5 ____ ns ____ 7 ____ 8 ____ 10 ns 0 ____ 0 ____ 0 ____ ns 6 ____ 6 ____ 8 ns (1) tOLZ Output Enable Low to Output in Low-Z tOHZ(1) Output Enable High to Output in High-Z tOH Output Hold from Address Change tBE Byte Enable Low to Output Valid tBLZ(1) Byte Enable Low to Output in Low-Z tBHZ(1) Byte Enable High to Output in High-Z ____ tWC Write Cycle Time 12 ____ 15 ____ 20 ____ ns tAW Address Valid to End of Write 9 ____ 10 ____ 12 ____ ns tCW Chip Select Low to End of Write 9 ____ 10 ____ 12 ____ ns tBW Byte Enable Low to End of Write 9 ____ 10 ____ 12 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Address Hold from End of Write 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 9 ____ 10 ____ 12 ____ ns tDW Data Valid to End of Write 7 ____ 8 ____ 10 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tOW Write Enable High to Output in Low-Z 1 ____ 1 ____ 1 ____ ns tWHZ(1) Write Enable Low to Output in High-Z ____ 6 ____ 6 ____ 8 ns WRITE CYCLE (1) 3210 tbl 10 NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. 12ns commercial only. Timing Waveform of Read Cycle No. 1(1,2,3) tRC ADDRESS tAA tOH DATAOUT tOH DATAOUT VALID PREVIOUS DATAOUT VALID 3210 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 6.42 5 Jun.02.20 , 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2(1) tRC ADDRESS tAA tOH OE tOE tOLZ CS tCLZ (3) tOHZ , (3) (3) tACS (2) tCHZ (3) BHE, BLE (2) tBE tBLZ tBHZ (3) DATAOUT (3) DATA OUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured ±200mV from steady state. 3210 drw 07 Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tCW (2) tCHZ (5) tBW BHE , BLE tWR WE tAS tWHZ DATAOUT tBHZ (5) tWP PREVIOUS DATA VALID (5) tOW (3) (5) DATA VALID tDW DATAIN , tDH DATAIN VALID 3210 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 6 Jun.02.20 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tCW (2) tAS tBW BHE , BLE tWP tWR WE , DATAOUT tDH tDW DATAIN DATAIN VALID 3210 drw 9 Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tCW (2) tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 3210 drw 10 , NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 7 Jun.02.20 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Ordering Information 71016 S XX XXX Device Type Power Speed Package X X X Process/ Temperature Range Blank 8 Tube Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green Y PH 400-mil SOJ (PBG44) 400-mil TSOP Type II (PHG44) 12* 15 20 Speed in nanoseconds 3210 drw 11 NOTE: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. Orderable Part Information Speed (ns) 12 15 20 Pkg. Code Pkg. Type Temp. Grade 71016S12PHG PHG44 TSOP C 71016S12PHG8 PHG44 TSOP C 71016S12YG PBG44 SOJ C 71016S12YG8 PBG44 SOJ C 71016S15PHG PHG44 TSOP C 71016S15PHG8 PHG44 TSOP C Orderable Part ID 71016S15PHGI PHG44 TSOP I 71016S15PHGI8 PHG44 TSOP I 71016S15YG PBG44 SOJ C 71016S15YG8 PBG44 SOJ C 71016S15YGI PBG44 SOJ I 71016S15YGI8 PBG44 SOJ I 71016S20PHG PHG44 TSOP C 71016S20PHG8 PHG44 TSOP C 71016S20PHGI PHG44 TSOP I 71016S20PHGI8 PHG44 TSOP I 71016S20YG PBG44 SOJ C 71016S20YG8 PBG44 SOJ C 71016S20YGI PBG44 SOJ I 71016S20YGI8 PBG44 SOJ I 6.42 8 Jun.02.20 *Commercial temperature range only 71016 CMOS Static RAM 1 Meg (64K x 16-bit) Commercial and Industrial Temperature Ranges Datasheet Document History 07/30/99: 080/5/99: Pg. 3 Pg. 5 Pg. 6 Pg. 7 Pg. 8 08/13/99: 09/30/99: 08/09/00: 02/01/01: 01/30/04: 01/30/06: 02/13/07: 10/13/08: 09/25/13: Pg. 9 Pg. 3, 5, 8 Pg. 8 Pg. 3 Pg. 8 Pg. 8 Pg. 1 Pg. 3 Pg. 5 Pg. 8 06/02/20: Pg. 1 - 10 Pg. 2 & 8 Pg. 8 Pg. 8 Updated to new format Expressed commercial and industrial ranges on DC Electrical table Removed Icc, ISB, and ISB1 values for S12 industrial speed Expressed commercial and industrial ranges on AC Electrical table Changed footnote #2 to commercial temperature only Revised footnotes on Write Cycle No.1 diagram Revised footnotes on Write Cycle No.2 and No.3 diagrams Removed SCD 2752 footnote Added commercial only for 12ns speed Added Datasheet Document History Added 12ns industrial temperature speed grade offering Not recommended for new designs Removed "Not recommended for new designs" Added "Restricted hazardous substance device" to order information Updated Capacitance table to include TSOP Added N generation die step to data sheet ordering information Removed "IDT" from orderable part number Updated Commercial and Industrial speed grade offerings Removed IDT reference to fabrication Removed Commercial TA information from the Absolute Maximum Ratings table Removed Ind. temp values for the 12ns speed grade from the DC Elec Chars table Added the footnote annotation to the AC Elec Chars table and the footnote for 12ns commercial only Added T & R to, updated Restricted Hazardous Substance Device wording to "Green", added annotation indicating "Commercial temperature range only" and removed Die Stepping indicator from the ordering information Rebranded as Renesas datasheet Updated package codes Added Industrial temp footnote to Ordering Information Added Orderable Part Information table 6.42 9 Jun.02.20 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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