71256SA20YG8

CMOS Static RAM 256K (32K x 8-Bit) Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 71256SA Description 32K x 8 advanced high-speed CMOS static RAM Commercial (0° to 70°C) and Industrial (-40° to 85°C) temperature options Equal access and cycle times – Commercial: 12ns – Commercial and Industrial: 15/20/25ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTL-compatible Low power consumption via chip deselect Commercial product available in 28-pin 300-mil Plastic DIP, 300 mil Plastic SOJ and TSOP packages Industrial product available in 28-pin 300 mil Plastic SOJ and TSOP packages Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information The IDT71256SA is a 262,144-bit high-speed Static RAM organized as 32K x 8. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. . The IDT71256SA has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71256SA are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71256SA is packaged in 28-pin 300-mil Plastic DIP, 28-pin 300 mil Plastic SOJ and TSOP. Functional Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 262,144-BIT MEMORY ARRAY ADDRESS DECODER , I/O0 - I/O7 8 8 I/O CONTROL 2948 drw 01 CS WE OE CONTROL LOGIC 1 Jun.29.20 71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Pin Configurations(1) Symbol A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 28 2 27 3 26 4 25 5 24 6 7 8 71256SA PJG28 PTG28 9 10 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 23 22 21 20 11 19 18 12 17 13 16 14 15 22 21 23 20 24 19 25 18 17 27 16 71256SA PZG28 28 1 15 14 2 13 3 12 4 11 5 10 6 9 7 Unit VCC Supply Voltage Relative to GND -0.5 to +7.0 V VTERM Terminal Voltage Relative to GND -0.5 to VCC+0.5 V TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -55 to +125 o C PT Power Dissipation 1.0 IOUT DC Output Current 50 W mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DIP/SOJ Top View 26 Value 2948 tbl 02 2948 drw 02 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 Rating 8 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 Truth Table(1,2) , 2948 drw 02a TSOP Top View CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Outputs Disabled H X X High-Z Deselecte d - Standby (ISB) VHC(3) X X High-Z Deselecte d - Standby (ISB1) Function 2948 tbl 03 NOTES: 1. H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC –0.2V. 3. Other inputs ≥VHC or ≤VLC. NOTE: 1. This text does not indicate orientation of actual part-marking. Recommended DC Operating Conditions Symbol Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial VCC Supply Voltage GND Ground Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V V Temperature GND Vcc VIH Input High Voltage 2.2 ____ VCC +0.5 0 C to +70 C 0V 4.5V ± 5.5V VIL Input Low Voltage -0.5(1) ____ 0.8 -40OC to +85OC 0V 4.5V ± 5.5V O O NOTE: 1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle. 2948 tbl 01 2 Jun.29.20 Parameter V 2948 tbl 04 71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5.0V ± 10%) IDT71256SA Symbol Parameter Test Conditions Min. Max. Unit 5 µA |ILI| Input Leakage Current VCC = Max., VIN = GND to VCC ___ |ILO| Output Leakage Current VCC = Max., CS = VIH, VOUT = GND to V CC ___ 5 µA VOL Output Low Voltage IOL = 8mA, VCC = Min. ___ 0.4 V VOH Output High Voltage IOH = -4mA, VCC = Min. 2.4 ___ V 2948 tbl 05 DC Electrical Characteristics(1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V) Symbol Parameter 71256SA12 71256SA15 71256SA20 71256SA25 Unit ICC Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., f = fMAX(2) 160 150 145 145 mA ISB Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open, VCC = Max., f = fMAX(2) 50 40 40 40 mA ISB1 Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VCC = Max., f = 0(2), VIN < VLC or VIN > VHC 15 15 15 15 mA 2948 tbl 06 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. Capacitance AC Test Conditions Input Pulse Levels (TA = +25°C, f = 1.0MHz, SOJ package) GND to 3.0V Parameter(1) Symbol Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V CIN Input Capacitance Output Reference Levels 1.5V CI/O I/O Capacitance AC Test Load See Figures 1 and 2 Max. Unit VIN = 3dV 7 pF VOUT = 3dV 7 pF 2948 tbl 08 2948 tbl 07 NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 5V 5V 480Ω 480Ω DATA OUT DATA OUT 30pF* 5pF* 255Ω 2948 drw 03 255Ω . , 2948 drw 04 Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) *Including jig and scope capacitance. 6.42 3 Jun.29.20 Conditions 71256SA CMOS Static RAM 256K (32K x 8-Bit) AC Electrical Characteristics Commercial and Industrial Temperature Ranges (VCC = 5.0V ± 10%) 71256SA12 Symbol Parameter 71256SA15 71256SA20 71256SA25 Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 12 ____ 15 ____ 20 ____ 25 ____ ns tAA Address Access Time ____ 12 ____ 15 ____ 20 ____ 25 ns tACS Chip Select Access Time ____ 12 ____ 15 ____ 20 ____ 25 ns tCLZ(1) Chip Select to Output in Low-Z 4 ____ 4 ____ 4 ____ 4 ____ ns tCHZ(1) Chip Sele ct to Output in High-Z tOE Output Enable to Output Valid tOLZ(1) 0 6 0 7 0 10 0 11 ns ____ 6 ____ 7 ____ 10 ____ 11 ns Output Enab le to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tOHZ(1) Output Disab le to Output in High-Z 0 6 0 6 0 8 0 10 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ 3 ____ ns tPU(1) Chip Sele ct to Power Up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tPD(1) Chip Deselect to Power Down Time ____ 12 ____ 15 ____ 20 ____ 25 ns Write Cycle tWC Write Cycle Time 12 ____ 15 ____ 20 ____ 25 ____ ns tAW Address Valid to End-of-Write 9 ____ 10 ____ 15 ____ 20 ____ ns tCW Chip Select to End-of-Write 9 ____ 10 ____ 15 ____ 20 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 8 ____ 10 ____ 15 ____ 20 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 6 ____ 7 ____ 11 ____ 13 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ 0 ____ ns tOW(1) Output Active from End-of-Write 4 ____ 4 ____ 4 ____ 4 ____ ns tWHZ(1) Write Enab le to Output in High-Z 0 6 0 6 0 10 0 11 ns NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 4 Jun.29.20 2948 tbl 09 71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE tOLZ CS (5) tACS tCLZ tOHZ tCHZ HIGH IMPEDANCE DATAOUT VCC SUPPLY CURRENT (3) (5) ICC (5) (5) DATA OUT VALID tPD tPU ISB 2948 drw 05 , Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH DATAOUT tOH DATAOUT VALID PREVIOUS DATAOUT VALID 2948 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6.42 5 Jun.29.20 , 71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tWP (2) tAS tWR WE tWHZ (5) DATAOUT (5) tOW HIGH IMPEDANCE (3) tDW DATAIN tCHZ (5) (3) tDH DATAIN VALID 2948 drw 07 , Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4) tWC ADDRESS tAW CS tAS tWR tCW WE tDW DATAIN tDH DATAIN VALID 2948 drw 08 , NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6 Jun.29.20 71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Ordering Information 71256 SA XX Device Power Speed Type XXX X Package X X Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I(2) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green TP Y PZ 300-mil Plastic DIP (PTG28) 300-mil SOJ (PJG28) TSOP Type I (PZG28) 12(1) 15 20 25 Speed in nanoseconds 2948 drw 09 NOTES: 1. Available in commercial temperature range only. 2. Contact your local sales office for Industrial temp range for other speeds, packages and powers. Orderable Part Information Pkg. Code Pkg. Type Temp. Grade Speed (ns) 71256SA12PZG PZG28 TSOP C 20 71256SA12PZG8 PZG28 TSOP Speed (ns) 12 15 Orderable Part ID Pkg. Code Pkg. Type Temp. Grade 71256SA20PZG PZG28 TSOP C C 71256SA20PZG8 PZG28 TSOP C PZG28 TSOP I Orderable Part ID 71256SA12TPG PTG28 PDIP C 71256SA20PZGI 71256SA12YG PJG28 SOJ C 71256SA20PZGI8 PZG28 TSOP I 71256SA12YG8 PJG28 SOJ C 71256SA20TPG PTG28 PDIP C 71256SA20TPGI PTG28 PDIP I 71256SA20YG PJG28 SOJ C 71256SA20YG8 PJG28 SOJ C 71256SA15PZG PZG28 TSOP C 71256SA15PZG8 PZG28 TSOP C 71256SA15PZGI PZG28 TSOP I 71256SA15PZGI8 PZG28 TSOP I 71256SA15TPG PTG28 PDIP C 71256SA15TPGI PTG28 PDIP I 71256SA15YG PJG28 SOJ C 71256SA15YG8 PJG28 SOJ 71256SA15YGI PJG28 71256SA15YGI8 PJG28 71256SA20YGI PJG28 SOJ I 71256SA20YGI8 PJG28 SOJ I 71256SA25PZG PZG28 TSOP C 71256SA25PZG8 PZG28 TSOP C 71256SA25PZGI PZG28 TSOP I C 71256SA25PZGI8 PZG28 TSOP I SOJ I 71256SA25TPG PTG28 PDIP C SOJ I 71256SA25TPGI PTG28 PDIP I 71256SA25YG PJG28 SOJ C 71256SA25YG8 PJG28 SOJ C 25 6.42 7 Jun.29.20 71256SA CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges Datasheet Document History 1/7/00 Pg. 1, 3, 4, 7 Pg. 6 Pg. 8 08/09/00 02/01/01 09/30/04 02/20/07 04/28/11 Pg. 7 Pg. 7 Pg. 1, 2, 7 11/03/14 Pg. 1 & 8 06/29/20 Pg. 2 & 8 Pg. 1 - 9 Pg. 1 & 7 Pg. 2 & 7 Pg. 7 Updated to new format Revised Industrial Temperature range offerings Removed Note No. 1 for Write Cycle diagrams, renumbered footnotes and notes Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" Added "Restricted hazardous substance device" to ordering informations. Added TT generation die step to data sheet ordering information. Obsoleted 28-pin 600 mil and removed TT generation die step from Ordering information. Added Tape and Reel to Ordering information and updated description of Restricted hazardous substance device to Green Removed 12ns I-temp offering in Features. Added note regarding 12ns commercial only on the Ordering information page. Removed IDT as a reference for fabrication in Description. Removed package extensions from pinouts and from Ordering information. Rebranded as Renesas datasheet Updated Industrial temp range and green availability Updated package codes Added Orderable Part Information tables 8 Jun.29.20 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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