HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
Features
◆
◆
◆
◆
High-speed access
– Commercial: 20/35/55ns (max.)
– Industrial: 25/55ns (max.)
Low-power operation
– IDT71321/IDT71421SA
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71321/421LA
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
Two INT flags for port-to-port communications
◆
◆
◆
◆
◆
◆
◆
◆
71321SA/LA
71421SA/LA
MASTER IDT71321 easily expands data bus width to 16-ormore-bits using SLAVE IDT71421
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and
64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O
Control
I/O0R-I/O7R
I/O
Control
(1,2)
(1,2)
BUSYL
A10L
A0L
BUSYR
Address
Decoder
MEMORY
ARRAY
11
CEL
OEL
R/WL
Address
Decoder
A10R
A0R
11
ARBITRATION
and
INTERRUPT
LOGIC
CER
OER
R/WR
(2)
(2)
INTR
INTL
2691 drw 01
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
SEPTEMBER 2019
1
©2019 Integrated Device Technology, Inc.
DSC-2691/17
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit DualPort Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM approach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCC,
52-pin STQFP, 64-pin TQFP, and 64-pin STQFP.
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PLG52 package body is approximately .75 in x .75 in x .17 in.
PNG64 package body is approximately 14mm x 14mm x 1.4mm.
PPG64 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
A0L
OE L
A10L
INTL
BUSYL
R/WL
CE L
V CC
CE R
R/WR
BUSYR
INTR
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
N/C
A7R
A8R
A9R
N/C
N/C
I/O7R
I/O6R
2691 drw 02
N/C
N/C
A10R
INTR
BUSYR
R/WR
CER
VCC
VCC
CEL
R/WL
BUSYL
INTL
A10L
N/C
N/C
48 4746 45444342 41 40 39 38 3736 3534 33
32
49
50
31
51
30
52
29
53
28
54
27
55
26
71321/421
PNG64/PPG64(4)
56
25
24
57
64-Pin TQFP
58
23
64-Pin STQFP
59
22
Top View
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I/O5R
I/O4R
N/C
I/O3R
I/O2R
I/O1R
I/O0R
GND
GND
N/C
I/O7L
I/O6L
I/O5L
I/O4L
N/C
I/O3L
2691 drw 03
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
N/C
A7L
A8L
A9L
N/C
I/O0L
I/O1L
I/O2L
I/O7R
NC
A 9R
A 8R
I/O 1R
I/O 2R
I/O 3R
I/O 4R
I/O 5R
I/O 6R
20 19 18 17 16 15 14 13 12 11 10 9 8
7
21
6
22
5
23
4
24
3
25
2
26
1
27
71321/421
PLG52(4)
52
28
PLCC
51
29
Top View
50
30
49
31
48
32
47
33
34 35 36 37 38 39 40 41 42 43 44 45 46
A 7R
A 6R
A 5R
A 4R
A 3R
A 2R
A 1R
A 0R
OER
I/O 4L
I/O 5L
I/O 6L
I/O 7L
NC
GND
I/O 0R
I/O1L
I/O 0L
A9L
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
I/O 3L
I/O 2L
Pin Configurations(1,2,3)
2
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
A9R
N/C
I/O7R
A7R
A8R
24
I/O4R
43
44
71321
45
PPG52(4)
46
52-Pin STQFP
47
Top View
48
49
50
51
52
1 2 3 4 5 6 7 8 9 10 11 12
23
22
I/O3R
I/O2R
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
CEL
R/WL
BUSYL
INTL
A10L
OEL
A0L
42
I/O1L
R/WR
CER
VCC
I/O6R
I/O5R
21
20
19
18
17
16
15
14
13
I/O1R
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. PPG52 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
I/O0R
GND
N/C
I/O7L
I/O6L
I/O5L
I/O4L
2691 drw 03a
I/O2L
I/O3L
BUSYR
39 38 37 36 35 34 33 32 31 30 29 28 27
26
40
25
41
A9L
I/O0L
A10R
INTR
A0R
A1R
A2R
A3R
A4R
A5R
A6R
OER
Pin Configurations (continued)(1,2,3)
Recommended Operating
Temperature and Supply Voltage(1,2)
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
Grade
Commercial
Industrial
2691 tbl 00
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
TBIAS
Temperature
Under Bias
-55 to +125
o
TSTG
IOUT
Storage
Temperature
DC Output
Current
-65 to +150
50
o
GND
Vcc
0OC to +70OC
0V
5.0V + 10%
-40 C to +85 C
0V
5.0V + 10%
O
O
2691 tbl 02
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Recommended DC Operating
Conditions
Symbol
VTERM(2)
Ambient
Temperature
C
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
VIL
C
Parameter
Input Low Voltage
Min.
Typ.
Max.
Unit
4.5
5.0
5.5
V
0
0
0
V
2.2
____
(1)
-0.5
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
mA
2691 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3
6.42
____
(2)
6.0
0.8
V
V
2691 tbl 03
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4) (VCC = 5.0V ± 10%)
71321X20
71421X20
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
71321X25
71421X25
Com'l
& Ind
Typ.
Max.
Typ.
Max.
Unit
COM'L
SA
LA
110
110
250
200
110
110
220
170
mA
IND
SA
LA
____
____
____
____
110
110
270
220
COM'L
SA
LA
30
30
65
45
30
30
65
45
IND
SA
LA
____
____
____
____
30
30
75
55
COM'L
SA
LA
65
65
165
125
65
65
150
115
IND
SA
LA
____
____
____
____
65
65
170
140
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(2)
COM'L
SA
LA
60
60
155
115
60
60
145
105
IND
SA
LA
____
____
____
____
60
60
165
130
CEL and CER = VIL,
Outputs Disabled
f = fMAX(2)
CEL and CER = VIH
f = fMAX(2)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(2)
mA
mA
mA
mA
2691 tbl 04a
71321X35
71421X35
Com'l Only
Symbol
ICC
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CEL and CER = VIL,
Outputs Disabled
f = fMAX(2)
CEL and CER = VIH
f = fMAX(2)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f=fMAX(2)
CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(2)
71321X55
71421X55
Com'l
& Ind
Typ.
Max.
Typ.
Max.
Unit
mA
COM'L
SA
LA
80
80
165
120
65
65
155
110
IND
SA
LA
____
____
____
____
65
65
190
140
COM'L
SA
LA
25
25
65
45
20
20
65
35
IND
SA
LA
____
____
____
____
20
20
70
50
COM'L
SA
LA
50
50
125
90
40
40
110
75
IND
SA
LA
____
____
____
____
40
40
125
90
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
COM'L
SA
LA
45
45
110
85
40
40
100
70
IND
SA
LA
____
____
____
____
40
40
110
85
mA
mA
mA
mA
2691 tbl 04b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
4
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
71321SA
71421SA
Symbol
Parameter
Test Conditions
(1)
71321LA
71421LA
Min.
Max.
Min.
Max.
Unit
10
___
5
µA
|ILI|
Input Leakage Current
VCC = 5.5V, VIN = 0V to V CC
___
|ILO|
Output Leakage Current(1)
CE = VIH, VOUT = 0V to V CC,
VCC - 5.5V
___
10
___
5
µA
VOL
Output Low Voltage (I/O0-I/O7)
IOL = 4mA
___
0.4
___
0.4
V
VOL
Open Drain Output
Low Voltage (BUSY/INT)
IOL = 16mA
___
0.5
___
0.5
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
2691 tbl 05
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol
Parameter
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR(3)
(3)
tR
Test Condition
Min.
Typ.(1)
Max.
Unit
2.0
____
____
V
VCC = 2.0V, CE > VCC - 0.2V
COM'L
____
100
1500
µA
VIN > VCC - 0.2V or VIN < 0.2V
IND
____
100
4000
µA
0
____
____
ns
____
____
ns
Chip Deselect to Data Retention Time
(2)
Operation Recovery Time
tRC
2691 tbl 06
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
VDR ≥ 2.0V
tCDR
4.5V
tR
VDR
CE
VIH
VIH
,
2691 drw 04
5
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
Figures 1,2 and 3
2691 tbl 07
5V
5V
1250Ω
1250Ω
DATA OUT
DATA OUT
775Ω
30pF*
775Ω
5pF*
*100pF for 55ns versions
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
5V
270Ω
BUSY or INT
2691 drw 05
30pF*
*100pF for 55ns versions
Figure 3. BUSY and INT
AC Output Test Load
6
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(2)
71321X25
71421X25
Com'l
& Ind
71321X20
71421X20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
ns
tAA
Address Access Time
____
20
____
25
ns
tACE
Chip Enable Access Time
____
20
____
25
ns
tAOE
Output Enable Access Time
____
11
____
12
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
0
____
0
____
ns
____
10
____
10
ns
0
____
0
____
ns
____
20
____
25
ns
tLZ
Output Low-Z Time
tHZ
(1,3)
Output High-Z Time
tPU
(1,3)
Chip Enable to Power Up Time
(3)
Chip Disable to Power Down Time
tPD
(3)
2691 tbl 08a
71321X35
71421X35
Com'l Only
Symbol
Parameter
71321X55
71421X55
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
ns
tAA
Address Access Time
____
35
____
55
ns
tACE
Chip Enable Access Time
____
35
____
55
ns
tAOE
Output Enable Access Time
____
20
____
25
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time (1,3)
0
____
5
____
ns
tHZ
Output High-Z Time (1,3)
____
15
____
25
ns
0
____
0
____
ns
____
35
____
50
ns
tPU
tPD
Chip Enable to Power Up Time
(3)
Chip Disable to Power Down Time
(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. 'X' in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
7
6.42
2691 tbl 08b
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tOH
tAA
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2691 drw 06
tBDDH (2,3)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side (3)
tACE
CE
tAOE
(4)
tHZ (2)
OE
tHZ (2)
tLZ(1)
VALID DATA
DATAOUT
tLZ
ICC
CURRENT
ISS
(1)
tPD
tPU
50%
(4)
50%
2691 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
8
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
71321X25
71421X25
Com'l
& Ind
71321X20
71421X20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time (2)
20
____
25
____
ns
tEW
Chip Enable to End-of-Write
15
____
20
____
ns
tAW
Address Valid to End-of-Write
15
____
20
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
ns
(3)
tWP
Write Pulse Width
15
____
15
____
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
12
____
ns
____
10
____
10
ns
0
____
0
____
ns
tHZ
Output High-Z Time
tDH
Data Hold Time
(1)
(1)
tWZ
Write Enable to Output in High-Z
____
10
____
10
ns
tOW
Output Active from End-of-Write (1)
0
____
0
____
ns
2691 tbl 09a
71321X55
71421X55
Com'l
& Ind
71321X35
71421X35
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time (2)
35
____
55
____
ns
tEW
Chip Enable to End-of-Write
30
____
40
____
ns
tAW
Address Valid to End-of-Write
30
____
40
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
(3)
tWP
Write Pulse Width
25
____
30
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
20
____
ns
tHZ
Output High-Z Time (1)
____
15
____
25
ns
tDH
Data Hold Time
0
____
0
____
ns
____
15
____
30
ns
0
____
0
____
tWZ
tOW
(1)
Write Enable to Output in High-Z
Output Active from End-of-Write
(1)
ns
2691 tbl 09b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
4. 'X' in part numbers indicates power rating (SA or LA).
9
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
tHZ(7)
OE
tAW
CE
tAS(6)
tWR(3)
tWP(2)
tHZ(7)
R/W
tWZ(7)
tOW
(4)
DATA OUT
(4)
tDW
tDH
DATA IN
2691 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
tAW
CE
tAS(6)
tEW(2)
(3)
tWR
R/W
tDW
tDH
DATA IN
2691 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
10
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
71321X25
71421X25
Com'l
& Ind
71321X20
71421X20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY Access Time from Address
____
20
____
20
ns
BUSY Disable Time from Address
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable
____
20
____
20
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
ns
____
50
____
50
ns
____
35
____
35
ns
5
____
5
____
ns
____
25
____
35
ns
0
____
0
____
ns
12
____
15
____
ns
____
40
____
50
ns
____
30
____
35
BUSY TIMING (For MASTER 71321)
tBAA
tBDA
(1)
tWDD
Write Pulse to Data Delay
tDDD
Write Data Valid to Read Data Delay (1)
tAPS
tBDD
Arbitration Priority Set-up Time
(2)
(3)
BUSY Disable to Valid Data
BUSY INPUT TIMING (For SLAVE 71421)
Write to BUSY Input(4)
tWB
tWH
(5)
Write Hold After BUSY
(1)
tWDD
Write Pulse to Data Delay
tDDD
Write Data Valid to Read Data Delay (1)
ns
2691 tbl 10a
71321X35
71421X35
Com'l Only
Symbol
Parameter
71321X55
71421X55
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
BUSY Access Time from Address
____
20
____
30
ns
tBDA
BUSY Disable Time from Address
____
20
____
30
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
30
ns
BUSY Disable Time from Chip Enable
____
20
____
30
ns
ns
BUSY TIMING (For MASTER 71321)
tBAA
tBDC
(5)
tWH
Write Hold After BUSY
20
____
20
____
tWDD
Write Pulse to Data Delay(1)
____
60
____
80
ns
tDDD
Write Data Valid to Read Data Delay (1)
____
35
____
55
ns
5
____
5
____
ns
____
35
____
50
ns
0
____
0
____
ns
20
____
20
____
ns
____
60
____
80
ns
____
35
____
55
ns
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data(3)
(2)
BUSY INPUT TIMING (For SLAVE 71421)
tWB
tWH
Write to BUSY Input(4)
(5)
Write Hold After BUSY
(1)
tWDD
Write Pulse to Data Delay
tDDD
Write Data Valid to Read Data Delay (1)
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA)..
11
6.42
2691 tbl 10b
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W "A"
tDW
DATA IN "A"
tDH
VALID
tAPS(1)
MATCH
ADDR"B"
tBAA
tBDD
tBDA
BUSY"B"
tWDD
DATAOUT"B"
VALID
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT71421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
2691 drw 10
Timing Waveform of Write with BUSY(4)
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH (1)
R/W"B"
,
(2)
2691 drw 11
NOTES:
1. tWH must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version (IDT71421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
12
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR "A"
AND "B"
ADDRESSES MATCH
CE"B"
tAPS(2)
CE"A"
tBAC
tBDC
BUSY"A"
2691 drw 12
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing(1)
tRC or tWC
ADDR"A"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
tAPS
ADDR"B"
tBAA
tBDA
BUSY"B"
2691 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT71321 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
71321X20
71421X20
Com'l Only
Symbol
Parameter
71321X25
71421X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tINS
Interrupt Set Time
____
20
____
25
ns
tINR
Interrupt Reset Time
____
20
____
25
ns
2691 tbl 11a
NOTE:
1. 'X' in part numbers indicates power rating (SA or LA).
13
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(1)
71321X35
71421X35
Com'l Only
Symbol
Parameter
71321X55
71421X55
Com'l
& Ind
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tINS
Interrupt Set Time
____
25
____
45
ns
tINR
Interrupt Reset Time
____
25
____
45
ns
2691 tbl 11b
NOTE:
1. 'X' in part numbers indicates power rating (SA or LA).
Timing Waveform of Interrupt Mode(1)
Set INT
tWC
ADDR"A"
INTERRUPT ADDRESS
(2)
tWR (4)
tAS (3)
R/W"A"
tINS (3)
INT"B"
2691 drw 14
Clear INT
tRC
(2)
ADDR"B"
INTERRUPT CLEAR ADDRESS
tAS(3)
OE"B"
tINR(3)
,
INT"B"
2691 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
14
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables
Truth Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
CE
OE
D0-7
Function
X
H
X
Z
Port Disabled and in Power-Down Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
L
L
X
DATAIN
H
L
L
DATAOUT
H
L
H
Z
Data on Port Written Into Memory(2)
Data in Memory Output on Port(3)
High Impedance Outputs
2691 tbl 12
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II. Interrupt Flag(1,4)
Left Port
R/WL
CEL
L
OEL
L
X
X
X
X
L
INTL
7FF
X
X
X
A10L-A0L
X
X
X
Right Port
L
X
OER
X
A10R-A0R
X
INTR
Function
(2)
Set Right INTR Flag
(3)
L
X
L
L
7FF
H
Reset Right INTR Flag
L
L
X
7FE
X
Set Left INTL Flag
(2)
X
X
X
X
X
Reset Left INTL Flag
L
7FE
X
CER
(3)
X
X
R/WR
H
2691 tbl 13
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Truth Table III — Address BUSY Arbitration
Inputs
Outputs
CEL
CER
A0L-A10L
A0R-A10R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2691 tbl 14
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSYX outputs on the IDT71321 are open drain, not pushpull outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
15
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Functional Description
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CER = R/WR = VIL, per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag (INTR) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an SRAM array in width while using BUSY logic, one
master part is used to decide which side of the SRAM array will receive
a BUSY indication, and to output that indication. Any number of slaves to
be addressed in the same address range as the master, use the BUSY
signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs
the BUSY pin is an output if the part is Master (IDT71321), and the BUSY
pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.
5V
270Ω
MASTER
Dual Port
SRAM
BUSYL
MASTER
Dual Port
SRAM
BUSYL
BUSYL
Busy Logic
CE
BUSYR
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
DECODER
The IDT71321/IDT71421 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT71321/IDT71421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
5V
270Ω
CE
BUSYR
BUSYR
2691 drw 16
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. In slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT71321 (Master) are open drain type
outputs and require open drain resistors to operate. If these SRAMs are
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
16
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
XXXX
A
999
A
Device Type Power Speed Package
A
A
Process/
Temperature
Range
A
Blank
8
Tube or Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
J
PF
PP
TF
52-pin PLCC (PLG52)
64-pin TQFP (PNG64)
52-pin STQFP (PPG52)
64-pin STQFP (PPG64)
20
25
35
55
Commercial Only
Industrial Only
Commercial Only
Commercial & Industrial
LA
SA
Low Power
Standard Power
71321
71421
16K (2K x 8-Bit) MASTER Dual-Port SRAM w/ Interrupt
16K (2K x 8-Bit) SLAVE Dual-Port SRAM w/ Interrupt
Speed in nanoseconds
2691 drw 18
NOTES:
1. Contact your sales office for industrial temperature range availability in other speeds, packages and powers.
LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02
Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience.
Orderable Part Information
Speed
(ns)
20
25
55
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
71321LA20JG
PLG52
PLCC
C
35
71321LA20JG8
PLG52
PLCC
C
71321LA20PFG
PNG64
TQFP
C
55
71321LA20PFG8
PNG64
TQFP
C
71321SA55JG8
71321LA20TFG
PPG64
TQFP
C
71321LA20TFG8
PPG64
TQFP
C
71321LA25JGI
PLG52
PLCC
I
71321LA25JGI8
PLG52
PLCC
I
Speed
(ns)
20
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
71321SA35TFG
PPG64
TQFP
C
71321SA35TFG8
PPG64
TQFP
C
71321SA55JG
PLG52
PLCC
C
PLG52
PLCC
C
Pkg.
Code
Pkg.
Type
Temp.
Grade
Orderable Part ID
Orderable Part ID
71321LA25PFGI
PNG64
TQFP
I
71421LA20JG
PLG52
PLCC
C
71321LA25PFGI8
PNG64
TQFP
I
71421LA20JG8
PLG52
PLCC
C
71321LA25TFGI
PPG64
TQFP
I
71421LA20PFG
PNG64
TQFP
C
71321LA25TFGI8
PPG64
TQFP
I
71421LA20PFG8
PNG64
TQFP
C
71321LA55PPGI
PPG52
TQFP
I
71421LA25PFGI
PNG64
TQFP
I
71321LA55PPGI8
PPG52
TQFP
I
71421LA25PFGI8
PNG64
TQFP
I
71321LA55TFG
PPG64
TQFP
C
71321LA55TFG8
PPG64
TQFP
C
25
17
6.42
71321SA/LA and 71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Datasheet Document History
03/24/99:
Pages 2 & 3
06/07/99:
11/10/99:
08/23/01:
Page 3
Page 4
Page 16
Page 4
01/17/06:
08/25/06:
10/29/08:
09/10/12:
06/10/16:
Page 7 & 9
Page 17
Page 1
Page 17
Page 1 & 17
Page 14
Page 17
Page 1 & 2
Page 3
Page 9
Page 17
Page 2
Page 3
Pages 2 & 17
02/20/18:
09/24/19:
Pages 1 & 17
Pages 2 & 3
Page 3
Page 5
Page 17
Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Added additional notes to pin configurations
Changed drawing format
Replaced IDT logo
Increased storage temperature parameters
Clarified TA parameter
DC Electrical parameters–changed wording from "open" to "disabled"
Fixed part numbers in "Width Expansion" paragraph
Changed ±500mV to 0mV in notes
Industrial temperature range offering added to DC Electrical Characteristics for 25ns and removed
for 35ns
Industrial temperature range added to AC Electrical Characteristics for 25ns
Industrial offering removed for 35ns ordering information
Added green availability to features
Added green indicator to ordering information
Replaced old IDTTM with new IDTTM logo
Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode
Removed "IDT" from orderable part number
52-pin STQFP added to the features and description
PP52-1 pin configuration added
Typo corrected
Added T&R indicator and PP52-1 package information to the ordering information
Changed diagram for the J52 pin configuration by rotating package pin labels and pin
numbers 90 degrees clockwise to reflect pin1 orientation and added pin 1 dot at pin 1
Removed J52 chamfers and aligned the top and bottom pin labels in the standard direction
Changed diagram for the PN64/PP64 pin configuration by rotating package pin labels and pin
numbers 90 degrees counter clockwise to reflect pin 1 orientation and added pin 1 dot at pin 1
PP52 pin configuration. Added the IDT logo, changed the text to be in alignment with new diagram
marking specs
Removed footnote 5 and its references
In pin configuration footnotes and in the Ordering Information: The package codes J52-1, PN64-1,
PP64-1 and PP52-1 changed to J52, PN64, PP64 & PP52 respectively to match standard package codes
Product Discontinuation Notice - PDN# SP-17-02
Last time buy expires June 15, 2018
Deleted obsolete Commercial 25ns speed grade
Updated package codes
Rotated PPG52 STQFP pin configuration to accurately reflect pin 1 orientation
Typo corrected in the Data Retention Characteristics table 06
Added Orderable Part Information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
18
6.42
for Tech Support:
408-284-2794
DualPortHelp@idt.com
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ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
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