7140LA35J

7130SA/LA 7140SA/LA HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM Features ◆ ◆ ◆ ◆ High-speed access – Commercial: 20/25/35/55/100ns (max.) – Industrial: 25/55ns (max.) – Military: 25/35/55/100ns (max.) Low-power operation – IDT7130/IDT7140SA — Active: 550mW (typ.) — Standby: 5mW (typ.) – IDT7130/IDT7140LA — Active: 550mW (typ.) — Standby: 1mW (typ.) MASTER IDT7130 easily expands data bus width to 16-ormore-bits using SLAVE IDT7140 ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ On-chip port arbitration logic (IDT7130 Only) BUSY output flag on IDT7130; BUSY input on IDT7140 INT flag for port-to-port communication Fully asynchronous operation from either port Battery backup operation–2V data retention (LA only) TTL-compatible, single 5V ±10% power supply Military product compliant to MIL-PRF-38535 QML Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin PLCC, and 64-pin STQFP and TQFP Green parts available, see ordering information Functional Block Diagram OEL OER CEL R/WL CER R/WR I/O0L- I/O7L I/O0R-I/O7R I/O Control BUSYL I/O Control (1,2) A9L (1,2) BUSYR Address Decoder A0L MEMORY ARRAY 10 CEL OEL R/WL INTL A9R A0R 10 ARBITRATION and INTERRUPT LOGIC CER OER R/WR (2) (2) INTR 2689 drw 01 NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor. IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor. 1 Jul.12.21 Address Decoder , 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Description of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 550mW of power. Low-power (LA) versions offer battery backup data retention capability, with each DualPort typically consuming 200µW from a 2V battery. The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP and STQFP. Military grade products are manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-ormore-bit memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R GND I/O7L I/O6L I/O5L I/O4L I/O3L GND I/O0R I/O1R I/O2R I/O3R I/O6R NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. LC48 package body is approximately .57 in x .57 in x .68 in. FP48 package body is approximately .75 in x .75 in x .11 in. 4. This package code is used to reference the package diagram. I/O4R I/O5R 2 Jul.12.21 18 17 16 15 14 13 12 11 10 9 8 7 6 19 20 5 4 21 22 3 7130/40 23 2 LC48(4) 1 24 48-Pin LCC 48 25 Top View 26 47 46 27 45 28 44 29 43 30 31 32 33 34 35 36 37 38 39 40 41 42 A3R A2R A1R A0R I/O3L I/O4L I/O5L I/O6L I/O7L A5L A4L A3L A2L A1L I/O2L I/O1L I/O0L A9L A8L A7L A6L 2689 drw 03F I/O7R A9R A8R A7R A6R A5R A4R INDEX 42 41 40 39 38 37 36 35 34 33 32 31 43 30 44 29 45 28 46 27 7130/40 26 47 FP48(4) 25 48 48-Pin Flatpack 24 1 Top View 23 2 22 3 4 21 20 5 19 6 7 8 9 10 11 12 13 14 15 16 17 18 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L OER INTR BUSYR R/WR CER VCC CEL R/WL BUSYL INTL OEL A0L A4R A5R A6R A7R A8R A9R I/O7R I/O6R A0R A1R A2R A3R Pin Configurations(1,2,3) A0L OEL INTL BUSYL R/WL CEL VCC CER R/WR BUSYR INTR OER 2689 drw 03L 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't.) CEL R/WL BUSYL INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND 1 2 3 7130 4 7140 5 6 7 PDG48(4) or 8 9 SB48(4) 10 11 48-Pin 12 DIP 13 Top 14 View(5) 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC CER R/WR BUSYR INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R 2689 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PDG48 package body is approximately .55 in x .61 in x .19 in. SB48 package body is approximately .62 in x 2.43 in x .15 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 3 Jul.12.21 , 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges I/O3L I/O2L I/O1L I/O0L A9L A8L A7L A6L A5L A4L A3L A2L A1L Pin Configurations(1,2,3) (con't.) I/O4L I/O5L I/O6L I/O7L N/C GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R 20 19 18 17 16 15 14 13 12 11 10 9 8 21 7 6 22 5 23 4 24 25 3 2 7130/40 PLG52(4) 26 27 52-Pin PLCC Top View 1 52 28 51 29 50 30 49 31 48 32 47 33 34 35 36 37 38 39 40 41 42 43 44 45 46 A0L OEL N/C INTL BUSYL R/WL CEL VCC CER R/WR BUSYR INTR N/C I/O7R N/C A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R OER 2689 drw 04 NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PLG52 package body is approximately .75 in x .75 in x .17 in. 4. This package code is used to reference the package diagram. 4 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges OER A0R A1R A2R A3R A4R A5R A6R N/C A7R A8R A9R N/C N/C I/O7R I/O6R Pin Configurations(1,2,3) (con't.) N/C N/C N/C INTR BUSYR R/WR CER VCC VCC CEL R/WL BUSYL INTL N/C N/C N/C 48 47 46 4544 43 42 4140 39 383736 35 34 33 49 32 50 31 51 30 52 29 28 53 7130/40 54 27 PPG64(4) (4) 55 26 PNG64 25 56 64-Pin STQFP 57 24 64-Pin TQFP 58 23 Top View 59 22 21 60 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 1213 14 1516 OEL A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L aa NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. PPG64 package body is approximately 10 mm x 10 mm x 1.4mm. PNG64 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram 5 Jul.12.21 I/O5R I/O4R N/C I/O3R I/O2R I/O1R I/O0R GND GND N/C I/O7L I/O6L I/O5L I/O4L N/C I/O3L 2689 drw 05 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Military Unit Symbol VTERM(2) Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V TBIAS Temperature Under Bias -55 to +125 -65 to +135 o Storage Temperature TSTG -65 to +150 DC Output Current IOUT Recommended DC Operating Conditions -65 to +150 50 o 50 C VCC Supply Voltage GND Ground VIH Input High Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ (1) Input Low Voltage VIL C Parameter -0.5 (2) 6.0 V 0.8 ____ V 2689 tbl 02 NOTES: 1. VIL (min.) > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. mA 2689 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended Operating Temperature and Supply Voltage(1) Grade Military Ambient Temperature GND Vcc -55OC to +125OC 0V 5.0V + 10% 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% Commercial Capacitance (TA = +25°C, f = 1.0MHz) Industrial STQFP and TQFP Packages Only Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions Max. Unit V IN = 3dV 9 pF VOUT = 3dV 10 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2689 tbl 03 pF 2689 tbl 05 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 7130SA 7140SA Symbol Parameter Test Conditions 7130LA 7140LA Min. Max. Min. Max. Unit |ILI| Input Leakage Current(1) VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA |ILO| Output Leakage Current(1) VCC - 5.5V, CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage (I/O0-I/O7) IOL = 4mA ___ 0.4 ___ 0.4 V VOL Open Drain Output Low Voltage (BUSY, INT) IOL = 16mA ___ 0.5 ___ 0.5 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V 2689 tbl 04 NOTE: 1. At Vcc < 2.0V leakages are undefined. 6 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,5) (VCC = 5.0V ± 10%) 7130X20(2) 7140X20(2) Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition Version 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military Typ. Max. Typ. Max. Typ. Max. Unit COM'L SA LA 110 110 250 200 110 110 220 170 110 110 165 120 mA MIL & IND SA LA ____ ____ ____ ____ 110 110 280 220 110 110 230 170 COM'L SA LA 30 30 65 45 30 30 65 45 25 25 65 45 MIL & IND SA LA ____ ____ ____ ____ 30 30 80 60 25 25 80 60 COM'L SA LA 65 65 165 125 65 65 150 115 50 50 125 90 MIL & IND SA LA ____ ____ ____ ____ 65 65 160 125 50 50 150 115 CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) COM'L SA LA 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 30 10 MIL & IND SA LA ____ ____ 30 10 ____ ____ 1.0 0.2 ____ ____ ____ ____ CE"A" < 0.2V and CE"B" > VCC - 0.2V(6) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(3) COM'L SA LA 60 60 155 115 60 60 145 105 45 45 110 85 MIL & IND SA LA ____ ____ ____ ____ 60 60 155 115 45 45 145 105 CEL and CER = VIL, Outputs Disabled f = fMAX(3) CEL and CER = VIH f = fMAX(3) CE"A" = VIL and CE"B" = VIH(6) Active Port OutputsDisabled, f=fMAX(3) mA mA mA mA 2689 tbl 06a 7130X55 7140X55 Com'l, Ind & Military Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Typ. Max. Typ. Max. Unit COM'L SA LA 110 110 155 110 110 110 155 110 mA MIL & IND SA LA 110 110 190 140 110 110 190 140 COM'L SA LA 20 20 65 35 20 20 55 35 MIL & IND SA LA 20 20 65 45 20 20 65 45 CE"A" = VIL and CE"B" = VIH(6) Active Port Outputs Disabled, f=fMAX(3) COM'L SA LA 40 40 110 75 40 40 110 75 MIL & IND SA LA 40 40 125 90 40 40 125 90 Full Standby Current (Both Ports CMOS Level Inputs) CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) COM'L SA LA 1.0 0.2 15 4 1.0 0.2 15 4 MIL & IND SA LA 1.0 0.2 30 10 1.0 0.2 30 10 Full Standby Current (One Port CMOS Level Inputs) CE"A" < 0.2V and CE"B" > VCC - 0.2V(6) VIN > VCC - 0.2V or V IN < 0.2V Active Port Outputs Disabled, f = fMAX(3) COM'L SA LA 40 40 100 70 40 40 95 70 MIL & IND SA LA 40 40 110 85 40 40 110 80 Dynamic Operating Current (Both Ports Active) CEL and CER = VIL, Outputs Disabled f = fMAX(3) Standby Current (Both Ports - TTL Level Inputs) CEL and CER = VIH f = fMAX(3) Standby Current (One Port - TTL Level Inputs) Version 7130X100 7140X100 Com'l, Ind & Military mA mA mA mA 2689 tbl 06b NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. PLCC , TQFP and STQFP packages only. 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tCYC, and using “AC TEST CONDITIONS” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ) 6. Port "A" may be either left or right port. Port "B" is opposite from port "A". 7 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Data Retention Characteristics (LA Version Only) 7130LA/7140LA Symbol Parameter VDR VCC for Data Retention ICCDR Data Retention Current VCC = 2.0V, CE > VCC -0.2V tCDR (3) tR(3) Min. Typ.(1) Max. Unit 2.0 ___ ___ V MIL. & IND. ___ 100 4000 µA COM'L. ___ 100 1500 0 ___ ___ ns tRC(2) ___ ___ ns Test Condition Chip Deselect to Data Retention Time VIN > VCC -0.2V or VIN < 0.2V Operation Recovery Time 2689 tbl 07 NOTES: 1. VCC = 2V, TA = +25°C, and is not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed but not production tested. Data Retention Waveform DATA RETENTION MODE VCC 4.5V VDR ≥ 2.0V tCDR 4.5V tR VDR CE VIH VIH 2692 drw 06 , 8 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1,2 and 3 2689 tbl 08 5V 5V 1250Ω 1250Ω DATAOUT DATAOUT 775Ω 30pF* 775Ω 5pF* *100pF for 55 and 100ns versions Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * including scope and jig Figure 1. Output Test Load 5V 270Ω BUSY or INT 30pF* *100pF for 55 and 100ns versions 2689 drw 07 Figure 3. BUSY and INT AC Output Test Load 9 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3) 7130X20(2) 7140X20(2) Com'l Only Symbol Parameter 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 11 ____ 12 ____ 20 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns 0 ____ 0 ____ 0 ____ ns ____ 10 ____ 10 ____ 15 ns 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 25 ____ 35 ns (1,4) tLZ Output Low-Z Time tHZ Output High-Z Time (1,4) tPU Chip Enable to Power Up Time (4) tPD (4) Chip Disable to Power Down Time 2689 tbl 09a 7130X55 7140X55 Com'l, Ind & Military Symbol Parameter 7130X100 7140X100 Com'l, Ind & Military Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 55 ____ 100 ____ ns tAA Address Access Time ____ 55 ____ 100 ns tACE Chip Enable Access Time ____ 55 ____ 100 ns tAOE Output Enable Access Time ____ 25 ____ 40 ns tOH Output Hold from Address Change 3 ____ 10 ____ ns tLZ Output Low-Z Time (1,4) 5 ____ 5 ____ ns tHZ (1,4) ____ 25 ____ 40 ns 0 ____ 0 ____ ns ____ 50 ____ 50 ns tPU tPD Output High-Z Time Chip Enable to Power Up Time (4) Chip Disable to Power Down Time (4) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2). 2. PLCC, TQFP and STQFP packages only. 3. 'X' in part numbers indicates power rating (SA or LA). 4. This parameter is guaranteed by device characterization, but is not production tested. . 10 Jul.12.21 2689 tbl 09b 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 1, Either Side(1) tRC ADDRESS tAA tOH tOH DATAOUT PREVIOUS DATA VALID DATA VALID BUSYOUT 2689 drw 08 tBDDH (2,3) NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations, BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. Timing Waveform of Read Cycle No. 2, Either Side(3) tACE CE tAOE (4) tHZ (2) OE tHZ (2) tLZ (1) DATAOUT VALID DATA tLZ ICC CURRENT ISS (1) tPD(4) tPU 50% 50% 2689 drw 09 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. 11 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(5) 7130X20(2) 7140X20(2) Com'l Only Symbol Parameter 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time (3) 20 ____ 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write 15 ____ 20 ____ 30 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width(4) 15 ____ 15 ____ 25 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 10 ____ 12 ____ 15 ____ ns ____ 10 ____ 10 ____ 15 ns 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time tDH Data Hold Time (1) (1) tWZ Write Enable to Output in High-Z ____ 10 ____ 10 ____ 15 ns tOW Output Active from End-of-Write (1) 0 ____ 0 ____ 0 ____ ns 2689 tbl 10a 7130X55 7140X55 Com'l, Ind & Military Symbol Parameter 7130X100 7140X100 Com'l, Ind & Military Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time (3) 55 ____ 100 ____ ns tEW Chip Enable to End-of-Write 40 ____ 90 ____ ns tAW Address Valid to End-of-Write 40 ____ 90 ____ ns tAS Address Set-up Time 0 ____ 0 ____ ns (4) tWP Write Pulse Width 30 ____ 55 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 20 ____ 40 ____ ns tHZ Output High-Z Time (1) ____ 25 ____ 40 ns tDH Data Hold Time 0 ____ 0 ____ ns ____ 25 ____ 40 ns 0 ____ 0 ____ ns tWZ tOW (1) Write Enable to Output in High-Z Output Active from End-of-Write (1) 2689 tbl 10b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization but is not production tested. 2. PLCC, TQFP and STQFP packages only. 3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA. 4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 5. 'X' in part numbers indicates power rating (SA or LA). 12 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8) tWC ADDRESS tHZ(7) OE tAW CE tWP(2) tAS(6) tWR(3) tHZ(7) R/W tWZ(7) tOW (4) DATA OUT (4) tDW tDH DATA IN 2689 drw 10 Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5) tWC ADDRESS tAW CE tAS(6) tEW(2) tWR(3) R/W tDW tDH DATA IN 2689 drw 11 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the HIGH impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 13 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(7) 7130X20(1) 7140X20(1) Com'l Only Symbol Parameter 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (For MASTER IDT 7130) tBAA BUSY Access Time from Address ____ 20 ____ 20 ____ 20 ns tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 20 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 20 ns tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 20 ____ 20 ns tWH Write Hold After BUSY(6) 12 ____ 15 ____ 20 ____ ns ____ 40 ____ 50 ____ 60 ns ____ 30 ____ 35 ____ 35 ns 5 ____ 5 ____ 5 ____ ns ____ 25 ____ 35 ____ 35 ns tWDD Write Pulse to Data Delay (2) tDDD Write Data Valid to Read Data Delay tAPS Arbitration Priority Set-up Time (3) tBDD (2) (4) BUSY Disable to Valid Data BUSY INPUT TIMING (For SLAVE IDT 7140) tWB Write to BUSY Input(5) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(6) 12 ____ 15 ____ 20 ____ ns ____ 40 ____ 50 ____ 60 ns ____ 30 ____ 35 ____ 35 ns (2) tWDD Write Pulse to Data Delay tDDD Write Data Valid to Read Data Delay (2) 2689 tbl 11a 7130X55 7140X55 Com'l, Ind & Military Symbol Parameter 7130X100 7140X100 Com'l, Ind & Military Min. Max. Min. Max. Unit BUSY TIMING (For MASTER IDT 7130) tBAA BUSY Access Time from Address] ____ 30 ____ 50 ns tBDA BUSY Disable Time from Address ____ 30 ____ 50 ns tBAC BUSY Access Time from Chip Enable ____ 30 ____ 50 ns tBDC BUSY Disable Time from Chip Enable ____ 30 ____ 50 ns tWH Write Hold After BUSY(6) 20 ____ 20 ____ ns ____ 80 ____ 120 ns ____ 55 ____ 100 ns 5 ____ 5 ____ ns ____ 55 ____ 65 ns tWDD Write Pulse to Data Delay (2) tDDD Write Data Valid to Read Data Delay tAPS Arbitration Priority Set-up Time (3) tBDD (2) (4) BUSY Disable to Valid Data BUSY INPUT TIMING (For SLAVE IDT 7140) tWB Write to BUSY Input(5) 0 ____ 0 ____ ns tWH Write Hold After BUSY(6) 20 ____ 20 ____ ns ____ 80 ____ 120 ns ____ 55 ____ 100 tWDD tDDD Write Pulse to Data Delay (2) Write Data Valid to Read Data Delay (2) NOTES: 1. PLCC, TQFP and STQFP packages only. 2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY." 3. To ensure that the earlier of the two ports wins. 4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'. 6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'. 7. 'X' in part numbers indicates power rating (S or L). 14 Jul.12.21 ns 2689 tbl 11b 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4) tWC ADDR"A" MATCH tWP R/W"A" tDH tDW DATAIN"A" VALID (1) tAPS ADDR"B" MATCH tBDD tBDA tBAA BUSY"B" tWDD DATAOUT"B" VALID tDDD 2689 drw 12 NOTES: 1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". Timing Waveform of Write with BUSY(3) tWP R/W"A" tWB BUSY"B" tWH(1) R/W"B" , (2) 2689 drw 13 NOTES: 1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A". 15 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) ADDR 'A' AND 'B' ADDRESSES MATCH CE'B' tAPS (2) CE'A' tBDC tBAC BUSY'A' 2689 drw 14 Timing Waveform by BUSY Arbitration Controlled by Address Match Timing(1) tRC OR tWC ADDR'A' ADDRESSES MATCH tAPS ADDRESSES DO NOT MATCH (2) ADDR'B' tBAA tBDA BUSY'B' 2689 drw 15 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only). AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(2) 7130X20(1) 7140X20(1) Com'l Only Symbol Parameter 7130X25 7140X25 Com'l, Ind & Military 7130X35 7140X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 20 ____ 25 ____ 25 ns tINR Interrupt Reset Time ____ 20 ____ 25 ____ 25 ns 2689 tbl 12a NOTES: 1. PLCC, TQFP and STQFP package only. 2. 'X' in part numbers indicates power rating (SA or LA). 16 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges AC Electrical characteristics Over the Operating Temperature and Supply Voltage Range(1) 7130X55 7140X55 Com'l, Ind & Military Symbol Parameter 7130X100 7140X100 Com'l, Ind & Military Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 45 ____ 60 ns tINR Interrupt Reset Time ____ 45 ____ 60 ns 2689 tbl 12b NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). Timing Waveform of Interrupt Mode(1) INT Set: tWC ADDR'A' (2) INTERRUPT ADDRESS tWR(4) tAS(3) R/W'A' tINS (3) INT'B' 2689 drw 16 INT Clear: tRC ADDR'B' INTERRUPT CLEAR ADDRESS tAS (3) OE'B' tINR (3) INT'A' 2689 drw 17 NOTES:. 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interrupt Truth Table II. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 17 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Truth Tables Truth Table I — Non-Contention Read/Write Control(4) Inputs(1) R/W CE OE D0-7 Function X H X Z Port Disabled and in Power-Down Mode, ISB2 or ISB4 X H X Z CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3 L L X DATAIN H L L DATAOUT H L H Z Data on Port Written into Memory (2) Data in Memory Output on Port(3) High Impedance Outputs 2689 tbl 13 NOTES: 1. A0L – A10L ≠ A0R – A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE Truth Table II — Interrupt Flag(1,4) Left Port Right Port R/WL CEL OEL A9L-A0L INTL R/WR CER OER A9R-A0R L L X 3FF X X X X X X X X X X L X X X X L(3) L X L L 3FE H X (2) Truth Table III — Address BUSY Arbitration Outputs CEL CER A0L-A9L A0R-A9R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 2689 tbl 15 NOTES: 1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are inputs for IDT7140 (slave). BUSYX outputs on the IDT7130 are open drain, not push-pull outputs. On slaves the BUSYX input internally inhibits writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 18 Jul.12.21 Function X L(2) Set Right INTR Flag L 3FF H(3) Reset Right INTR Flag L X 3FE X Set Left INTL Flag X X X X Reset Left INTL Flag 2689 tbl 14 NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE Inputs INTR 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Functional Description RAMs are being expanded in depth, then the BUSY indication for the resulting array does not require the use of an external AND gate. The IDT7130/IDT7140 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7130/IDT7140 has an automatic power down feature controlled by CE. The CE controls onchip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Width Expansion with Busy Logic Master/Slave Arrays Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FE (HEX), where a write is defined as the CER = R/WR = VIL per Truth Table II. The left port clears the interrupt by accessing address location 3FE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 3FF. The message (8 bits) at 3FE or 3FF is userdefined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 3FE and 3FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation. 5V 270Ω MASTER Dual Port RAM BUSYL Busy Logic BUSYL CE BUSYR CE BUSYR SLAVE Dual Port RAM BUSYL SLAVE Dual Port RAM BUSYL CE BUSYR 5V 270Ω CE BUSYR BUSYR 2689 drw 18 Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. In slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7130 RAM (Master) are open drain type outputs and require open drain resistors to operate. If these Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7130 (Master) and IDT7140 (Slave)RAMs. If two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a Master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with either the R/W signal or the byte enables. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. 19 Jul.12.21 MASTER Dual Port RAM BUSYL DECODER When expanding an RAM array in width while using busy logic, one master part is used to decide which side of the RAM array will receive a busy indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. Thus on the IDT7130/IDT7140 RAMs the BUSY pin is an output if the part is Master (IDT7130), and the BUSY pin is an input if the part is a Slave (IDT7140) as shown in Figure 3. 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Ordering Information XXXX A 999 Device Type Power Speed A Package A A A Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML G(2) Green P C J L F PF TF 48-pin 48-pin 52-pin 48-pin 48-pin 64-pin 64-pin 20 25 35 55 100 Commercial PLCC, TQFP and STQFP Only Commercial, Industrial & Military Commercial & Military Commercial, Industrial & Military Commercial & Military LA SA Low Power Standard Power 7130 7140 8K (1K x 8-Bit) MASTER Dual-Port RAM 8K (1K x 8-Bit) SLAVE Dual-Port RAM Plastic DIP (PDG48) Sidebraze DIP (SB48) PLCC (PLG52) LCC (LC48) Ceramic Flatpack (FP48) TQFP (PNG64) STQFP (PPG64) Speed in nanoseconds 2689 drw 19 NOTES: 1. Contact your local sales office for industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are Obsolete excluding FP48, LC48 & SB48. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. 20 Jul.12.21 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Orderable Part Information Speed (ns) 20 25 35 55 Pkg. Code Pkg. Type Temp. Grade Speed (ns) 7130LA20JG PLG52 PLCC C 20 7140LA20JG 7130LA20JG8 PLG52 PLCC C 7130LA20PFG PNG64 TQFP C 25 7130LA20PFG8 PNG64 TQFP C 7140LA25PFG8 7130LA20TFG PPG64 STQFP C 7140LA35CB 7130LA20TFG8 PPG64 STQFP C 7140LA35FB 7130LA25JGI PLG52 PLCC I 7130LA25JGI8 PLG52 PLCC I 7130LA25L48B LC48 LCC M 7130LA25PFGI PNG64 TQFP I 7130LA25PFGI8 PNG64 TQFP I 7130LA25TFGI PPG64 STQFP I 7130LA35C SB48 SB C 7130LA35CB SB48 SB M 7130LA35FB FP48 FPACK M Orderable Part ID 7130LA35L48B LC48 LCC M 7130LA35PDG PDG48 PDIP C SB48 SB C 7130LA55C 7130LA55CB SB48 SB M 7130LA55FB FP48 FPACK M 7130LA55L48B LC48 LCC M 7130LA55PDGI 100 PDG48 PDIP I 7130LA100C SB48 SB C 7130LA100CB SB48 SB M 7130LA100L48B LC48 LCC M 7130LA100PDG PDG48 PDIP C Pkg. Code Pkg. Type Temp. Grade Speed (ns) Orderable Part ID 25 7130SA25L48B LC48 LCC M 35 7130SA35C SB48 SB C 7130SA35CB SB48 SB M 7130SA35L48B LC48 LCC M 7130SA55C SB48 SB C 7130SA55CB SB48 SB M 7130SA55L48B LC48 LCC M 7130SA100C SB48 SB C 7130SA100CB SB48 SB M 7130SA100L48B LC48 LCC M 55 100 35 55 100 Speed (ns) 35 21 Jul.12.21 Pkg. Code Pkg. Type Temp. Grade PLG52 PLCC C 7140LA20JG8 PLG52 PLCC C 7140LA25PFG PNG64 TQFP C PNG64 TQFP C SB48 SB M FP48 FPACK M 7140LA35L48B LC48 LCC M 7140LA35PDG Orderable Part ID PDG48 PDIP C 7140LA55CB SB48 SB M 7140LA55L48B LC48 LCC M 7140LA100CB SB48 SB M 7140LA100L48B LC48 LCC M 7140LA100PDG PDG48 PDIP C Pkg. Code Pkg. Type Temp. Grade Orderable Part ID 7140SA35CB SB48 SB M 7140SA35L48B LC48 LCC M 55 7140SA55CB SB48 SB M 7140SA55L48B LC48 LCC M 100 7140SA100CB SB48 SB M 7130SA/LA and 7140SA/LA High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges Datasheet Document History 03/15/99: Pages 2 and 3 06/08/99: 08/02/99: 09/29/99: 11/10/99: 06/23/00: 01/08/02: 01/08/02: Page 2 Page 2 Page 1 & 18 Page 4 Page 5 Page 10 Page 1 Page 2 & 3 Page 4, 5, 8, 10, 12,14 & 15 Page 5, 8, 10, 12, & 14 Page 5, 8, 10, 12, & 14 Page 18 04/14/06: 10/21/08: 01/21/13: Page 1 & 19 Page 1 Page 18 Page 1 & 19 Page 18 Page 18 Page 2 05/20/16: Page 13, 18, 19 & 20 Page 20 Page 2 01/11/06: Page 3 Page 4 Page 5 Page 20 02/13/18: 07/12/21: Page 1 - 23 Page 1 & 21 Page 2, 3, 4 & 5 Page 21 Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Changed drawing format Corrected package number in note 3 Fixed pin 1 in DIP pin configuration Replaced IDT logo Increased storage temperature parameters Clarified TA parameter DC Electrical parameters–changed wording from "open" to "disabled" Changed ±500mV to 0mV in notes Added Ceramic Flatpack to 48-pin package offerings Added date revision to pin configurations Removed industrial temp option footnote from all tables Added industrial temp for 25ns to DC & AC Electrical Characteristics Removed industrial temp for 35ns to DC & AC Electrical Characteristics Added industrial temp for 25ns and removed industrial temp for 35ns in ordering information Updated industrial temp option footnote Replaced IDT TM logo with IDT ® logo Added green availability to features Added green indicator to ordering information Replaced old IDT TM with new IDT TM logo Added "PDG" footnote to the ordering information Removed "IDT" from orderable part number Added L48-1 package and F48-1 package pin configurations with corresponding foot notes Typo/corrections Added T & Reel indicator to ordering information Split the F48 and L48 pin configuration, creating two separate pin configurations: F48 pin ceramic flatpack rotated 90 degrees counterclockwise, removed footnote 5 reference and L48 LCC rotated 90 degrees clockwise to reflect pin 1 orientation and added dot at pin 1, removed footnote 5 reference P48 plastic DIP and C48 sidebrazed DIP, removed half moon and to reflect pin 1 orientation added dot at pin 1 J52 PLCC rotated 90 degrees clockwise to reflect pin 1 orientation added dot at pin 1, removed footnote 5 reference PN64 TQFP and PP64 STQFP, chamfer removed, rotated 90 degrees counterclockwise to reflect pin 1 orientation and added dot at pin 1, removed footnote 5 reference All incidences of -1 , -2 have been removed from the datasheet Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Rebranded as Renesas datasheet Deleted obsolete Industrial speed grade for 100ns Updated package codes Added Orderable Part Information tables 22 Jul.12.21 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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