7143LA35PF8

7133SA/LA 7143SA/LA HIGH SPEED 2K X 16 DUAL-PORT SRAM Features ◆ ◆ ◆ High-speed access – Commercial: 20/25/35/45/55/70/90ns (max.) – Industrial: 25ns (max.) – Military: 35/55/70/90ns (max.) Low-power operation – IDT7133/43SA Active: 1150mW (typ.) Standby: 5mW (typ.) – IDT7133/43LA Active: 1050mW (typ.) Standby: 1mW (typ.) Versatile control for write: separate write control for lower and upper byte of each port ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143 On-chip port arbitration logic (IDT7133 only) BUSY output flag on IDT7133; BUSY input on IDT7143 Fully asynchronous operation from either port Battery backup operation–2V data retention TTL-compatible; single 5V (±10%) power supply Available in 68-pin ceramic PGA, Flatpack, PLCC and 100pin TQFP Military product compliant to MIL-PRF-38535 QML Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram R/WRUB R/WLUB CER CE L R/W LLB R/WRLB OE R OE L I/O8L - I/O15L I/O CONTROL I/O0L - I/O7L I/O8R - I/O15R I/O CONTROL I/O0R - I/O7R (1) BUSY R BUSYL(1) A10L A0L MEMORY ARRAY ADDRESS DECODER 11 CE L ADDRESS DECODER A10R A0R 11 ARBITRATION LOGIC CE R (IDT7133 ONLY) 2746 drw 01 NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input. 1 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a “MASTER” Dual-Port RAM together with the IDT7143 “SLAVE” Dual-Port in 32-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R GND(2) VCC(1) I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L I/O9L Pin Configurations(1,2,3,4) address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology. Low-power (LA) versions offer battery backup data retention capability, with each port typically consuming 200µW for a 2V battery. The IDT7133/7143 devices have identical pinouts. Each is packed in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 27 9 28 8 29 7 30 6 31 5 32 33 34 35 36 4 3 7133/43 PLG68(4) 68-Pin PLCC Top View 2 1 68 37 67 38 66 39 65 40 64 41 63 42 62 43 61 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L I/O0L VCC(1) R/WLUB R/WLLB OEL A10L A9L A8L A7L 2746 drw 02 A6L A5L A4L A3L A2L A1L A0L BUSYL CEL CER BUSYR A0R A1R A2R A3R A4R A5R A5R A4R A3R A2R A1R A0R BUSYR CER CEL BUSYL A0L A1L A2L A3L A4L A5L A6L I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND(2) R/WRUB R/WRLB OER A10R A9R A8R A7R A6R NOTES: 1. Both VCC pins must be connected to the power supply to ensure reliable operation. 2. Both GND pins must be connected to the ground supply to ensure reliable operation. 3. PLG68 package body is approximately 0.95 in x 0.95 in x 0.17 in. FP68 package body is approximately 1.18 in x 1.18 in x 0.16 in. 4. This package code is used to reference the package diagram. A7L A8L A9L A10L OEL R/WLLB R/WLUB VCC(1) I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 62 42 63 41 64 40 65 39 66 67 68 1 2 38 7133/43 FP68(4) 68-Pin Flatpack Top View 37 36 35 34 3 33 4 32 5 31 6 30 7 29 8 28 27 9 A6R A7R A8R A9R A10R OER R/WRLB R/WRUB GND(2) I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O8R I/O9L I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L VCC(1) GND(2) I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 6.42 2 Jun.16.21 2746 drw 02c 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3,4) (con't.) 51 11 53 10 52 55 A10L 08 R/WLLB 57 59 41 CEL 38 A0R 39 BUSYR 36 A2R 37 A1R 28 I/O0L Pin 1 Designator A 26 62 24 64 22 I/O4L 20 I/O6L 1 5 I/O11L 4 7 I/O13L 6 9 I/O15L 8 11 GND(2) 10 13 I/O1R 12 15 I/O3R 14 18 I/O5R 16 I/O13R 21 I/O10R 3 I/O9L I/O15R 23 I/O12R 66 R/WRUB 25 I/O14R I/O2L OER 27 GND(2) 68-Pin PGA Top View(5) A9R 29 R/WRLB 60 A7R 31 A10R 7133/43 GU68(4) A6R 33 A8R 30 2 01 34 A5R 32 58 I/O8L A4R 35 A3R OEL I/O7L 68 02 43 A0L 40 CER 56 I/O5L 67 03 45 A2L 42 BUSYL A9L I/O3L 65 04 47 A4L 44 A1L 54 I/O1L 63 05 49 46 A3L VCC(1) R/WLUB 61 06 48 A5L A7L A8L 09 07 50 A6L I/O11R 19 I/O8R I/O9R , 17 I/O10L I/O12L I/O14L VCC(1) I/O0R I/O2R I/O4R I/O6R I/O7R B C D E F G H J K L 2746 drw 04 NOTES: 1. Both VCC pins must be connected to the power supply to ensure reliable operation. 2. Both GND pins must be connected to the ground supply to ensure reliable operation. 3. GU68 package body is approximately 1.18 in x 1.18 in x 0.16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 3 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L N/C BUSYL GND N/C BUSYR N/C A0R A1R A2R A3R A4R N/C N/C N/C N/C Pin Configurations(1,2,3,4) (con't.) A6L A7L A8L A9L A10L N/C N/C N/C R/WLUB CEL N/C R/WLLB VCC OEL I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O8L I/O9L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 80 46 81 82 45 44 43 83 42 84 7133/43 PNG100(4) 41 100-Pin TQFP Top View 38 85 86 87 88 89 40 39 37 36 35 34 33 32 31 30 29 28 27 26 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A5R A6R A7R A8R A9R A10R N/C N/C N/C R/WRUB CER N/C GND R/WRLB OER I/O15R GND I/O14R I/O13R I/O12R I/O11R I/O10R I/O9R I/O8R I/O7R N/C N/C N/C N/C I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C 2746 drw 03 NOTES: 1. Both VCC pins must be connected to the power supply to ensure reliable operation. 2. Both GND pins must be connected to the ground supply to ensure reliable operation. 3. PNG100 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. Pin Names Left Port Right Port Names CEL CER Chip Enable R/WLUB R/WRUB Upper Byte Read/Write Enable R/WLLB R/WRLB Lower Byte Read/Write Enable OEL OER Output Enable A0L - A10L A0R - A10R Address I/O0L - I/O15L I/O0R - I/O15R Data Input/Output BUSYL BUSYR Busy Flag VCC Power GND Ground 2746 tbl 01 6.42 4 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Maximum Operating Temperature and Supply Voltage(1,2) Absolute Maximum Ratings(1) Symbol Rating VTERM(2) Commercial & Industrial Military Unit -0.5 to +7.0 -0.5 to +7.0 V Terminal Voltage with Respect to GND Grade Military Temperature Under Bias -55 to +125 TSTG Storage Temperature -65 to +150 -65 to +150 PT Power Dissipation 2.0 2.0 W IOUT DC Output Current 50 50 mA TBIAS -65 to +135 o C -55OC to +125OC 0V 5.0V + 10% 0 C to +70 C 0V 5.0V + 10% -40 C to +85 C 0V 5.0V + 10% O Parameter(1) Conditions(2) Max. Unit VIN = 3dV 11 pF VOUT = 3dV 11 Input Capacitance Output Capacitance O O O NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Capacitance (TA = +25°C, f = 1.0mhz) COUT Vcc Industrial o 2746 tbl 04 Recommended DC Operating Conditions Symbol Parameter VCC Supply Voltage GND Ground VIH Input High Voltage VIL CIN GND Commercial C 2746 tbl 02 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Symbol Ambient Temperature Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ (1) Input Low Voltage -0.5 (2) 6.0 0.8 ____ V V 2746 tbl 05 NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. pF 2746 tbl 03 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (Either port, VCC = 5.0V ± 10%) 7133SA 7143SA Symbol Parameter Min. Max. Min. Max. Unit VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA VOL Output Low Voltage (I/O0-I/O15) IOL = 4mA ___ 0.4 ___ 0.4 V VOL Open Drain Output Low Voltage (BUSY) IOL = 16mA ___ 0.5 ___ 0.5 V VOH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ |ILI| (1) Input Leakage Current |ILO| Test Conditions 7133LA 7143LA NOTE: 1. At Vcc < 2.0V, input leakages are undefined. 6.42 5 Jun.16.21 V 2746 tbl 06 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Operating Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%) Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition Version CE = VIL, Outputs Disabled CEL and CER = VIH f = fMAX(3) CE"A" = VIL and CE"B" = VIH(4) f=fMAX(3) Active Port Outputs Disabled Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3) 7133X25 7143X25 Com'l & Ind Typ. (1) Max. Typ.(1) Max. Typ.(1) Max. Unit COM'L S L 250 230 310 280 250 230 300 270 240 210 295 250 mA MIL & IND S L ____ ____ ____ ____ 250 230 330 300 240 220 325 295 COM'L S L 25 25 80 70 25 25 80 70 25 25 70 60 MIL & IND S L ____ ____ ____ ____ 25 25 90 80 25 25 75 65 COM'L S L 140 120 200 180 140 100 200 170 120 100 180 160 MIL & IND S L ____ ____ ____ ____ 140 100 230 190 120 100 200 180 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 4 1.0 0.2 15 4 MIL & IND S L ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 COM'L S L 140 120 190 170 140 120 190 170 120 100 170 150 MIL & IND S L ____ ____ ____ ____ 140 120 220 200 120 100 190 170 (3) f = fMAX 7133X35 7143X35 Com'l & Military 7133X20 7143X20 Com'l Only mA mA mA mA 2746 tbl 07a 7133X45 7143X45 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Test Condition Version CE = VIL, Outputs Disabled f = fMAX(3) CEL and CER = VIH CE"A" = VIL and CE"B" = VIH(4) f=fMAX(3) Active Port Outputs Disabled Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3) 7133X70/90 7143X70/90 Com'l & Military Typ. (1) Max. Typ. (1) Max. Typ. (1) Max. Unit mA COM'L S L 230 210 290 250 230 210 285 250 230 210 280 250 MIL & IND S L ____ ____ ____ ____ 230 210 315 285 230 210 310 280 COM'L S L 25 25 75 65 25 25 70 60 25 25 70 60 MIL & IND S L ____ ____ ____ ____ 25 25 80 70 25 25 75 65 COM'L S L 120 100 190 170 120 100 180 160 120 100 180 160 MIL & IND S L ____ ____ ____ ____ 120 100 210 190 120 100 200 180 COM'L S L 1.0 0.2 15 4 1.0 0.2 15 4 1.0 0.2 15 4 MIL & IND S L ____ ____ ____ ____ 1.0 0.2 30 10 1.0 0.2 30 10 COM'L S L 120 100 180 160 120 100 170 150 120 100 170 150 MIL & IND S L ____ ____ ____ ____ 120 100 200 180 120 100 190 170 (3) f = fMAX 7133X55 7143X55 Com'l, Ind & Military mA mA mA mA 2746 tbl 07b NOTES: 1. VCC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (typ.) 2. 'X' in part number indicates power rating (SA or LA) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.42 6 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Data Retention Characteristics (LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V 7133LA/7143LA Symbol Parameter Test Condition Min. Typ. (1) Max. Unit 2.0 ___ ___ V VDR VCC for Data Retention VCC = 2V ICCDR Data Retention Current CE > VHC MIL. & IND. ___ 100 4000 VIN > VHC or < VLC COM'L. ___ 100 1500 0 ___ ___ tRC(2) ___ ___ tCDR (3) tR(3) Chip Deselect to Data Retention Time Operation Recovery Time µA V V 2746 tbl 08 NOTES: 1. Vcc = 2V, TA = +25°C, and are not production tested. 2. tRC = Read Cycle Time 3. This parameter is guaranteed by device characterization but is not production tested. Data Retention Waveform DATA RETENTION MODE VCC 4.5V VDR > 2V 4.5V tCDR tR VDR CE VIH VIH 2746 drw 05 AC Test Conditions 5V GND to 3.0V Input Pulse Levels 5ns Max. Input Rise/Fall Times Input Timing Reference Levels 1.5V Output Reference Levels 1.5V 1250Ω DATAOUT 775Ω 30pF Figures 1, 2 and 3 Output Load 2746 tbl 09 Figure 1. AC Output Test Load 5V 5V 270Ω 1250Ω BUSY DATAOUT 775Ω 5pF* 30pF 2746 drw 06 Figure 2. Output Load (for tLZ, tHZ, tWZ, tOW) *Including scope and jig 6.42 7 Jun.16.21 Figure 3. BUSY Output Load (IDT7133 only) 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(3) 7133X20 7143X20 Com'l Only Symbol Parameter 7133X25 7143X25 Com'l & Ind 7133X35 7143X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ns tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns tAOE Output Enable Access Time ____ 12 ____ 15 ____ 20 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0 ____ ns tLZ Output Low-Z Time (1,2) 0 ____ 0 ____ 0 ____ ns tHZ (1,2) ____ 12 ____ 15 ____ 20 ns 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 50 ____ 50 ns Output High-Z Time tPU Chip Enable to Power Up Time tPD (2) Chip Disable to Power Down Time (2) 2746 tbl 10a 7133X45 7143X45 Com'l Only Symbol Parameter 7133X55 7143X55 Com'l, Ind & Military 7133X70/90 7143X70/90 Com'l & Military Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 45 ____ 55 ____ 70/90 ____ ns tAA Address Access Time ____ 45 ____ 55 ____ 70/90 ns tACE Chip Enable Access Time ____ 45 ____ 55 ____ 70/90 ns tAOE Output Enable Access Time ____ 25 ____ 30 ____ 40/40 ns tOH Output Hold from Address Change 0 ____ 0 ____ 0/0 ____ ns 0 ____ 5 ____ 5/5 ____ ns ____ 20 ____ 20 ____ 25/25 ns 0 ____ 0 ____ 0/0 ____ ns ____ 50 ____ 50 ____ 50/50 ns tLZ tHZ tPU tPD Output Low-Z Time (1,2) Output High-Z Time (1,2) Chip Enable to Power Up Time (2) Chip Disable to Power Down Time (2) 2746 tbl 10b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part number indicates power rating (SA or LA). 6.42 8 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATA VALID DATA VALID BUSYOUT tBDD (3,4) 2746 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5) tACE (4) CE tAOE (4) tHZ (2) OE tLZ DATAOUT tLZ tPU CURRENT (1) (1) tHZ (2) VALID DATA tPD ICC 50% 50% ISB 2746 drw 08 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no relationship to valid output data. 4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD. 5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW. 6.42 9 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) 7133X20 7143X20 Com'l Only Symbol Parameter 7133X25 7143X25 Com'l & Ind 7133X35 7143X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time (3) 20 ____ 25 ____ 35 ____ ns tEW Chip Enable to End-of-Write 15 ____ 20 ____ 25 ____ ns tAW Address Valid to End-of-Write 15 ____ 20 ____ 25 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 15 ____ 20 ____ 25 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 15 ____ 15 ____ 20 ____ ns ____ 12 ____ 15 ____ 20 ns 0 ____ 0 ____ ns 15 ____ 20 ns ____ 0 ____ Output High-Z Time tHZ Data Hold Time tDH tWZ tOW (1,2) (4) 0 ____ (1,2) ____ 12 ____ (1,2,4) 0 ____ 0 Write Enable to Output in High-Z Output Active from End-of-Write ns 2746 tbl 11a 7133X45 7143X45 Com'l Only Symbol Parameter 7133X55 7143X55 Com'l, Ind & Military 7133X70/90 7143X70/90 Com'l & Military Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time (3) 45 ____ 55 ____ 70/90 ____ ns tEW Chip Enable to End-of-Write 30 ____ 40 ____ 50/50 ____ ns tAW Address Valid to End-of-Write 30 ____ 40 ____ 50/50 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0/0 ____ ns tWP Write Pulse Width 30 ____ 40 ____ 50/50 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0/0 ____ ns tDW Data Valid to End-of-Write 20 ____ 25 ____ 30/30 ____ ns ____ 20 ____ 20 ____ 25/25 ns 5 ____ 5 ____ 5/5 ____ ns ____ 20 ____ 20 ____ 25/25 ns 5 ____ 5 ____ 5/5 ____ ns tHZ tDH Output High-Z Time Data Hold Time (1,2) (4) (1,2) tWZ Write Enable to Output in High-Z tOW Output Active from End-of-Write (1,2,4) 2746 tbl 11b NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage from the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but not production tested. 3. For MASTER/SLAVE combination, tWC = tBAA + tWR + tWP, since R/W = VIL must occur after tBAA. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part number indicates power rating (SA or LA). 6.42 10 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(6) 7133X20 7143X20 Com'l Only Symbol Parameter 7133X25 7143X25 Com'l & Ind 7133X35 7143X35 Com'l & Military Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address ____ 20 ____ 20 ____ 30 ns BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 25 ns tBDC BUSY Disable Time from Chip Enable ____ 17 ____ 20 ____ 25 ns tWDD Write Pulse to Data Delay (1) ____ 40 ____ 50 ____ 60 ns ____ 30 ____ 35 ____ 45 ns ____ 25 ____ 30 ____ 35 ns 5 ____ 5 ____ 5 ____ ns 20 ____ 20 ____ 25 ____ ns BUSY TIMING (For MASTER 71V33) tBAA tBDA tBAC tDDD Write Data Valid to Read Data Delay tBDD BUSY Disable to Valid Data(2) tAPS Arbitration Priority Set-up Time tWH Write Hold After BUSY(5) (1) (3) BUSY INPUT TIMING (For SLAVE 71V43) tWB BUSY Input to Write (4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 20 ____ 20 ____ 25 ____ ns ____ 40 ____ 50 ____ 60 ns ____ 30 ____ 35 ____ 45 (1) tWDD Write Pulse to Data Delay tDDD Write Data Valid to Read Data Delay (1) ns 2746 tbl 12a 7133X45 7143X45 Com'l Only Symbol Parameter 7133X55 7143X55 Com'l, Ind & Military 7133X70/90 7143X70/90 Com'l & Military Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (For MASTER 71V33) tBAA BUSY Access Time from Address ____ 40 ____ 40 ____ 45/45 ns tBDA BUSY Disable Time from Address ____ 40 ____ 40 ____ 45/45 ns tBAC BUSY Access Time from Chip Enable ____ 30 ____ 35 ____ 35/35 ns tBDC BUSY Disable Time from Chip Enable ____ 25 ____ 30 ____ 30/30 ns ____ 80 ____ 80 ____ 90/90 ns ____ 55 ____ 55 ____ 70/70 ns ____ 40 ____ 40 ____ 40/40 ns 5 ____ 5 ____ 5/5 ____ ns 30 ____ 30 ____ 30/30 ____ ns 0 ____ 0 ____ 0/0 ____ ns 30 ____ 30 ____ 30/30 ____ ns ____ 80 ____ 80 ____ 90/90 ns ____ 55 ____ 55 ____ 70/70 (1) tWDD Write Pulse to Data Delay tDDD Write Data Valid to Read Data Delay (1) (2) tBDD BUSY Disable to Valid Data tAPS Arbitration Priority Set-up Time (3) tWH Write Hold After BUSY (5) BUSY INPUT TIMING (For SLAVE 71V43) tWB tWH BUSY Input to Write (4) Write Hold After BUSY (5) (1) tWDD Write Pulse to Data Delay tDDD Write Data Valid to Read Data Delay (1) ns 2746 tbl 12b NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy". 2. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). 3. To ensure that the earlier of the two ports wins. 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part number indicates power rating (SA or LA). 6.42 11 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)(1,5,8) tWC ADDRESS (6) tAS OE tWR(3) tAW CE tHZ tWP (2) R/W (7) (9) tWZ (7) tLZ DATAOUT tHZ (7) tOW (4) (4) tDH tDW DATAIN 2746 drw 09 Write Cycle No. 2 (CE Controlled Timing)(1,5) tWC ADDRESS tAW CE tAS(6) R/W tEW (2) tWR (9) tDW tDH DATAIN 2746 drw 10 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. Timing depends on which enable signal is de-asserted first, CE or OE. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. R/W for either upper or lower byte. 6.42 12 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3) tWC MATCH ADDR"A" tWP R/W"A" tDW tDH VALID DATAIN"A" (1) tAPS MATCH ADDR"B" tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID (4) tDDD NOTES: 1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2746 drw 11 Timing Waveform of Write with BUSY(3) tWP R/W"A" tWB BUSY"B" tWH R/W"B" (1) (2) , 2746 drw 12 NOTES: 1. tWH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6.42 13 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) ADDR"A" AND "B" ADDRESSES MATCH CE"A" tAPS(2) CE"B" tBAC tBDC BUSY"B" 2746 drw 13 Timing Waveform of BUSY Arbitration Controlled by Addresses(1) tRC OR ADDR "A" tWC ADDRESSES MATCH ADDRESSES DO NOT MATCH tAPS(2) ADDR "B" tBAA tBDA BUSY "B" 2746 drw 14 NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT7133 only). 6.42 14 Jun.16.21 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Functional Description The IDT7133/43 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7133/43 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Non-contention READ/WRITE conditions are illustrated in Truth Table 1. LEFT R/W Width Expansion with Busy Logic Master/Slave Arrays When expanding an IDT7133/43 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAM array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7133 RAM the BUSY pin is an output and on the IDT7143 RAM, the BUSY pin is an input (see Figure 3). BUSY VCC BUSY R/W R/W 270Ω R/W Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by using the IDT7143 (SLAVE). In the IDT7143, the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 7133 RAM are open drain and require pullup resistors. IDT7133 MASTER BUSY BUSY Busy Logic VCC IDT7143 SLAVE BUSY 270Ω R/W BUSY 2746 drw 15 Figure 4. Busy and chip enable routing for both width and depth expansion with the IDT7133 (MASTER) and the IDT7143 (SLAVE). Expanding the data bus width to 32 bits or more in a Dual-Port RAM system implies that several chips will be active at the same time. If each chip includes a hardware arbitrator, and the addresses for each chip arrive at the same time, it is possible that one will activate its BUSYL while another activates its BUSYR signal. Both sides are now BUSY and the CPUs will await indefinitely for their port to become free. To avoid the “Busy Lock-Out” problem, IDT has developed a MASTER/SLAVE approach where only one hardware arbitrator, in the MASTER, is used. The SLAVE has BUSY inputs which allow an interface to the MASTER with no external components and with a speed advantage over other systems. When expanding Dual-Port RAMs in width, the writing of the SLAVE RAMs must be delayed until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a write cycle during a contention situation. Conversely, the write pulse must extend a hold time past BUSY to ensure that a write cycle takes place after the contention is resolved. This timing is inherent in all Dual-Port memory systems where more than one chip is active at the same time. The write pulse to the SLAVE should be delayed by the maximum arbitration time of the MASTER. If, then, a contention occurs, the write to the SLAVE will be inhibited due to BUSY from the MASTER. 6.42 15 Jun.16.21 RIGHT R/W 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Truth Table I – Non-Contention Read/Write Control(4) LEFT OR RIGHT PORT(1) R/WLB R/WUB CE OE I/O0-7 I/O8-15 Function X X H X Z Z Port Disabled and in Power Down Mode, ISB2, ISB4 X X H X Z Z CER = CEL = VIH, Power Down Mode, ISB1 or ISB3 L L L X DATAIN DATAIN L H L L DATAIN DATAOUT H L L L DATAOUT DATAIN L H L H DATAIN Z Data on Lower Byte Written into Memory (2) H L L H Z DATAIN Data on Upper Byte Written into Memory (2) H H L L DATAOUT DATAOUT H H L H Z Z Data on Lower Byte and Upper Byte Written into Memory (2) Data on Lower Byte Written into Memory (2) , Data in Memory Output on Upper Byte (3) Data in Memory Output on Lower Byte (3), Data on Upper Byte Written into Memory (2) Data in Memory Output on Lower Byte and Upper Byte High Impedance Outputs NOTES: 1. A0L - A10L≠A0R - A10R 2. If BUSY = LOW, data is not written. 3. If BUSY = LOW, data may not be valid, see tWDD and tDDD timing. 4. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte Truth Table II — Address BUSY Arbitration Inputs Outputs CEL CER A0L-A10L A0R-A10R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 2746 tbl 14 NOTES: 1. Pins BUSYL and BUSYR are both outputs on the IDT7133 (MASTER). Both are inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. “H” if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = VIL will result BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 6.42 16 Jun.16.21 2746 tbl 13 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Ordering Information A XXXXX A 999 A Device Type Power Speed Package A A Process/ Temperature Range Blank Tube or Tray Tape and Reel 8 Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML G(2) Green J G F PF 68-pin PLCC (PLG68) 68-pin PGA (GU68) 68-pin Flatpack (FP68) 100-pin TQFP (PNG100) 20 25 35 45 55 70 90 Commercial Only Commercial & Industrial Commercial & Military Commercial Only Commercial & Military Commercial & Military Commercial & Military LA SA Low Power Standard Power 7133 7143 32K (2K x 16-Bit) MASTER Dual-Port RAM 32K (2K x 16-Bit) SLAVE Dual-Port RAM Speed in nanoseconds 2746 drw 16 NOTES: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are Obsolete excluding PGA and Flatpack. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 20 Orderable Part ID 7133LA20G 7133LA20JG 7133LA20JG8 7133LA20PFG 7133LA20PFG8 25 35 7133LA25G Pkg. Code Pkg. Type Temp. Grade Speed (ns) GU68 PGA C 20 C 25 C 35 PLG68 PLG68 PNG100 PNG100 GU68 PLCC PLCC TQFP TQFP PGA Pkg. Code Pkg. Type Temp. Grade 7133SA20G GU68 PGA C 7133SA25G GU68 PGA C 7133SA35FB FP68 FPACK M C 7133SA35G GU68 PGA C C 7133SA35GB GU68 PGA M C 7133SA35PFG PNG100 TQFP C 7133SA35PFG8 PNG100 TQFP C 7133LA25JGI PLG68 PLCC I 7133LA25JGI8 PLG68 PLCC I 7133LA25PFGI PNG100 TQFP I 7133LA25PFGI8 PNG100 TQFP I 7133LA35FB FP68 FPACK GU68 PGA C 7133LA35GB GU68 PGA M 45 7133LA45G GU68 PGA C 55 7133LA55FB FP68 FPACK M 7133LA55G GU68 PGA C 7133LA55GB GU68 PGA M 70 7133LA70G GU68 PGA C 7133LA70GB GU68 PGA M 90 7133LA90G GU68 PGA C 7133LA90GB GU68 PGA M 6.42 17 Jun.16.21 45 7133SA45G GU68 PGA C 55 7133SA55FB FP68 FPACK M 7133SA55G GU68 PGA C 7133SA55GB GU68 PGA M 70 7133SA70G GU68 PGA C 7133SA70GB GU68 PGA M 90 7133SA90G GU68 PGA C 7133SA90GB GU68 PGA M M 7133LA35G Orderable Part ID 7133SA/LA, 7143SA/LA High-Speed 2K x 16 Dual-Port RAM Military, Industrial and Commercial Temperature Ranges Orderable Part Information (con't) Speed (ns) 20 Orderable Part ID Pkg. Code Pkg. Type Temp. Grade Speed (ns) Pkg. Code Pkg. Type Temp. Grade C 7143LA20G GU68 PGA C 20 7143SA20G GU68 PGA 7143LA20JG PLG68 PLCC C 25 7143SA25G GU68 PGA C 7143LA20JG8 PLG68 PLCC C 35 7143SA35FB FP68 FPACK M 7143SA35G GU68 PGA C M 25 7143LA25G GU68 PGA C 35 7143LA35FB FP68 FPACK M 7143LA35G GU68 PGA C 7143LA35GB GU68 PGA M 7143LA55G GU68 PGA C 7143LA55GB GU68 PGA M 70 7143LA70GB GU68 PGA M 90 7143LA90GB GU68 PGA M 55 Orderable Part ID Datasheet Document History 12/18/98: 02/17/99: 030/9/99: 06/09/99: 10/01/99: 11/10/99: 04/01/00: 06/26/00: 01/31/06: 10/21/08: 01/16/13: 08/13/19: 06/16/21: GU68 PGA GU68 PGA C 7143SA55GB GU68 PGA M 70 7143SA70GB GU68 PGA M 90 7143SA90GB GU68 PGA M Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Page 2 Corrected PN100 pinout Corrected PF ordering code Cosmetic and typographical corrections Changed drawing format Added Industrial Temperature Ranges and removed corresponding notes Replaced IDT logo Changed ±500mV to 0mV in notes Page 2 Fixed overbar in pinout Page 4 Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Page 1 Added green availability to features Page 16 Added green indicator for ordering information Page 16 Removed "IDT" from orderable part number Page 1, 5, 7, 9 &10 Removed Military 25ns & 45ns & Industrial 35ns speed grades from Features and from the headers of the MIL & IND of the DC Chars and AC Chars tables to indicate this change Page 5 Removed the Typ & Max values for the MIL & IND temp range from the 7133x45 and 7143x45 speed grade offering from the DC Chars tables to indicate this change, see table 07b Page 4 Removed annotation for footnote 3 in the Absolute Maximum Ratings table Page 8 & 9 Typo/correction Page 16 Added T& R indicator to and removed Military 25ns & 45ns & Industrial 35ns speed grades from the ordering information Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 1 & 16 Deleted obsolete Industrial speed 55ns Page 2 Rotated PLG68 PLCC and PNG100 TQFP pin configurations to accurately reflect pin 1 orientation Page 16 Added Orderable Part Information Pages 1-19 Rebranded as Renesas datasheet Page 2 Rotated FP68 Flatpack pin configuration to accurately reflect pin 1 orientation 6.42 18 Jun.16.21 7143SA35GB 7143SA55G 55 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.