71T75802S133BGGI8

512K x 36, 1M x 18 2.5V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 512K x 36, 1M x 18 memory configurations Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 71T75602 71T75802 Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion 2.5V power supply (±5%) 2.5V I/O Supply (VDDQ) Power down controlled by ZZ input Boundary Scan JTAG Interface (IEEE 1149.1 Compliant) Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram - 512K x 36 LBO Address A [0:18] D Q 512Kx36 BIT MEMORY ARRAY Address D Q Control CE1, CE2, CE2 R/W Input Register CEN ADV/LD BWx D DI Q DO Control Logic Clk Mux Gate OE TMS TDI TCK D Output Register Q Clk Clock Sel JTAG Data I/O [0:31], I/O P[1:4] TDO TRST 5313 drw 01 (optional) ® ZBT and Zero Bus Turnaround are trademarks of Renesas Electronics Corporation and the architecture is supported by Micron Technology and Motorola Inc. 1 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Description There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Megaasserted when ADV/LD is low, no new memory operation can be initiated. bit) synchronous SRAMs. They are designed to eliminate dead bus However, any pending data transfers (reads or writes) will be cycles when turning the bus around between reads and writes, or writes completed. The data bus will tri-state two cycles after the chip is deselected and reads. Thus, they have been given the name ZBTTM, or Zero Bus or a write is initiated. Turnaround. The IDT71T75602/802 have an on-chip burst counter. In the burst Address and control signals are applied to the SRAM during one clock mode, the IDT71T75602/802 can provide four cycles of data for a single cycle, and two cycles later the associated data cycle occurs, be it read or address presented to the SRAM. The order of the burst sequence is write. defined by the LBO input pin. The LBO pin selects between linear and The IDT71T75602/802 contain data I/O, address and control signal interleaved burst sequence. The ADV/LD signal is used to load a new registers. Output enable is the only asynchronous signal and can be used external address (ADV/LD = LOW) or increment the internal burst to disable the outputs at any given time. counter (ADV/LD = HIGH). A Clock Enable CEN pin allows operation of the IDT71T75602/802 The IDT71T75602/802 SRAMs utilize a high-performance 2.5V to be suspended as long as necessary. All synchronous inputs are CMOS process, and are packaged in a JEDEC Standard 14mm x ignored when (CEN) is high and the internal device registers will hold their 20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid previous values. array (BGA). Functional Block Diagram - 1M x 18 LBO Address A [0:19] D Q 1Mx18 BIT MEMORY ARRAY Address D Q Control CE1, CE2, CE2 R/W Input Register CEN ADV/LD BWx D DI Q DO Control Logic Clk Mux Gate OE TMS TDI TCK JTAG Data I/O [0:15], I/O P[1:2] TDO TRST 5313 drw 01b (optional) 6.42 2 Sep.27.21 D Output Register Q Clk Clock Sel 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Description Summary A0-A19 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static TMS Test Mode Select Input N/A TDI Test Data Input Input N/A TCK Test Clock Input N/A TDO Test Data Input Output N/A TRST JTAG Reset (Optional) Input Asynchronous ZZ Sleep Mode Input Synchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5313 tbl 01 6.42 3 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Definitions Commercial and Industrial Temperature Ranges (1) Symbol Pin Function I/O Active Description A0-A19 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high. R/W Read / Write I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The data bus activity for the current cycle takes place two clock cycles later. CEN Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock. BW1-BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles (when R/W and ADV/LD are sample d low) the appropriate byte write signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word. CE1, CE2 Chip Enables I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71T75602/802 (CE1 or CE2 sampled high or CE 2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle de select, i.e., the data bus will tri-state two clock cycles after deselect is initiated. CE 2 Chip Enable I HIGH Synchronous active high chip enable. CE 2 is used with CE1 and CE2 to enable the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2. CLK Clock I N/A This is the clock input to the IDT71T75602/802. Except for OE, all timing references for the device are made with respect to the rising edge of CLK. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are reg istered and triggered by the rising edge of CLK. LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is sele cted. When LBO is low the Linear burst sequence is selected. LBO is a static input and it must not change during device operation. OE Output Enable I LOW Asynchronous output enable . OE must be low to read data from the 71T75602/802. Whe n OE is high the I/O pins are in a high-impedance state.OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied low. TMS Test Mode Select I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup. TDI Test Data Input I N/A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal pullup. TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while test outputs are d riven from the falling edge of TCK. This pin has an internal pullup. TDO Test Data Output O N/A Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP controller. TRST JTAG Reset (Optional) I LOW Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can be left floating. This pin has an internal pullup. Only available in BGA package. ZZ Sleep Mode I HIGH Synchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown. VDD Power Supply N/A N/A 2.5V core power supply. VDDQ Power Supply N/A N/A 2.5V I/O Supply. VSS Ground N/A N/A Ground. 5313 tbl 02 NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 4 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS VDD(1) VDD ZZ I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 Pin Configuration — 512K x 36, PKG100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A9 A8 A17 A18 ADV/LD OE CEN R/W CLK VSS VDD CE2 BW1 BW2 BW3 BW4 CE2 CE1 A7 A6 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 71T75602 PKG100 90 91 42 41 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 A16 A15 A14 A13 A12 A11 A10 NC/TCK(2) NC/TDO(2) VDD VSS NC/TDI(2) NC/TMS(2) A0 A1 A2 A3 A4 A5 LBO 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VDD(1) VDD VDD(1) VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 5313 drw 02r Top View 100 TQFP NOTES: 1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH. 2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up. 6.42 5 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS VDD(1) VDD ZZ I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC Pin Configuration — 1M x 18, PKG100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A9 A8 A18 A19 ADV/LD OE CEN R/W CLK VSS VDD CE2 BW1 BW2 NC NC CE2 CE1 A7 A6 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 71T75802 PKG100 90 91 41 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 A17 A16 A15 A14 A13 A12 A11 NC/TCK(2) NC/TDO(2) VDD VSS NC/TDI(2) NC/TMS(2) A0 A1 A2 A3 A4 A5 LBO 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VDD(1) VDD VDD(1) VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC NC NC NC 5313 drw 02ra Top View 100 TQFP NOTES: 1. Pins 14, 16, and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH. 2. Pins 38, 39 and 43 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39 and 43 could be tied to VDD or VSS and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up. 6.42 6 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Pin Configuration — 512K X 36, BG119, BGG119(1,2,4) 1 2 3 4 5 6 7 A V DDQ A6 A4 A18 A8 A16 V DDQ B NC CE2 A3 ADV/LD A9 CE2 NC C NC A7 A2 V DD A12 A15 NC D I/O16 I/OP3 V SS NC V SS I/OP2 I/O15 E I/O17 I/O18 V SS CE1 V SS I/O13 I/O14 F V DDQ I/O19 V SS OE V SS I/O12 V DDQ G I/O20 I/O21 BW3 A17 BW2 I/O11 I/O10 H I/O22 I/O23 V SS R/W V SS I/O9 I/O8 J V DDQ V DD V DD(1) V DD V DD(1) V DD V DDQ K I/O24 I/O26 V SS CLK V SS I/O6 I/O7 L I/O25 I/O27 BW4 NC BW1 I/O4 I/O5 M V DDQ I/O28 V SS CEN V SS I/O3 V DDQ N I/O29 I/O30 V SS A1 V SS I/O2 I/O1 P I/O31 I/OP4 V SS A0 V SS I/OP1 I/O0 R NC A5 LBO V DD V DD(1) A13 NC T NC NC A10 A11 A14 NC U V DDQ NC/TMS (2) NC/TDI (2) NC/TCK (2) NC/TDO (2) ZZ NC/TRST (2,3) Top View V DDQ 5313 tbl 25b Pin Configuration — 1M X 18, BG119, BGG119(1,2,4) 1 2 3 4 5 6 7 A V DDQ A6 A4 A19 A8 A16 V DDQ B NC CE2 A3 ADV/LD A9 CE2 NC C NC A7 A2 V DD A13 A17 NC D I/O8 NC V SS NC V SS I/OP1 NC E NC I/O9 V SS CE1 V SS NC I/O7 F V DDQ NC V SS OE V SS I/O6 V DDQ G NC I/O10 BW2 A18 V SS NC I/O5 H I/O11 NC V SS R/W V SS I/O4 NC J V DDQ V DD V DD V DD V DD V DD V DDQ K NC I/O12 V SS CLK V SS NC I/O3 (1) (1) L I/O13 NC V SS NC BW1 I/O2 NC M V DDQ I/O14 V SS CEN V SS NC V DDQ N I/O15 NC V SS A1 V SS I/O1 NC P NC I/OP2 V SS A0 V SS NC I/O0 R NC A5 LBO V DD V DD(1) A12 NC T NC A10 A15 NC A14 A11 ZZ U V DDQ NC/TMS(2) NC/TDI(2) NC/TCK(2) NC/TDO(2) NC/TRST(2,3) V DDQ Top View 5313 tbl 25c NOTES: 1. J3, R5, and J5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH. 2. U2, U3, U4 and U6 will be pulled internally to VDD if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. U2, U3, U4 and U6 could be tied to VDD or VSS and U5 should be left unconnected. Or all JTAG inputs(TMS, TDI, and TCK and TRST) U2, U3, U4 and U6 could be left unconnected “NC” and the JTAG circuit will remain disabled from power up. 3. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD. 4. This text does not indicate orientation of actual part-marking. 6.42 7 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Absolute Maximum Ratings Symbol Rating Commercial (1) Commercial and Industrial Temperature Ranges 100 Pin TQFP Capacitance Industrial (TA = +25°C, f = 1.0MHz) Unit VTERM(2) Terminal Voltage with Respect to GND -0.5 to +3.6 -0.5 to +3.6 VTERM(3,6) Terminal Voltage with Respect to GND -0.5 to VDD -0.5 to VDD VTERM(4,6) Terminal Voltage with Respect to GND -0.5 to VDD +0.5 -0.5 to VDD +0.5 (5,6) Terminal Voltage with Respect to GND -0.5 to VDDQ +0.5 -0.5 to VDDQ +0.5 0 to +70 -40 to +85 o C C Symbol C CIN Input Capacitance CI/O I/O Capacitance VTERM V Symbol V CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 3dV 5 pF VOUT = 3dV 7 pF V 5313 tbl 07 V 119 Pin BGA Capacitance TA(7) Operating Ambient Temperature TBIAS Temperature Under Bias -55 to +125 -55 to +125 o TSTG Storage Temperature -55 to +125 -55 to +125 o PT Power Dissipation 2.0 2.0 W IOUT DC Output Current 50 50 mA (TA = +25°C, f = 1.0MHz) 5313 tbl 06 Recommended Operating Temperature and Supply Voltage Ambient Temperature(1) VSS VDD VDDQ Commercial 0° C to +70° C OV 2.5V ± 5% 2.5V ± 5% Industrial -40° C to +85° C OV 2.5V ± 5% 2.5V ± 5% Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 7 pF NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit VDD Core Supply Voltage 2.375 2.5 2.625 V VDDQ I/O Supply Voltage 2.375 2.5 2.625 V VSS Ground 0 0 0 V VIH Input High Voltage - Inputs 1.7 ____ VDD +0.3 V VIH Input High Voltage - I/O 1.7 ____ VDDQ +0.3 V ____ 0.7 V VIL Grade Parameter(1) 5313 tbl 07a NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp up. 7. During production testing, the case temperature equals TA. Input Low Voltage (1) -0.3 NOTE: 1. VIL (min.) = –0.8V for pulse width less than tCYC/2, once per cycle. 5313 tbl 05 NOTE: 1. During production testing, the case temperature equals the ambient temperature. 6.42 8 Sep.27.21 Parameter(1) 5313 tbl 03 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Synchronous Truth Table(1) CEN R/W Chip(5) Enable ADV/LD BWx ADDRESS USED PREVIOUS CYCLE CURRENT CYCLE I/O (2 cycles later) L L Select L Valid External X LOAD WRITE D(7) L H Select L X External X LOAD READ Q(7) L X X H Valid Internal LOAD WRITE / BURST WRITE BURST WRITE (Advance burst counter)(2) D(7) L X X H X Internal LOAD READ / BURST READ BURST READ (Advance burst counter)(2) Q(7) L X Deselect L X X X DESELECT or STOP (3) HiZ L X X H X X DESELECT / NOOP NOOP HiZ H X X X X X (4) X SUSPEND Previous Value 5313 tbl 08 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle. 3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state two cycles after deselect is initiated. 4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propagating through the part. The state of all the internal registers and the I/Os remains unchanged. 5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false. 6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. 7. Q - Data read from the device, D - data written to the device. Partial Truth Table for Writes(1) OPERATION READ WRITE ALL BYTES (2) WRITE BYTE 1 (I/O[0:7], I/OP1) (2) WRITE BYTE 2 (I/O[8:15], I/OP2) R/W BW1 BW2 BW3(3) BW4(3) H X X X X L L L L L L L H H H L H L H H (2,3) WRITE BYTE 3 (I/O[16:23], I/OP3) L H H L H WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3) L H H H L NO WRITE L H H H H 5313 tbl 09 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. Multiple bytes may be selected during the same cycle. 3. N/A for X18 configuration. 6.42 9 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Interleaved Burst Sequence Table (LBO=VDD) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 Fourth Address (1) 5313 tbl 10 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 Fourth Address (1) 5313 tbl 11 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Functional Timing Diagram(1) CYCLE n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 A29 A30 A31 A32 A33 A34 A35 A36 A37 C29 C30 C31 C32 C33 C34 C35 C36 C37 D/Q27 D/Q28 D/Q29 D/Q30 D/Q31 D/Q32 D/Q33 D/Q34 D/Q35 CLOCK (2) ADDRESS (A0 - A18) (2) CONTROL (R/W, ADV/LD, BWx) (2) DATA I/O[0:31], I/O P[1:4] , 5313drw 03 NOTES: 1. This assumes CEN, CE1, CE2, CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock. 6.42 10 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2) Cycle Address R/W ADV/LD CE(1) CEN BWx OE I/O Comments n A0 H L L L X X X Load read n+1 X X H X L X X X Burst read n+2 A1 H L L L X L Q0 Load read n+3 X X L H L X L Q0+1 Deselect or STOP n+4 X X H X L X L Q1 NOOP n+5 A2 H L L L X X Z Load read n+6 X X H X L X X Z Burst read n+7 X X L H L X L Q2 Deselect or STOP n+8 A3 L L L L L L Q2+1 Load write n+9 X X H X L L X Z Burst write n+10 A4 L L L L L X D3 Load write n+11 X X L H L X X D3+1 n+12 X X H X L X X D4 NOOP n+13 A5 L L L L L X Z Load write n+14 A6 H L L L X X Z Load read n+15 A7 L L L L L X D5 Load write n+16 X X H X L L L Q6 Burst write n+17 A8 H L L L X X D7 Load read n+18 X X H X L X X D7+1 Burst read n+19 A9 L L L L L L Q8 Load write Deselect or STOP 5313 tbl 12 NOTES: 1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 2. H = High; L = Low; X = Don’t Care; Z = High Impedance. Read Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X L X X X Clock Setup Valid n+2 X X X X X X L Q0 Contents of Address A0 Read Out NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 11 Sep.27.21 5313 tbl 13 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Burst Read Operation Commercial and Industrial Temperature Ranges (1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X H X L X X X Clock Setup Valid, Advance Counter n+2 X X H X L X L Q0 Address A0 Read Out, Inc. Count n+3 X X H X L X L Q0+1 Address A0+1 Read Out, Inc. Count n+4 X X H X L X L Q0+2 Address A0+2 Read Out, Inc. Count n+5 A1 H L L L X L Q0+3 Address A0+3 Read Out, Load A1 n+6 X X H X L X L Q0 Address A0 Read Out, Inc. Count n+7 X X H X L X L Q1 Address A1 Read Out, Inc. Count n+8 A2 H L L L X L Q1+1 Address A1+1 Read Out, Load A2 5313 tbl 14 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup n+1 X X X X L X X X Clock Setup Valid n+2 X X X X L X X D0 Write to Address A0 5313 tbl 15 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Burst Write Operation(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup n+1 X X H X L L X X Clock Setup Valid, Inc. Count n+2 X X H X L L X D0 Address A0 Write, Inc. Count n+3 X X H X L L X D0+1 Address A0+1 Write, Inc. Count n+4 X X H X L L X D0+2 Address A0+2 Write, Inc. Count n+5 A1 L L L L L X D0+3 Address A0+3 Write, Load A1 n+6 X X H X L L X D0 Address A0 Write, Inc. Count n+7 X X H X L L X D1 Address A1 Write, Inc. Count n+8 A2 L L L L L X D1+1 Address A1+1 Write, Load A2 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 12 Sep.27.21 5313 tbl 16 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Read Operation with Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 H L L L X X X Address and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 H L L L X X X Clock Valid n+3 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+4 X X X X H X L Q0 Clock Ignored. Data Q0 is on the bus. n+5 A2 H L L L X L Q0 Address A0 Read out (bus trans.) n+6 A3 H L L L X L Q1 Address A1 Read out (bus trans.) n+7 A4 H L L L X L Q2 Address A2 Read out (bus trans.) 5313 tbl 17 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Write Operation with Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n A0 L L L L L X X Address and Control meet setup. n+1 X X X X H X X X Clock n+1 Ignored. n+2 A1 L L L L L X X Clock Valid. n+3 X X X X H X X X Clock Ignored. n+4 X X X X H X X X Clock Ignored. n+5 A2 L L L L L X D0 Write Data D0 n+6 A3 L L L L L X D1 Write Data D1 n+7 A4 L L L L L X D2 Write Data D2 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 13 Sep.27.21 5313 tbl 18 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Read Operation with Chip Enable Used Commercial and Industrial Temperature Ranges (1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O(3) Comments n X X L H L X X ? Deselected. n+1 X X L H L X X ? Deselected. n+2 A0 H L L L X X Z Address and Control meet setup. n+3 X X L H L X X Z Deselected or STOP. n+4 A1 H L L L X L Q0 Address A0 Read out. Load A 1. n+5 X X L H L X X Z Deselected or STOP. n+6 X X L H L X L Q1 Address A1 Read out. Deselected. n+7 A2 H L L L X X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STOP. n+9 X X L H L X L Q2 Address A2 Read out. Deselected. 5313 tbl 19 NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up. Write Operation with Chip Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O Comments n X X L H L X X ? Deselected. n+1 X X L H L X X ? Deselected. n+2 A0 L L L L L X Z Address and Control meet setup. n+3 X X L H L X X Z Deselected or STOP. n+4 A1 L L L L L X D0 Address D0 Write in. Load A 1. n+5 X X L H L X X Z Deselected or STOP. n+6 X X L H L X X D1 Address D1 Write in. Deselected. n+7 A2 L L L L L X Z Address and control meet setup. n+8 X X L H L X X Z Deselected or STOP. n+9 X X L H L X X D2 Address D2 Write in. Deselected. NOTES: 1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 6.42 14 Sep.27.21 5313 tbl 20 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 2.5V±5%) Symbol Parameter |ILI| Test Conditions Input Leakage Current |ILI| LBO, JTAG and ZZ Input Leakage Current (1) Min. Max. Unit VDD = Max., VIN = 0V to VDD ___ 5 µA VDD = Max., VIN = 0V to VDD ___ 30 µA |ILO| Output Leakage Current VOUT = 0V to VDDQ , Device Deselected ___ 5 µA VOL Output Low Voltage IOL = +6mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = -6mA, VDD = Min. 2.0 ___ V 5313 tbl 21 NOTE: 1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD, and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) (VDD = 2.5V±5%) Symbol Parameter 200MHz(4) Test Conditions 166MHz 150MHz 133MHz 100MHz Com'l Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind Unit IDD Operating Power Supply Current Device Selected, Outputs Open, ADV/LD = X, V DD = Max., V IN > V IH or < V IL, f = fMAX(2) 275 295 245 265 215 235 195 215 175 195 mA ISB1 CMOS Standby Power Supply Current Device Deselected, Outputs Open, V DD = Max., V IN > V HD or < V LD, f = 0(2,3) 40 60 40 60 40 60 40 60 40 60 mA ISB2 Clock Running Power Supply Current Device Deselected, Outputs Open, V DD = Max., V IN > V HD or < V LD, f = fMAX(2.3) 80 100 70 90 60 80 50 70 45 65 mA ISB3 Idle Power Supply Current Device Selected, Outputs Open, CEN > V IH, V DD = Max., V IN > V HD or < V LD, f = fMAX(2,3) 60 80 60 80 60 80 60 80 60 80 mA IZZ Full Sleep Mode Supply Current Device Selected, Outputs Open, CEN < V IH, V DD = Max., V IN > V HD or < V LD, f = fMAX(2,3),ZZ > V HD 40 60 40 60 40 60 40 60 40 60 mA 5313 tbl 22 NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V. 4. 200MHz is for 71T75802 only. AC Test Load AC Test Conditions VDDQ/2 50Ω I/O Input Pulse Levels , Z0 = 50Ω 5313 drw 04 Figure 1. AC Test Load 6 Input Rise/Fall Times (VDDQ/2) Output Timing Reference Levels (VDDQ/2) AC Test Load 1 • • 20 30 50 • • 80 100 Capaci t ance (pF ) 200 5313 dr w 05 Figure 2. Lumped Capacitive Load, Typical Derating 6.42 15 Sep.27.21 See Figure 1 5313 tbl 23 • Δt CD 3 (Ty pi cal , ns ) 2 2ns Input Timing Reference Levels 5 4 0 to 2.5V 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 2.5V +/-5%, Commercial and Industrial Temperature Ranges) 200MHz(6) Symbol Parameter 166MHz 150MHz 133MHz 100MHz Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tCYC Clock Cycle Time 5 ____ 6 ____ 6.7 ____ 7.5 ____ 10 ____ ns (1) tF Clock Frequency ____ 200 ____ 166 ____ 150 ____ 133 ____ 100 MHz tCH(2) Clock High Pulse Width 1.8 ____ 1.8 ____ 2.0 ____ 2.2 ____ 3.2 ____ ns tCL(2) Clock Low Pulse Width 1.8 ____ 1.8 ____ 2.0 ____ 2.2 ____ 3.2 ____ ns Output Parameters tCD Clock High to Valid Data ____ 3.2 ____ 3.5 ____ 3.8 ____ 4.2 ____ 5 ns tCDC Clock High to Data Change 1.0 ____ 1.0 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns tCLZ(3,4,5) Clock High to Output Active 1.0 ____ 1.0 ____ 1.5 ____ 1.5 ____ 1.5 ____ ns tCHZ(3,4,5) Clock High to Data High-Z 1.0 3 1.0 3 1.5 3 1.5 3 1.5 3.3 ns tOE Output Enable Access Time ____ 3.2 ____ 3.5 ____ 3.8 ____ 4.2 ____ 5 ns tOLZ(3,4) Output Enable Low to Data Active 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns tOHZ(3,4) Output Enable High to Data High-Z ____ 3.2 ____ 3.5 ____ 3.8 ____ 4.2 ____ 5 ns Set Up Times tSE Clock Enable Setup Time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns tSA Address Setup Time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns tSD Data In Setup Time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns tSW Read/Write (R/W) Setup Time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns tSADV Advance/Load (ADV/LD) Setup Time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns tSC Chip Enable/Select Setup Time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns tSB Byte Write Enable (BWx) Setup Time 1.4 ____ 1.5 ____ 1.5 ____ 1.7 ____ 2.0 ____ ns tHE Clock Enable Hold Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHA Address Hold Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHD Data In Hold Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHW Read/Write (R/W) Hold Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHADV Advance/Load (ADV/LD) Hold Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHC Chip Enable/Select Hold Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns tHB Byte Write Enable (BWx) Hold Time 0.4 ____ 0.5 ____ 0.5 ____ 0.5 ____ 0.5 ____ ns Hold Times 5313 tbl 24 NOTES: 1. tF = 1/tCYC. 2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ. 3. Transition is measured ±200mV from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 2.625V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 2.375V) 6. 200MHz is for 71T75802 only. 6.42 16 Sep.27.21 Sep.27.21 6.42 17 A1 tSADV tHA tHW tHE tCLZ tHC Pipeline Read tSC A2 tSA tSW tSE tCD Pipeline Read Q(A1) tHADV tCH Q(A2) tCDC tCL Q(A2+1) Q(A2+2) (CEN high, eliminates current L-H clock edge) Burst Pipeline Read tCD Q(A2+2) tCDC Q(A2+3) tCHZ Q(A2) 5313 drw 06 (Burst Wraps around to initial state) NOTES: 1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. DATAOUT OE BW1 - BW4 CE1, CE2 (2) ADDRESS R/W ADV/LD CEN CLK tCYC 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle(1,2,3,4) Sep.27.21 6.42 18 tHW tHB tHC Pipeline Write tSB tSC tHA A2 tSA tSW tHE tHD Pipeline Write D(A1) tSD tHADV tCH D(A2) tCL D(A2+1) Burst Pipeline Write (CEN high, eliminates current L-H clock edge) tSD D(A2+2) tHD D(A2) 5313 drw 07 D(A2+3) (Burst Wraps around to initial state) NOTES: 1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are loaded into the SRAM. 5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAIN OE A1 tSADV tSE Timing Waveform of Write Cycles BW1 - BW4 CE1, CE2 (2) ADDRESS R/W ADV/LD CEN CLK tCYC 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs (1,2,3,4,5) Commercial and Industrial Temperature Ranges Sep.27.21 6.42 19 A1 tSADV tHW tHE tCD tHB tHC Read tSB tSC tHA A2 tSA tSW tSE A3 Q(A1) tCHZ Write tHADV tCH tCLZ Read D(A2) tSD tHD A4 tCL Q(A3) tCDC Write A5 D(A4) A6 Read D(A5) A7 Q(A6) A8 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 5313 drw 08 Q(A7) A9 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of Combined Read and Write Cycles(1,2,3) Sep.27.21 6.42 20 A1 tSE tSADV tHE tHW tHC tCD tCLZ tHB B(A2) tSB tSC tHA A2 tSA tSW tCH tHADV Q(A1) tCL tCHZ tCDC Q(A1) A3 D(A2) tSD tHD A4 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2. 2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOUT DATAIN OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 5313 drw 09 Q(A3) A5 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of CEN Operation (1,2,3,4) Commercial and Industrial Temperature Ranges Sep.27.21 6.42 21 A1 tSADV tHW tHE tSC tCLZ tCD tHC tHA A2 tSA tSW tSE Q(A1) tHADV tCH tCDC tCHZ tHB Q(A2) tSB A3 tCL D(A3) tSD tHD A4 Q(A4) A5 NOTES: 1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3. 2 CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH. 3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal registers in the SRAM will retain their previous state. 4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two cycles before the actual data is presented to the SRAM. DATAOut DATAIn OE BW1 - BW4 CE1, CE2(2) ADDRESS R/W ADV/LD CEN CLK tCYC 5313 drw 10 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Timing Waveform of CS Operation(1,2,3,4) 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges JTAG Interface Specification tJCYC tJF tJCL tJR tJCH TCK Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO tJDC tJH tJRSR tJCD TRST(3) x M5313 drw 01 tJRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. 3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. JTAG AC Electrical Characteristics(1,2,3,4) Symbol Parameter Min. Max. Units tJCYC JTAG Clock Input Period 100 ____ ns tJCH JTAG Clock HIGH 40 ____ ns tJCL JTAG Clock Low 40 ____ ns tJR JTAG Clock Rise Time ____ 5(1) ns tJF JTAG Clock Fall Time ____ 5(1) ns tJRST JTAG Reset 50 ____ ns tJRSR JTAG Reset Recovery 50 ____ ns tJCD JTAG Data Output ____ 20 ns tJDC JTAG Data Output Hold 0 ____ ns tJS JTAG Setup 25 ____ ns tJH JTAG Hold 25 ____ ns Scan Register Sizes Register Name 4 Bypass (BYR) 1 Boundary Scan (BSR) 32 Note (1) I5313 tbl 03 NOTE: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available by contacting your local IDT sales representative. I5313 tbl 01 Guaranteed by design. AC Test Load (Fig. 1) on external output signals. Refer to AC Test Conditions stated earlier in this document. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 6.42 22 Sep.27.21 Instruction (IR) JTAG Identification (JIDR) NOTES: 1. 2. 3. 4. Bit Size 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges JTAG Identification Register Definitions Instruction Field Value Revision Number (31:28) Description 0x2 IDT Device ID (27:12) 0x220, 0x222 IDT JEDEC ID (11:1) 0x33 ID Register Indicator Bit (Bit 0) Reserved for version number. Define s IDT part number 71T75602 and 71T75802, respectively. Allows unique identification of device vendor as IDT. 1 Indicates the presence of an ID register. I5313 tbl 02 Available JTAG Instructions Instruction Description OPCODE (1) EXTEST Forces contents of the boundary scan cells onto the device outputs . Places the boundary scan register (BSR) between TDI and TDO. 0000 SAMPLE/PRELOAD Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. 0001 DEVICE_ID Loads the JTAG ID register (JIDR) with the vendor ID code and places the register between TDI and TDO. 0010 HIGHZ Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. 0011 0100 RESERVED RESERVED RESERVED Several combinations are reserved. Do not use codes other than those identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP, VALIDATE and BYPASS instructions. RESERVED CLAMP RESERVED 0110 0111 Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the byp ass registe r (BYR) between TDI and TDO. RESERVED RESERVED 0101 1000 1001 1010 Same as above. 1011 RESERVED 1100 VALIDATE Automatically loaded into the instruction register whenever the TAP controller passes through the CAPTURE-IR state. The lower two bits '01' are mand ated by the IEEE std. 1149.1 specification. 1101 RESERVED Same as above. 1110 BYPASS The BYPASS instruction is used to truncate the boundary scan register as a single bit in length. 1111 I5313 tbl 04 NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 6.42 23 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges (1) Timing Waveform of OE Operation OE tOE tOHZ tOLZ Valid DATAOUT 5313 drw 11 NOTE: 1. A read operation is assumed to be in progress. Ordering Information S XXXX Device Type XX Power Speed XX X X X Package Blank 8 Tray Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G(2) Green PF BG 100-Pin Plastic Thin Quad Flatpack (PKG100) 119 Ball Grid Array (BG119, BGG119) 200 150 133 100 Clock Frequency in Megahertz S Standard Power 71T75602 512Kx36 Pipelined ZBT SRAM 71T75802 1Mx18 Pipelined ZBT SRAM 5313 drw 12a NOTES: 1. Contact your local sales office for Industrial temp range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. 6.42 24 Sep.27.21 , I C I C C C C C I I I I I C I C C I C I C I C I .e p d ma r eG T P F Q T A G B P P F Q T A G B P P F Q T A G B P P F Q T A G B P A G B P P F Q T A G B P P F Q T A G B P P F Q T I A G B P P F Q T A G B P A G B P A G B P A G B P A G B P A G B P A G B P A G B P . e gp ky PT I 0 0 1 G K P 9 1 1 G G B C 0 0 1 G K P 9 1 1 G G B C 0 0 1 G K P 9 1 1 G G B I 0 0 1 G K P 9 1 1 G B I 9 1 1 G B 9 1 1 G B I 9 1 1 G B 0 0 1 G K P I P F Q T 9 1 1 G G B 0 0 1 G K P 9 1 1 G G B 0 0 1 G K P 9 1 1 G G B 0 0 1 G K P 9 1 1 G G B 9 1 1 G B 9 1 1 G B 9 1 1 G B 9 1 1 G B 9 1 1 G G B .e g d ko PC 8 I G G B 6 6 1 S 2 0 6 5 7 T 1 7 C P F Q T 0 0 1 G K P 8 I G F P 6 6 1 S 2 0 6 5 7 T 1 7 I G G B 6 6 1 S 2 0 6 5 7 T 1 7 C P F Q T 0 0 1 G K P I G F P 6 6 1 S 2 0 6 5 7 T 1 7 8 G G B 6 6 1 S 2 0 6 5 7 T 1 7 C P F Q T 0 0 1 G K P 8 G F P 6 6 1 S 2 0 6 5 7 T 1 7 G G B 6 6 1 S 2 0 6 5 7 T 1 7 C A G B P 0 0 1 G K P 8 I G F P 3 3 1 S 2 0 6 5 7 T 1 7 G F P 6 6 1 S 2 0 6 5 7 T 1 7 8 G B 6 6 1 S 2 0 6 5 7 T 1 7 I A G B P 9 1 1 G B I G F P 3 3 1 S 2 0 6 5 7 T 1 7 8 I G B 6 6 1 S 2 0 6 5 7 T 1 7 G B 6 6 1 S 2 0 6 5 7 T 1 7 I A G B P 9 1 1 G B 8 G F P 3 3 1 S 2 0 6 5 7 T 1 7 I G B 6 6 1 S 2 0 6 5 7 T 1 7 8 I G F P 0 5 1 S 2 0 6 5 7 T 1 7 8 I G G B 0 5 1 S 2 0 6 5 7 T 1 7 I G F P 0 5 1 S 2 0 6 5 7 T 1 7 I G G B 0 5 1 S 2 0 6 5 7 T 1 7 8 G F P 0 5 1 S 2 0 6 5 7 T 1 7 8 G G B 0 5 1 S 2 0 6 5 7 T 1 7 G F P 0 5 1 S 2 0 6 5 7 T 1 7 G G B 0 5 1 S 2 0 6 5 7 T 1 7 8 I G B 0 5 1 S 2 0 6 5 7 T 1 7 8 G B 0 5 1 S 2 0 6 5 7 T 1 7 I G B 0 5 1 S 2 0 6 5 7 T 1 7 G B 0 5 1 S 2 0 6 5 7 T 1 7 I A G B P 9 1 1 G G B G F P 3 3 1 S 2 0 6 5 7 T 1 7 9 1 1 G G B 8 I G B 3 3 1 S 2 0 6 5 7 T 1 7 8 I G G B 3 3 1 S 2 0 6 5 7 T 1 7 I G B 3 3 1 S 2 0 6 5 7 T 1 7 166 I G G B 3 3 1 S 2 0 6 5 7 T 1 7 6.42 25 D I t r a P e l b a r e d r O 0 5 1 I C A G B P C A G B P C A G B P C A G B P .e p d ma r eG T A G B P A G B P A G B P A G B P A G B P A G B P A G B P A G B P 9 1 1 G G B .e g p ky PT 9 1 1 G G B 9 1 1 G G B 9 1 1 G B 9 1 1 G G B 9 1 1 G B 9 1 1 G G B 9 1 1 G B 9 1 1 G B 9 1 1 G B 9 1 1 G B 9 1 1 G G B .e g d ko PC 8 G G B 3 3 1 S 2 0 6 5 7 T 1 7 8 I G G B 0 0 1 S 2 0 6 5 7 T 1 7 G G B 3 3 1 S 2 0 6 5 7 T 1 7 I G G B 0 0 1 S 2 0 6 5 7 T 1 7 8 G B 3 3 1 S 2 0 6 5 7 T 1 7 8 G G B 0 0 1 S 2 0 6 5 7 T 1 7 G B 3 3 1 S 2 0 6 5 7 T 1 7 G G B 0 0 1 S 2 0 6 5 7 T 1 7 8 I G B 0 0 1 S 2 0 6 5 7 T 1 7 8 G B 0 0 1 S 2 0 6 5 7 T 1 7 3 3 1 I G B 0 0 1 S 2 0 6 5 7 T 1 7 G B 0 0 1 S 2 0 6 5 7 T 1 7 0 0 1 Sep.27.21 Speed (MHz) Speed (MHz) D I t r a P e l b a r e d r O Orderable Part Information Commercial and Industrial Temperature Ranges 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Orderable Part Information (con’t) Speed Orderable Part ID (MHz) 100 133 150 Pkg. Code Pkg. Type Temp. Grade 71T75802S100BG BG119 PBGA C 71T75802S100BG8 BG119 PBGA C 71T75802S100BGGI BGG119 PBGA 71T75802S100BGGI8 BGG119 71T75802S100BGI Pkg. Code Pkg. Type Temp. Grade 71T75802S166BG BG119 PBGA C 71T75802S166BG8 BG119 PBGA C I 71T75802S166BGG BGG119 PBGA C PBGA I 71T75802S166BGG8 BGG119 PBGA C BG119 PBGA I 71T75802S166BGGI BGG119 PBGA I 71T75802S100BGI8 BG119 PBGA I 71T75802S166BGGI8 BGG119 PBGA I 71T75802S133BG BG119 PBGA C 71T75802S166BGI BG119 PBGA I 71T75802S133BG8 BG119 PBGA C 71T75802S166BGI8 BG119 PBGA I 71T75802S133BGG BGG119 PBGA C 71T75802S166PFG PKG100 TQFP C 71T75802S133BGG8 BGG119 PBGA C 71T75802S166PFG8 PKG100 TQFP C 71T75802S133BGGI BGG119 PBGA I 71T75802S166PFGI PKG100 TQFP I 71T75802S133BGGI8 BGG119 PBGA I 71T75802S166PFGI8 PKG100 TQFP I 71T75802S133BGI BG119 PBGA I 71T75802S200BG BG119 PBGA C 71T75802S133BGI8 BG119 PBGA I 71T75802S200BG8 BG119 PBGA C 71T75802S133PFG PKG100 TQFP C 71T75802S200BGG BGG119 PBGA C 71T75802S133PFG8 PKG100 TQFP C 71T75802S200BGG8 BGG119 PBGA C 71T75802S133PFGI PKG100 TQFP I 71T75802S200BGI BG119 PBGA I 71T75802S133PFGI8 PKG100 TQFP I 71T75802S200BGI8 BG119 PBGA I 71T75802S150BG BG119 PBGA C 71T75802S200PFG PKG100 TQFP C 71T75802S150BG8 BG119 PBGA C 71T75802S200PFG8 PKG100 TQFP C 71T75802S150BGG BGG119 PBGA C 71T75802S200PFGI PKG100 TQFP I 71T75802S150BGG8 BGG119 PBGA C 71T75802S200PFGI8 PKG100 TQFP I 71T75802S150BGGI BGG119 PBGA I 71T75802S150BGGI8 BGG119 PBGA I BG119 PBGA I 71T75802S150BGI8 BG119 PBGA I 71T75802S150PFG PKG100 TQFP C 71T75802S150PFG8 PKG100 TQFP C 71T75802S150BGI Speed Orderable Part ID (MHz) 166 200 6.42 26 Sep.27.21 71T75602, 71T75802, 512K x 36, 1M x 18, 2.5V Synchronous SRAMs with ZBT™ 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History Date 04/20/00 05/25/00 08/23/01 10/16/01 10/29/01 12/21/01 06/07/02 11/19/02 05/23/03 04/01/04 10/01/08 04/04/12 10/04/17 09/27/21 Pages Description Created New Datasheet Pg.1,14,15,25 Added 166MHz speed grade offering Pg. 1,2,14 Corrected error in ZZ Sleep Mode Pg. 23 AddBQ165 Package Diagram Outline Pg. 24 Corrected 119BGA Package Diagram Outline. Pg. 25 Corrected topmark on ordering information Pg. 1,2,24 Removed reference of BQ165 Package Pg. 7 Removed page of the 165 BGA pin configuration Pg. 23 Removed page of the 165 BGA package diagram outline Pg. 6 Corrected 3.3V to 2.5V in Note 2 Pg. 13 Improved DC Electrical characteristics-parameters improved: Icc, ISB2, ISB3, IZZ. Pg. 4-6 Added clarification to JTAG pins, allow for NC. Added 36M address pin locations. Pg. 14 Revised 166MHz tCDC(min), tCLZ(min) and tCHZ(min) to 1.0ns Pg. 1-3,6,13,20,21 Added complete JTAG functionality. Pg. 2,13 Added notes for ZZ pin internal pulldown and ZZ leakage current. Pg. 13,14,24 Added 200MHz and 225MHz to DC and AC Electrical Characteristics. Updated supply current for Idd, ISB1, ISB3 and Izz. Pg.1-24 Changed datasheet from Advanced Information to final release. Pg.13 Updated DC Electrical characteristics temperature and voltage range table. Pg.4,5,13,14,24 Added I-temp to the datasheet. Pg.5 Updated 165 BGA Capacitance table. Pg. 1 Updated logo with new design. Pg. 4,5 Clarified ambient and case operating temperatures. Pg. 6 Updated pin I/O number order for the 119 BGA. Pg. 23 Updated 119BGA Package Diagram Drawing. Pg. 1,13,14,24 Deleted 225MHz part, added 200MHz Industrial grade and added green packages. Updated the ordering information by removing the “IDT” notation. Pg. 2,22 Updated text on Page 2 last paragraph. Added Note to ordering information and updated to include tube or tray and tape & reel. Pg. 1 & 26 Updated IDT logo from Trademark to Registered Pg. 1- 4 In Features: Added text: "Green parts available, see Ordering Information" Moved the 512Kx36 FBD from page 3 to page 1, moved the 1Mx18 FBD from page 3 to page 2, moved the Pin Description Summary from page 1 to page 3 and moved the Pin Definitions from page 2 to page 4 in accordance with our standard datasheet format Pg. 5 & 6 Updated the TQFP pin configurations for the 512kx36 and 1Mx18 by rotating package pin labels and pin numbers 90 degrees counter clockwise, added IDT logo & in accordance with the packaging code, changed the PK100 designation to PKG100 , changed the text to be in alignment with new diagram marking specs Pg. 6 Removed fBGA capacitance table as this package is no longer offered for this device Pg. 12 Removed “? = don’t know” from Burst Write Operation footnote 1 as it does not apply to this table Pg. 15 Updated DC Chars table added footnote 4 & reference 4 for the 512K x 36, 119 BGA 200Mhz speed offered only for the 71T75802 device Pg. 16 Updated AC Chars table added footnote 6 & reference 6 for the 1M x 18, 119 BGA 200Mhz speed offered only for the 71T75802 device Pg. 24 Ordering Information updated to Tray and Green indicator Updated package codes TQFP to PKG100 and BGA to BGG119 Pg. 24-25 Added Orderable Part Information from idt.com Pg. 1-27 Rebranded as Renesas datasheet Pg. 1 & 24 Updated Industrial temp range and green availability Pg. 5-7 & 24 Updated package codes Pg. 24-25 Updated Orderable Part Information tables by correcting “ns” to “MHz” 6.42 27 Sep.27.21 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.