71V124SA12YGI

3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 71V124SA Description 128K x 8 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 10/12/15ns One Chip Select plus one Output Enable pin Inputs and outputs are LVTTL-compatible Single 3.3V supply Low power consumption via chip deselect Available in a 32-pin 300- and 400-mil Plastic SOJ, and 32-pin Type II TSOP packages Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information The IDT71V124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. Functional Block Diagram A0 • • • ADDRESS • • • 1,048,576-BIT MEMORY ARRAY DECODER A16 8 8 I/O0 - I/O7 I/O CONTROL . 8 WE OE CS CONTROL LOGIC 3873 drw 01 1 Jun.30.20 71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Pin Configurations(1) Absolute Maximum Ratings(1) Symbol A0 A1 A2 A3 CS I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 71V124 28 PJG32 27 PBG32 26 PHG32 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8 Rating SOJ and TSOP Top View Supply Voltage Relative to GND -0.5 to +4.6 V VIN, VOUT Terminal Voltage Relative to GND -0.5 to VDD+0.5 V Commercial Operating Temperature -0 to +70 Industrial Operating Temperature -40 to +85 TBIAS Temperature Under Bias TSTG Storage Temperature CS OE WE I/O L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected – Standby Function (TA = +25°C, f = 1.0MHz, SOJ package) CI/O I/O Capacitance C -55 to +125 o C Power Dissipation 1.25 W IOUT DC Output Current 50 mA Grade Temperature GND VDD Commercial 0°C to +70°C 0V See Below Industrial -40°C to +85°C 0V See Below Recommended DC Operating Conditions 3873 tbl 01 Capacitance Input Capacitance o PT Symbol CIN -55 to +125 3873 tb l 02a NOTE: 1. H = VIH, L = VIL, X = Don't care. Conditions C Recommended Operating Temperature and Supply Voltage Truth Table(1) Parameter(1) o 3873 tbl 02 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: 1. This text does not indicate oriebtation of actual part-marking. Symbol Unit VDD TA 3873 drw 02 Value Max. 6 pF VOUT = 3dV 7 pF Min. Typ. Max. Unit VDD(1) Supply Voltage 3.15 3.3 3.6 V VDD(2) Supply Voltage 3.0 3.3 3.6 V 0 0 0 VSS Unit VIN = 3dV Parameter Ground VIH Input High Voltage 2.0 ____ VIL Input Low Voltage –0.5(1) ____ VDD+0.3 0.8 NOTES: 1. For 71V124SA10 only. 2. For all speed grades except 71V124SA10. 3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 4. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. 3873 tbl 03 NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. DC Electrical Characteristics V (3) V V 3873 tbl 04 (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) Symbol Parameter Test Conditions Min. Max. Unit 5 µA |ILI| Input Leakage Current VDD = Max., VIN = GND to VDD ___ |ILO| Output Leakage Current VDD = Max.,CS = VIH, VOUT = GND to VDD ___ 5 µA VOL Output Low Voltage IOL = 8mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = –4mA, VDD = Min. 2.4 ___ V 3873 tbl 05 2 Jun.30.20 71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges DC Electrical Characteristics(1, 2) (VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V) 71V124SA10 Symbol Parameter 71V124SA12 71V124SA15 Commercial Com'l Ind Com'l Ind Unit ICC Dynamic Operating Current CS < VLC, Outputs Open, V DD = Max., f = fMAX(3) 145 130 140 100 120 mA ISB Dynamic Standby Power Supply Current CS > VHC, Outputs Open, V DD = Max., f = fMAX(3) 45 40 40 35 40 mA ISB1 Full Standby Power Supply Current (static) CS > VHC, Outputs Open, V DD = Max., f = 0(3) 10 10 10 10 10 mA 3873 tbl 06 NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD–0.2V (High). 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. AC Test Conditions GND to 3.0V Input Pulse Levels Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V 1.5V Output Reference Levels See Figure 1 and 2 AC Test Load 3873 tbl 07 3.3V 320Ω +1.5V DATAOUT 50Ω I/O 5pF* Z0 = 50Ω 350Ω 30pF 3873 drw 03 . 3873 drw 04 Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 3 6.42 Jun.30.20 71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) Symbol Parameter 71V124SA10 71V124SA12 71V124SA15 Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ns (1) tCLZ Chip Select to Output in Low-Z 4 ____ 4 ____ 4 ____ ns tCHZ(1) Chip Deselect to Output in High-Z 0 5 0 6 0 7 ns tOE Output Enable to Output Valid ____ 5 ____ 6 ____ 7 ns tOLZ(1) Output Enable to Output in Low-Z 0 ____ 0 ____ 0 ____ ns tOHZ Output Disable to Output in High-Z 0 5 0 5 0 5 ns tOH Output Hold from Address Change 4 ____ 4 ____ 4 ____ ns (1) WRITE CYCLE tWC Write Cycle Time 10 ____ 12 ____ 15 ____ ns tAW Address Valid to End-of-Write 7 ____ 8 ____ 10 ____ ns tCW Chip Select to End-of-Write 7 ____ 8 ____ 10 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 7 ____ 8 ____ 10 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 5 ____ 6 ____ 7 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tOW(2) Output Active from End-of-Write 3 ____ 3 ____ 3 ____ ns tWHZ(2) Write Enable to Output in High-Z 0 5 0 5 0 5 ns NOTES: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 4 Jun.30.20 3873 tbl 08 71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tAA OE tOE tOLZ (5) CS tACS(3) tCLZ tOHZ (5) (5) tCHZ (5) HIGH IMPEDANCE DATAOUT . DATAOUT VALID 3873 drw 05 Timing Waveform of Read Cycle No. 2(1, 2, 4) tRC ADDRESS tAA tOH DATAOUT tOH PREVIOUS DATAOUT VALID DATAOUT VALID 3873 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 5 6.42 Jun.30.20 . 71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tWP tAS (2) tWR WE tCHZ (5) tOW (5) tWHZ (5) HIGH IMPEDANCE (3) DATAOUT (3) tDW DATAIN tDH . DATAIN VALID 3873 drw 07 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4) tWC ADDRESS tAW CS tAS (3) tWR tCW WE tDW DATAIN tDH DATAIN VALID 3873 drw 08 . NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6 Jun.30.20 71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Ordering Information 71V124 Device Type SA XX Power Speed X Package X X X Process/ Temperature Range Blank 8 Tube Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green TY Y PH 300-mil SOJ (PJG32) 400-mil SOJ (PBG32) TSOP Type II (PHG32) 10 12 15 Speed in nanoseconds NOTE: 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 3873 drw 09 Orderable Part Information Pkg. Code Pkg. Type Temp. Grade Speed (ns) Pkg. Code Pkg. Type Temp. Grade 71V124SA10PHG PHG32 TSOP C 15 71V124SA15PHG PHG32 TSOP C 71V124SA10PHG8 PHG32 TSOP 71V124SA10PHGI PHG32 TSOP C 71V124SA15PHG8 PHG32 TSOP C I 71V124SA15PHGI PHG32 TSOP I 71V124SA10PHGI8 PHG32 TSOP I 71V124SA15PHGI8 PHG32 TSOP I 71V124SA10TYG 71V124SA10TYG8 PJG32 SOJ C 71V124SA15TYG PJG32 SOJ C PJG32 SOJ C 71V124SA15TYG8 PJG32 SOJ C 71V124SA10YG PBG32 SOJ C 71V124SA15TYGI PJG32 SOJ I 71V124SA10YG8 PBG32 SOJ C 71V124SA15TYGI8 PJG32 SOJ I 71V124SA12PHG PHG32 TSOP C 71V124SA15YG PBG32 SOJ C 71V124SA12PHG8 PHG32 TSOP C 71V124SA15YG8 PBG32 SOJ C 71V124SA12PHGI PHG32 TSOP I 71V124SA15YGI PBG32 SOJ I 71V124SA12PHGI8 PHG32 TSOP I 71V124SA15YGI8 PBG32 SOJ I 71V124SA12TYG PJG32 SOJ C 71V124SA12TYG8 PJG32 SOJ C 71V124SA12TYGI PJG32 SOJ I Speed (ns) 10 12 Orderable Part ID 71V124SA12TYGI8 PJG32 SOJ I 71V124SA12YG PBG32 SOJ C 71V124SA12YG8 PBG32 SOJ C 71V124SA12YGI PBG32 SOJ I 71V124SA12YGI8 PBG32 SOJ I 7 6.42 Jun.30.20 Orderable Part ID IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Datasheet Document History 11/22/99 08/30/00 08/22/01 11/30/03 01/30/04 2/14/07 10/13/08 11/15/10 03/29/12 02/19/13 03/10/17 06/30/20 Pg. 1–4, 7 Pg. 2 Pg. 6 Pg. 8 Pg. 3 Pg. 4 Pg. 7 Pg. 1,3,7 Pg. 7 Pg. 7 Pg. 7 Pg. 1,3,4,7 Pg. 7 Pg. 1 Pg. 2 Pg. 1 - 9 Pg. 2 & 7 Pg. 1 & 7 Pg. 7 Updated to new format Added Industrial Temperature range offerings Added Recommended Operating Temperature and Supply Voltage table Revised footnotes on Write Cycle No. 1 diagram Added Datasheet Document History Tighten ICC and ISB Tighten AC Characteristics tOHZ, tOW and tWHZ Removed footnote "400-mil SOJ package only offered in 10ns and 12ns speed grade" Added Industrial temperature offering 10ns speed grade Added "Restricted hazardous substance device" to ordering information Added H generation die step to data sheet ordering information Removed "IDT" from the orderable part number Removed 20ns commercial, 10ns & 20ns industrial and also removed HSA offering Removed die step indicator from the ordering information Added tape and reel and green to the ordering information Removed IDT reference to fabrication and changed fastest access address time from 9ns to 10ns Updated pin configurations with correct package codes and with new IDT logo Rebranded as Renesas datasheet Updated package codes Updated Industrial temp range and green availability Added Orderable Part Information table 8 Jun.30.20 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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