71V321L35JG8

HIGH SPEED 3.3V 2K X 8 DUAL-PORT STATIC RAM WITH INTERRUPTS Features ◆ ◆ ◆ ◆ ◆ High-speed access – Commercial & Industrial: 25/35ns (max.) Low-power operation – IDT71V321L — Active: 325mW (typ.) — Standby: 1mW (typ.) Two INT flags for port-to-port communications On-chip port arbitration logic (IDT71V321 only) BUSY output flag ◆ ◆ ◆ ◆ ◆ ◆ 71V321L Fully asynchronous operation from either port Battery backup operation—2V data retention (L only) TTL-compatible, single 3.3V power supply Available in 52-pin PLCC, 64-pin TQFP and STQFP packages Industrial temperature range (–40°C to +85°C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram OEL OER CEL R/WL CER R/WR I/O0L- I/O7L I/O0R-I/O7R I/O Control BUSYL I/O Control (1,2) A10L A0L (1,2) BUSYR Address Decoder MEMORY ARRAY 11 CEL OEL R/WL Address Decoder A10R A0R 11 ARBITRATION and INTERRUPT LOGIC CER OER R/WR (2) (2) INTR INTL 3026 drw 01 NOTES: 1. IDT71V321 (MASTER): BUSY is an output 2. BUSY and INT are totem-pole outputs. JULY 2019 1 ©2019 Integrated Device Technology, Inc. DSC-3026/14 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Description The IDT71V321 is a high-speed 2K x 8 Dual-Port Static RAMs with internal interrupt logic for interprocessor communications. The IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port RAM. The device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices typically operate on only 325mW of power. Low-power (L) versions offer battery backup data retention capability, with each Dual-Port typically consuming 200µW from a 2V battery. The IDT71V321 devices are packaged in a 52-pin PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP (super thin quad flatpack). I/O 3L I/O 2L I/O 1L I/O 0L A9L A8L A7L A6L A5L A4L A3L A2L A1L Pin Configurations(1,2,3) NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. J52-1 package body is approximately .75 in x .75 in x .17 in. PP64-1 package body is approximately 10mm x 10mm x 1.4mm. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. A 0L OEL A10L INTL BUSYL R/WL CEL VCC CER R/WR BUSYR INTR A10R OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R N/C A 7R A 8R A 9R N/C N/C I/O 7R I/O 6R 3026 drw 02 N/C N/C A10R INTR BUSYR R/WR CER VCC VCC CEL R/W L BUSYL INT L A10L N/C N/C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 71V321 55 26 PPG64(4) 56 25 PNG64(4) 57 24 64-Pin STQFP 58 23 64-Pin TQFP 59 22 Top View 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OEL A0L A1L A2L A3L A4L A5L A6L N/C A7L A8L A9L N/C I/O0L I/O1L I/O2L 20 19 18 17 16 15 14 13 12 11 10 9 8 7 21 6 22 5 23 4 24 3 25 71V321 2 26 PLG52(4) 1 27 52-Pin PLCC 52 28 Top View 51 29 50 30 49 31 48 32 33 47 34 35 36 37 38 39 40 41 42 43 44 45 46 I/O7R NC A 9R A 8R A 7R A 6R A 5R A 4R A 3R A 2R A 1R A 0R OER I/O 4L I/O 5L I/O 6L I/O 7L NC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R 2 6.42 I/O5R I/O4R N/C I/O 3R I/O 2R I/O 1R I/O 0R GND GND N/C I/O 7L I/O 6L I/O 5L I/O 4L N/C I/O 3L 3026 drw 03 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Unit -0.5 to +4.6 V Grade Ambient Temperature GND Vcc 0OC to +70OC 0V 3.3V + 0.3V -40OC to +85OC 0V 3.3V + 0.3V Commercial Operating Temperature TA Commercial & Industrial Recommended Operating Temperature and Supply Voltage(1,2) 0 to +70 Industrial °C TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -65 to +150 o C IOUT DC Output Current 50 3026 tbl 02 NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. mA 3026 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%. Recommended DC Operating Conditions Symbol Parameter VCC Supply Voltage GND Ground VIH Input High Voltage VIL Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 2.0 ____ (1) Input Low Voltage -0.3 VCC+0.3 0.8 ____ V V 3026 tbl 03 NOTES: 1. VIL (min.) = -1.5V for pulse width less than 20ns. 2. VTERM must not exceed Vcc + 0.3V. Capacitance(1) V (2) (TA = +25°C, f = 1.0MHz) TQFP Only Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions(2) Max. Unit VIN = 3dV 9 pF VOUT = 3dV 10 pF 3026 tbl 04 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V) 71V321S Symbol Parameter Test Conditions 71V321L Min. Max. Min. Max. Unit |ILI| Input Leakage Current(1) V CC = 3.6V, V IN = 0V to V CC ___ 10 ___ 5 µA |ILO| Output Leakage Current CE = V IH, V OUT = 0V to V CC V CC = 3.6V ___ 10 ___ 5 µA V OL Output Low Voltage IOL = 4mA ___ 0.4 ___ 0.4 V V OH Output High Voltage IOH = -4mA 2.4 ___ 2.4 ___ V 3026 tbl 05 NOTE: 1. At VCC < 2.0V input leakages are undefined. 3 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2) (VCC = 3.3V ± 0.3V) Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Test Condition Dynamic Operating Current (Both Ports Active) CE = V IL, Outputs Disabled SEM = V IH f = fMAX(3) Standby Current (Both Ports - TTL Level Inputs) Version 71V321X25 Com'l & Ind 71V321X35 Com'l & Ind 71V321X55 Com'l & Ind Typ. Max. Typ. Max. Typ. Max. Unit mA COM'L S L 55 55 130 100 55 55 125 95 55 55 115 85 IND L 55 130 55 125 55 115 CER = CEL = V IH SEMR = SEML = V IH f = fMAX(3) COM'L S L 15 15 35 20 15 15 35 20 15 15 35 20 IND L 15 35 15 35 15 35 Standby Current (One Port - TTL Level Inputs) CE"A" = V IL and CE"B" = V IH(5) Active Port Outputs Disabled, f=fMAX(3) SEMR = SEML = V IH COM'L S L 25 25 75 55 25 25 70 50 25 25 60 40 IND L 25 75 25 70 25 60 Full Standby Current (Both Ports - All CMOS Level Inputs) Both Ports CEL and CER > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(4) SEMR = SEML > V CC - 0.2V COM'L S L 1.0 0.2 5 3 1.0 0.2 5 3 1.0 0.2 5 3 IND L 0.2 6 1.0 5 1.0 5 CE"A" < 0.2V and CE"B" > V CC - 0.2V (5) SEMR = SEML > V CC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX(3) COM'L S L 25 25 70 55 25 25 65 50 25 25 55 40 IND L 25 70 25 65 25 55 Full Standby Current (One Port - All CMOS Level Inputs) mA mA mA mA 3026 tbl 06 NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.). 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Port "A" may be either left or right port. Port "B" is opposite from port "A". Data Retention Characteristics (L Version Only) Symbol Parameter Test Condition Min. Typ. (1) Max. Unit 2.0 ___ 0 V VDR VCC for Data Retention ICCDR Data Retention Current VCC = 2V, CE > VCC - 0.2V COM'L. ___ 100 500 µA tCDR(3) Chip Deselect to Data Retention Time VIN > VCC - 0.2V or VIN < 0.2V IND. ___ 100 1000 µA 0 ___ ___ V tRC(2) ___ ___ V tR(3) Operation Recovery Time NOTES: 1. VCC = 2V, TA = +25°C, and is not production tested. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but not production tested. 4 6.42 3026 tbl 07 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts AC Test Conditions Industrial and Commercial Temperature Ranges Data Retention Waveform Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load DATA RETENTION MODE VCC 3.0V t CDR Figures 1 and 2 3026 tbl 08 VDR ≥ 2.0V 3.0V tR VDR CE VIH VIH 3026 drw 04 3.3V 3.3V 590Ω DATAOUT BUSY INT 435Ω 590Ω DATAOUT 435Ω 30pF 5pF 3026 drw 05 Figure 1. AC Output Test Load Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * Including scope and jig. AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(2) 71V321X25 Com'l & Ind Symbol Parameter 71V321X35 Com'l & Ind 71V321X55 Com'l & Ind Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 25 ____ 35 ____ 55 ____ ns tAA Address Access Time ____ 25 ____ 35 ____ 55 ns tACE Chip Enable Access Time ____ 25 ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 12 ____ 20 ____ 25 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time (1,2) ____ 12 ____ 15 ____ 30 ns tPU Chip Enable to Power Up Time(2) 0 ____ 0 ____ 0 ____ ns ____ 50 ____ 50 ____ 50 ns tPD Chip Disable to Power Down Time (2) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part numbers indicates power rating (S or L). 5 6.42 3026 tbl 09 , 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle No. 1, Either Side(1) tRC ADDRESS tAA tOH tOH DATAOUT PREVIOUS DATA VALID DATA VALID BUSYOUT 3026 drw 06 tBDD (2,3) NOTES: 1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW. 2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relationship to valid output data. 3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. Timing Waveform of Read Cycle No. 2, Either Side (3) tACE CE tAOE (4) tHZ (2) OE tLZ (1) tHZ VALID DATA DATAOUT tLZ ICC CURRENT ISS (2) (1) tPD tPU 50% (4) 50% 3026 drw 07 NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE. 3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD. 6 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4) 71V321X25 Com'l & Ind Symbol Parameter 71V321X35 Com'l & Ind 71V321X55 Com'l & Ind Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 25 ____ 35 ____ 55 ____ ns tEW Chip Enable to End-of-Write 20 ____ 30 ____ 40 ____ ns tAW Address Valid to End-of-Write 20 ____ 30 ____ 40 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 20 ____ 30 ____ 40 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 12 ____ 20 ____ 20 ____ ns ____ 12 ____ 15 ____ 30 ns 0 ____ 0 ____ 0 ____ ns ____ 15 ____ 15 ____ 30 ns 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time tDH Data Hold Time(3) (1,2) (1,2) tWZ Write Enable to Output in High-Z tOW Output Active from End-of-Write(1,2) 3026 tbl 10 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization but is not production tested. 3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 4. 'X' in part numbers indicates power rating (S or L). 7 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8) tWC ADDRESS tHZ (7) OE tAW CE tAS(6) tWP(2) tHZ (7) tWR (3) R/W tOW tWZ (7) (4) DATAOUT (4) tDW tDH DATAIN 3026 drw 08 Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5) tWC ADDRESS tAW CE tAS (6) tEW (2) tWR (3) R/W tDW tDH DATA IN 3026 drw 09 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL. 3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle. 4. During this period, the l/O pins are in the output state and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 8 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) 71V321X25 Com'l & Ind Symbol Parameter 71V321X35 Com'l & Ind 71V321X55 Com'l & Ind Min. Max. Min. Max. Min. Max. Unit BUSY Access Time from Address ____ 20 ____ 20 ____ 30 ns tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 30 ns tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 20 ____ 30 ns 12 ____ 15 ____ 20 ____ ns ____ 50 ____ 60 ____ 80 ns ____ 35 ____ 45 ____ 65 ns 5 ____ 5 ____ 5 ____ ns ____ 30 ____ 30 ____ 45 BUSY Timing tBAA tWH Write Hold After BUSY (5) (1) tWDD Write Pulse to Data Delay tDDD Write Data Valid to Read Data Delay(1) tAPS tBDD Arbitration Priority Set-up Time BUSY Disable to Valid Data (2) (3) ns 3026 tbl 11 NOTES: 1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that a write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4) tWC ADDR"A" MATCH tWP R/W"A" tDW DATAIN"A" tDH VALID tAPS (1) ADDR"B" MATCH tBDD tBDA tBAA BUSY"B" tWDD DATAOUT"B" VALID tDDD 3026 drw 10 NOTES: 1. To ensure that the earlier of the two ports wins. 2 . CEL = CER = VIL 3 . OE=VILforthereadingport. 4 . Alltimingisthesamefortheleftandrightports.Port“A”maybeeithertheleftorrightport.Port“B”isoppositefromport“A”. 9 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Timing Waveform of Write with BUSY(3) tWP R/W"A" BUSY"B" tWH (1) , R/W"B" (2) NOTES: 1. tWH must be met for BUSY output 71V321. 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH. 3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A". 3026 drw 11 Timing Waveform of BUSY Arbitration Controlled by CE Timing(1) ADDR "A" AND "B" ADDRESSES MATCH CE"B" tAPS(2) CE"A" tBAC tBDC BUSY"A" 3026 drw 12 Timing Waveform of BUSY Arbitration Controlled by Address Match Timing(1) tRC ADDR"A" OR tWC ADDRESSES MATCH tAPS ADDRESSES DO NOT MATCH (2) ADDR"B" tBAA tBDA BUSY"B" 3026 drw 13 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. 10 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 71V321X25 Com'l & Ind Symbol Parameter 71V321X35 Com'l & Ind 71V321X55 Com'l & Ind Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 25 ____ 45 ns tINR Interrupt Reset Time ____ 25 ____ 25 ____ 45 ns 3026 tbl 12 NOTES: 1. 'X' in part numbers indicates power rating (S or L). Timing Waveform of Interrupt Mode(1) SET INT tWC ADDR"A" INTERRUPT ADDRESS (2) tWR (4) tAS (3) R/W"A" tINS (3) INT"B" 3026 drw 14 CLEAR INT tRC INTERRUPT CLEAR ADDRESS(2) ADDR"B" tAS(3) OE"B" tINR(3) , INT"B" 3026 drw 15 NOTES:. 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 11 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Truth Tables Table I — Non-Contention Read/Write Control(4) Left or Right Port(1) R/W CE OE D0-7 Function X H X Z Port Deselected and in PowerDown Mode. ISB2 or ISB4 X H X Z CER = CEL = VIH, Power-Down Mode ISB1 or ISB3 L L X DATAIN H L L DATAOUT H L H Z Data on Port Written Into Memory (2) Data in Memory Output on Port(3) High-impedance Outputs NOTES: 1. A0L – A10L ≠ A0R – A10R. 2. If BUSY = L, data is not written. 3. If BUSY = L, data may not be valid, see tWDD and tDDD timing. 4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance. 3026 tbl 13 Table II — Interrupt Flag(1,4) Left Port R/WL CEL L X X X X L INTL 7FF X X X A10L-A0L OEL L X Right Port L X R/WR CER X X X A10R-A0R X INTR Function (2) Set Right INTR Flag (3) Reset Right INTR Flag L X X X L L 7FF H X (3) L L X 7FE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag L 7FE H 3026 tbl 14 NOTES: 1. Assumes BUSYL = BUSYR = VIH 2. If BUSYL = VIL, then No Change. 3. If BUSYR = VIL, then No Change. 4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE Table III — Address BUSY Arbitration Inputs OER Outputs CEL CER AOL-A10L AOR-A10R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 3026 tbl 15 NOTES: 1. Pins BUSYL and BUSYR are both outputs. BUSYX outputs on the IDT71V321 are totempole. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 12 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges The IDT7V1321 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT71V321 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE = VIH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 7FE (HEX), where a write is defined as the CER = R/WR = VIL per Truth Table II. The left port clears the interrupt by accessing address location 7FE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 7FF (HEX) and to clear the interrupt flag (INTR), the right port must access the memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined, since it is an addressable SRAM location. If the interrupt function is not used, address locations 7FE and 7FF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table II for the interrupt operation. MASTER Dual Port RAM BUSYL BUSYL MASTER Dual Port RAM BUSYL Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “Busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY Logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. Depth Expansion The BUSY arbitration, is based on the chip enable and address signals only. It ignores whether an access is a read or write. The BUSY outputs on the IDT71V321 are totem-pole type outputs and do not require pull-up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate DECODER Functional Description CE BUSYR CE BUSYR BUSYR 3026 drw 16 Figure 3. Busy and chip enable routing for depth expansion with IDT71V321. 13 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Ordering Information XXXXX A 999 A Device Type Power Speed Package A A A Process/ Temperature Range Blank 8 Tube of Tray Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Green J PF TF 52-pin PLCC (PLG52) 64-pin TQFP (PNG64) 64-pin STQFP (PPG64) 25 35 Commercial & Industrial Commercial & Industrial L Low Power 71V321 16K (2K x 8-Bit) MASTER 3.3V Dual-Port RAM w/Interrupt Speed in nanoseconds 3026 drw 17 NOTES: 1. Contact your sales office Industrial temperature range is available for selected speeds, packages and powers. LEAD FINISH (SnPb) parts are Obsolete. Product Discontinuation Notice - PDN# SP-17-02 Note that information regarding recently obsoleted parts are included in this datasheet for customer convenience. Orderable Part Information Speed (ns) 25 35 Pkg. Code Pkg. Type Temp. Grade PLG52 PLCC C 71V321L25JG8 PLG52 PLCC C 71V321L25PFG PNG64 TQFP C 71V321L25PFG8 PNG64 TQFP C 71V321L25PFGI PNG64 TQFP I 71V321L25PFGI8 PNG64 TQFP I 71V321L25TFG PPG64 TQFP C 71V321L25TFG8 PPG64 TQFP C 71V321L25TFGI PPG64 TQFP I 71V321L35JG PLG52 PLCC C 71V321L35JG8 PLG52 PLCC C 71V321L35JGI PLG52 PLCC I 71V321L35JGI8 PLG52 PLCC I Orderable Part ID 71V321L25JG 71V321L35PFGI PNG64 TQFP I 71V321L35PFGI8 PNG64 TQFP I 14 6.42 71V321L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges Datasheet Document History 03/24/99: 06/15/99: 10/15/99: 10/21/99: 11/12/99: 01/12/01: 08/22/01: 01/17/06: 08/25/06: 10/23/08: 01/25/10: 06/25/15: 10/14/15: 01/12/18: 07/23/19: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 Added additional notes to pin configurations Changed drawing format Page 12 Changed open drain to totem-pole in Table III, note 1 Page 13 Deleted 'does not' in copy from Busy Logic Replaced IDT logo Page 1 & 2 Moved full "Description" to page 2 and adjusted page layouts Page 3 Increased storage temperature parameters Clarified TA parameter Page 4 DC Electrical parameters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes Page 4, 5, 7, 9 &11 Industrial temp range offering removed from DC & AC Electrical Chars for 35 and 55ns Page 1 Added green availability to features Page 14 Added green indicator to ordering information Page 1 & 14 Replaced old IDTTM with new IDTTM logo Page 11 Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode Page 14 Removed "IDT" from orderable part number Page 4 In order to correct the DC Chars table for the 71V321/71V421L35 speed grade and the Data Retention Chars table, I Temp values have been added to each table respectively. In addition, all of the AC Chars tables and the ordering information also now reflect this I temp correction Page 2 Removed IDT in reference to fabrication Page 2 & 14 The package codes J52-1, PN64-1 & PP64-1 changed to J52, PN64 & PP64 respectively to match standard package codes Page 14 Added Tape and Reel indicator to Ordering Information Page 1 -15 Removed 71V421S/L from the part number, in the pin configurations and throughout the datasheet Page 1 - 15 Removed all references to Master/Slave throughout the datasheet Page 1 -15 Updated the Com'l and Ind speeds for the 25/35/55ns offerings in Features , in the DC & AC Chars tables, in the Ordering Information and throughout the datasheet Page 13 Removed Width Expansion with Busy Logic Master/Slave Arrays diagram for part numbers 71V321/71V421S/ L and updated with a Depth Expansion diagram for the single part number 71V321S/L Updated the corresponding Depth Expansion descriptive text in the Depth Expansion section of the datasheet Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018 Page 2 Updated package codes J52 to PLG52, PP64 to PPG64 and PN64 to PNG64 Page 14 Added Orderable Part Information table CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 15 6.42 for Tech Support: 408-284-2794 DualPortHelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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