71V3577S
71V3579S
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Features
◆
◆
◆
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
128K x 36, 256K x 18 memory configurations
Supports fast access times:
Commercial:
– 6.5ns up to 133MHz clock frequency (TQFP package only)
Commercial and Industrial:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
LBO input selects interleaved or linear burst mode
◆
◆
◆
◆
◆
Functional Block Diagram
LBO
ADV
CLK
2
Binary
Counter
ADSC
Burst
Logic
Q0
CLR
ADSP
Q1
CLK EN
ADDRESS
REGISTER
A0 - A16/17
GW
BWE
INTERNAL
ADDRESS
Burst
Sequence
CEN
17/18
A0*
A1*
128K x 36/
256K x 18BIT
MEMORY
ARRAY
2
A0,A1
A2 - A17
36/18
17/18
Byte 1
Write Register
36/18
Byte 1
Write Driver
BW1
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
9
Byte 3
Write Register
Byte 3
Write Driver
BW3
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
9
CE
CS0
CS1
D
Q
Enable
Register
DATA INPUT
REGISTER
CLK EN
ZZ
Powerdown
OE
OE
I/O0 - I/O31
I/OP1 - I/OP4
OUTPUT
BUFFER
36/18
6450 drw 01
1
Apr.26.21
,
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Description
The IDT71V3577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
Commercial and Industrial Temperature Ranges
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V3577/79 SRAMs utilize a high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm 100-pin
thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and a 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A17
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0, CS1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
Input
Asynchronous
I/O
Synchronous
BWE
(1)
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS
Ground
Supply
N/A
6450tbl 01
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V3579.
6.42
2
Apr.26.21
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
ADV
Burst Address
Advance
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,
controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte
write causes all outputs to be disabled.
CE
Chip Enable
I
LOW
Synchronous chip enable. CE is used with CS0 and CS1 to enable the IDT71V3577/79. CE also gates ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect to this input.
CS0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS0 is used with CE and CS1 to enable the chip.
CS1
Chip Select 1
I
LOW
Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip.
GW
Global Write
Enable
I
LOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of
CLK. The data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
ZZ
Sleep Mode
I
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3577/79 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.
VDD
Power Supply
N/A
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
N/A
3.3V I/O Supply.
VSS
Ground
N/A
N/A
Ground.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the device.
6450 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
3
Apr.26.21
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Absolute Maximum Ratings(1)
Symbol
(2)
Rating
Commercial &
Industrial Values
Unit
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
Operating Temperature
-0 to +70
o
Industrial
Operating Temperature
-40 to +85
o
C
Temperature
Under Bias
-55 to +125
o
C
Storage
Temperature
-55 to +125
TA
(7)
TBIAS
TSTG
o
Recommended Operating
Temperature Supply Voltage
2.0
W
IOUT
DC Output Current
50
mA
CI/O
I/O Capacitance
Commercial
0°C to +70°C
0V
3.3V±5%
3.3V±5%
Industrial
-40°C to +85°C
0V
3.3V±5%
3.3V±5%
Input Capacitance
CI/O
I/O Capacitance
Max.
Unit
3.3
3.465
V
VDDQ
I/O Supply Voltage
3.135
3.3
3.465
V
VSS
Supply Voltage
0
0
0
V
VIH
Input High Voltage - Inputs
2.0
____
VDD +0.3
VIH
Input High Voltage - I/O
2.0
____
Input Low Voltage
(2)
-0.3
____
V
(1)
VDDQ +0.3
0.8
V
V
6450 tbl 06
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
(TA = +25° C, f = 1.0mhz)
Parameter(1)
Conditions
Max.
Unit
Symbol
VIN = 3dV
5
pF
CIN
Input Capacitance
VOUT = 3dV
7
pF
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
6450 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
4
Apr.26.21
Typ.
3.135
(TA = +25° C, f = 1.0mhz)
CIN
Min.
Core Supply Voltage
165 fBGA Capacitance
Parameter(1)
Parameter
VDD
6450 tbl 07
Symbol
6450 tbl 04
119 BGA Capacitance
(TA = +25° C, f = 1.0mhz)
Input Capacitance
VDDQ
VIL
100 Pin TQFP Capacitance
CIN
VDD
Symbol
6450 tbl 03
Parameter
VSS
Recommended DC Operating
Conditions
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Symbol
Temperature(1)
C
Power Dissipation
(1)
Grade
NOTES:
1. TA is the "instant on" case temperature.
C
PT
Commercial and Industrial Temperature Ranges
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
6450 tbl 07a
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
A6
A7
CE
CS0
BW4
BW3
BW2
BW1
CS1
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
Pin Configuration – 128K x 36, PKG100(3)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
NC
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
4
78
77
5
76
6
75
7
74
73
8
9
72
71
10
11
70
12
69
13
14
71V3577
PKG100
15
16
68
67
66
65
64
17
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
51
30
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
NC
VDD
ZZ (2)
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A10
A11
A12
A13
A14
A15
A16
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
3. This text does not indicate orientation of actual part-marking.
6.42
5
Apr.26.21
6450 drw 02a
,
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
A6
A7
CE
CS0
NC
NC
BW2
BW1
CS1
VDD
VSS
Pin Configuration – 256K x 18, PKG100(3)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
2
79
3
78
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VSS(1)
VDD
NC
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
77
5
76
75
6
7
74
73
8
9
72
10
71
11
70
12
69
13
14
71V3579
PKG100
15
16
68
67
66
65
64
17
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
51
30
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
NC
VDD
ZZ(2)
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
LBO
A5
A4
A3
A2
A1
A0
NC
NC
VSS
VDD
NC
NC
A11
A12
A13
A14
A15
A16
A17
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
3. This text does not indicate orientation of actual part-marking.
6.42
6
Apr.26.21
6450 drw 02b
,
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, BG119, BGG119(4)
1
2
3
4
5
6
7
A
VDDQ
A6
A4
ADSP
A8
A16
VDDQ
B
NC
CS0
A3
ADSC
A9
CS1
NC
C
NC
A7
A2
VDD
A12
A15
NC
D
I/O16
I/OP3
VSS
NC
VSS
I/OP2
I/O15
E
I/O17
I/O18
VSS
CE
VSS
I/O13
I/O14
F
VDDQ
I/O19
VSS
OE
VSS
I/O12
VDDQ
G
I/O20
I/O21
BW3
ADV
BW2
I/O11
I/O10
H
I/O22
I/O23
VSS
GW
VSS
I/O9
I/O8
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
I/O24
I/O26
VSS
CLK
VSS
I/O6
I/O7
L
I/O25
I/O27
BW4
NC
BW1
I/O4
I/O5
M
VDDQ
I/O28
VSS
BWE
VSS
I/O3
VDDQ
N
I/O29
I/O30
VSS
A1
VSS
I/O2
I/O1
P
I/O31
I/OP4
VSS
A0
VSS
I/OP1
I/O0
R
NC
A5
LBO
VDD
VSS
A13
NC
T
NC
NC
A10
A11
A14
NC
ZZ(3)
NC(2)
NC(2)
U
VDDQ
NC(2)
NC(2)
NC(2)
VDDQ
6450 drw 02c
Top View
Pin Configuration – 256K x 18, BG119, BGG119(4)
1
2
3
4
5
6
7
A
VDDQ
A6
A4
ADSP
A8
A16
VDDQ
B
NC
CS0
A3
ADSC
A9
CS1
NC
C
NC
A7
A2
VDD
A13
A17
NC
D
I/O8
NC
VSS
NC
VSS
I/OP1
NC
E
NC
I/O9
VSS
CE
VSS
NC
I/O7
F
VDDQ
NC
VSS
OE
VSS
I/O6
VDDQ
G
NC
I/O10
BW2
ADV
VSS
NC
I/O5
H
I/O11
NC
VSS
GW
VSS
I/O4
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
I/O12
VSS
CLK
VSS
NC
I/O3
L
I/O13
NC
VSS
NC
BW1
I/O2
NC
M
VDDQ
I/O14
VSS
BWE
VSS
NC
VDDQ
N
I/O15
NC
VSS
A1
VSS
I/O1
NC
P
NC
I/OP2
VSS
A0
VSS
NC
I/O0
R
NC
A5
LBO
VDD
VSS
A12
NC
T
NC
A10
A15
NC
A14
A11
ZZ(3)
VDDQ
NC(2)
NC(2)
NC(2)
NC(2)
NC(2)
U
Top View
VDDQ
6450 drw 02d
,
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. This does not indicate orientation of actual part-marking.
6.42
7
Apr.26.21
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36, BQ165, BQG165(5)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A7
CE1
BW3
BW2
CS1
BWE
ADSC
ADV
A8
NC
B
NC
A6
CS0
BW4
BW1
CLK
GW
OE
ADSP
A9
NC
C
I/OP3
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP2
D
I/O17
I/O16
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O15
I/O14
E
I/O19
I/O18
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O13
I/O12
F
I/O21
I/O20
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O11
I/O10
G
I/O23
I/O22
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O9
I/O8
H
VSS(1)
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ(3)
J
I/O25
I/O24
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O7
I/O6
K
I/O27
I/O26
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O5
I/O4
L
I/O29
I/O28
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
I/O2
M
I/O31
I/O30
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
I/O0
N
I/OP4
NC
VDDQ
VSS
NC
P
NC
NC
A5
R
LBO
NC
A4
NC
NC
VSS
VDDQ
NC
I/OP1
A2
(2)
NC
A1
(2)
NC
A10
A13
A14
NC
A3
NC(2)
A0
NC(2)
A11
A12
A15
A16
(2)
6450 tbl 17
Pin Configuration – 256K x 18, BQ165, BQG165(5)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A7
CE1
BW2
NC
CS1
BWE
ADSC
ADV
A8
A10
B
NC
A6
CS0
NC
BW1
CLK
GW
OE
ADSP
A9
NC
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP1
D
NC
I/O8
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O7
E
NC
I/O9
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O6
F
NC
I/O10
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O5
G
NC
I/O11
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O4
H
VSS(1)
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ(3)
J
I/O12
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
NC
K
I/O13
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O2
NC
L
I/O14
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
NC
M
I/O15
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O0
NC
N
I/OP2
NC
VDDQ
VSS
NC(2)
NC
NC
VSS
VDDQ
NC
NC
P
NC
NC
A5
A2
NC(2)
A1
NC(2)
A11
A14
A15
NC
LBO
NC
A4
A3
NC
A0
NC
A12
A13
A16
A17
R
(2)
(2)
6450 tbl 17a
NOTES:
1. H1 does not have to be directly VSS as long as input voltage is < VIL
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. This text does not indicate orientation of actual part-marking.
6.42
8
Apr.26.21
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
5
µA
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to V DD
___
|ILI|
ZZ , LBO and JTAG Input Leakage Current(1)
VDD = Max., VIN = 0V to V DD
___
30
µA
|ILO|
Output Leakage Current
VOUT = 0V to V DDQ, Device Deselected
___
5
µA
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
6450 tbl 08
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ in will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
6.5ns
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Com'l Only
Com'l
Ind
Com'l
Ind
Com'l
Ind
Unit
Device Selected, Outputs Open, V DD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
300
255
265
200
210
180
190
mA
IDD
Operating Power Supply Current
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, V DD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
30
30
35
30
35
30
35
mA
Clock Running Power
Supply Current
Device Deselected, Outputs Open, V DD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX (2,.3)
110
90
100
85
95
80
90
mA
Full Sleep Mode Supply Current
ZZ > VHD, VDD = Max.
30
30
35
30
35
30
35
mA
ISB2
IZZ
6450 tbl 09a
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
(VDDQ = 3.3V)
Input Pulse Levels
50Ω
0 to 3V
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
AC Test Load
VDDQ/2
I/O
,
Z0 = 50Ω
6450 drw 03
Figure 1. AC Test Load
6
See Figure 1
6450 tbl 10
5
4
ΔtCD 3
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
6450 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
9
Apr.26.21
,
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1,3)
Address
Used
CE
CS0
CS1
ADSP
ADSC
ADV
GW
BWE
BWx
OE(2)
CLK
I/O
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
X
H
L
X
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
L
X
L
X
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
X
H
X
L
X
X
X
X
X
↑
HI-Z
Deselected Cycle, Power Down
None
L
L
X
X
L
X
X
X
X
X
↑
HI-Z
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
L
X
X
X
X
X
H
↑
HI-Z
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
H
X
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
L
↑
DOUT
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
H
H
↑
HI-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L
X
↑
DIN
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
X
X
↑
DIN
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
X
H
↑
HI-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
X
H
H
↑
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
X
H
↑
HI-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
L
↑
DOUT
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
X
H
H
↑
HI-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
X
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L
X
↑
DIN
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
X
X
↑
DIN
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
X
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
X
H
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
X
H
↑
HI-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
L
↑
DOUT
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
X
H
H
↑
HI-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
X
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L
X
↑
DIN
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
X
X
↑
DIN
Operation
6450 tbl 11
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
6.42
10
Apr.26.21
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table (1, 2)
Operation
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1(3)
H
L
L
H
H
H
Write Byte 2(3)
H
L
H
L
H
H
Write Byte 3(3)
H
L
H
H
L
H
Write Byte 4(3)
H
L
H
H
H
L
6450 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V3579.
3. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table (1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
6450 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
1
0
0
1
0
0
6450 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
0
0
0
1
1
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
6.42
11
Apr.26.21
6450 tbl 15
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
6.5ns(5)
Symbol
Parameter
Min.
7.5ns
8ns
Max. Min. Max. Min.
8.5ns
Max. Min. Max.
Unit
Clock Parameter
tCYC
Clock Cycle Time
7.5
____
8.5
____
10
____
11.5
____
ns
(1)
tCH
Clock High Pulse Width
2.5
____
3
____
4
____
4.5
____
ns
tCL(1)
Clock Low Pulse Width
2.5
____
3
____
4
____
4.5
____
ns
____
6.5
____
7.5
____
8
____
8.5
ns
2
____
2
____
2
____
ns
Output Parameters
tCD
Clock High to Valid Data
tCDC
Clock High to Data Change
2
____
tCLZ(2)
Clock High to Output Active
0
____
0
____
0
____
0
____
ns
tCHZ(2)
Clock High to Data High-Z
2
3.5
2
3.5
2
3.5
2
3.5
ns
tOE
Output Enable Access Time
____
3.5
____
3.5
____
3.5
____
3.5
ns
tOLZ(2)
Output Enable Low to Output Active
0
____
0
____
0
____
0
____
ns
tOHZ(2)
Output Enable High to Output High-Z
____
3.5
____
3.5
____
3.5
____
3.5
ns
Set Up Times
tSA
Address Setup Time
1.5
____
1.5
____
2
____
2
____
ns
tSS
Address Status Setup Time
1.5
____
1.5
____
2
____
2
____
ns
tSD
Data In Setup Time
1.5
____
1.5
____
2
____
2
____
ns
tSW
Write Setup Time
1.5
____
1.5
____
2
____
2
____
ns
tSAV
Address Advance Setup Time
1.5
____
1.5
____
2
____
2
____
ns
tSC
Chip Enable/Select Setup Time
1.5
____
1.5
____
2
____
2
____
ns
Hold Times
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHS
Address Status Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHW
Write Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHAV
Address Advance Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
tZZPW
ZZ Pulse Width
100
____
100
____
100
____
100
____
ns
tZZR
ZZ Recovery Time
100
____
100
____
100
____
100
____
ns
Configuration Set-up Time
30
____
34
____
40
____
50
____
(3)
tCFG
(4)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. 6.5ns speed only available in TQFP package and in commercial temp range.
6.42
12
Apr.26.21
ns
6450 tbl 16
Apr.26.21
6.42
13
Output
Disabled
tSC
tSA
tSS
tHS
tOLZ
tOE
O1(Ax)
tHC
tHA
Flow-through
Read
Ax
tOHZ
Ay
(1)
tCH
tCD
tSAV
tHAV
O1(Ay)
tCDC
tSW
tCL
O3(Ay)
O4(Ay)
(Burst wraps around
to its initial state)
ADV HIGH suspends burst
Burst Flow-through Read
O2(Ay)
tHW
O1(Ay)
tCHZ
O2(Ay)
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
OE
ADV
(Note 3)
CE, CS1
GW, BWE, BWx
ADDRESS
ADSC
ADSP
CLK
tCYC
6450 drw 06
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Flow-Through Read Cycle (1,2)
,
Apr.26.21
6.42
14
Ax
(2)
Single Read
tSA
tHA
tSS
tHS
tCLZ
tCD
tOE
O1(Ax)
tOHZ
tSW
Ay
tCH
Write
I1(Ay)
tSD tHD
tCL
tHW
Az
tCD
tOLZ
O2(Az)
O3(Az)
Flow-through Burst Read
O1(Az)
tCDC
6450 drw 07
O4(Az)
,
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
DATAOUT
DATAIN
OE
ADV
GW
ADDRESS
ADSP
CLK
tCYC
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
Apr.26.21
6.42
15
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tHC
Ax
O4(Aw)
(1)
Ay
tCL
tOHZ
I1(Ax)
I1(Ay)
I2(Ay)
(ADV suspends burst)
tSAV
GW is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
tCH
I2(Ay)
(2)
I3(Ay)
tHAV
I4(Ay)
tSD
I1(Az)
tHW
tSW
Az
I2(Az)
tHD
6450 drw 08
I3(Az)
,
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
O3(Aw)
tSC
tSA
tHA
tSS
tHS
tCYC
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 - GW Controlled (1,2,3)
Apr.26.21
6.42
16
tHC
Burst
Read
O3(Aw)
tSC
tSA
tHA
tSS
tHS
O4(Aw)
Ax
Ay
tCL
Single
Write
tOHZ
I1(Ax)
I1(Ay)
Burst Write
I2(Ay)
(ADV HIGH suspends burst)
I2(Ay)
BWx is ignored when ADSP initiates a cycle and is sampled on the next clock rising edge
BWE is ignored when ADSP initiates a cycle and is sampled on the next cycle rising edge
tCH
I3(Ay)
I4(Ay)
tSD
Extended
Burst Write
I1(Az)
tSAV
tHW
tSW
tHW
tSW
Az
I2(Az)
tHD
6450 drw 09
I3(Az)
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
DATAOUT
DATAIN
OE
ADV
(Note 3)
CE, CS1
BWx
BWE
ADDRESS
ADSC
ADSP
CLK
tCYC
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled (1,2,3)
Apr.26.21
6.42
17
tSS
tSC
tSA
tHS
tOLZ
tOE
Ax
Single Read
O1(Ax)
tHC
tHA
tCH
tCL
tZZPW
Snooze Mode
NOTES:
1. Device must power up in deselected Mode.
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW
ZZ
DATAOUT
OE
ADV
(Note 4)
CE, CS1
GW
ADDRESS
ADSC
ADSP
CLK
tCYC
on this waveform, CS0 is HIGH.
tZZR
Az
6450 drw 13
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
,
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
DATAOUT
(Aw)
(Ax)
(Ay)
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
6450 drw 10
,
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
ADDRESS
Av
Aw
Ax
Ay
Az
(Ax)
(Ay)
(Az)
GW
CE, CS1
CS0
DATAIN
(Av)
(Aw)
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
18
Apr.26.21
6450 drw 11
,
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Ordering Information
XXX
S
X
XX
Device
Type
Power
Speed
Package
X
X
X
Process/
Temperature
Range
Blank
8
Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
PF
BG
BQ
100-pin Plastic Thin Quad Flatpack (PKG100)
119 Ball Grid Array (BG119, BGG119)
165 Fine Pitch Ball Grid Array (BQ165, BQG119)
65*
75
80
85
Access Time in Tenths of Nanoseconds
S
Standard Power
71V3577
71V3579
128K x 36 Flow-Through Burst Synchronous SRAM with 3.3V I/O
256K x 18 Flow-Through Burst Synchronous SRAM with 3.3V I/O
6450 drw 12
*6.5ns speed only available in TQFP package and commercial temp range
NOTES:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
Orderable Part Information
Speed
(ns)
65
75
80
85
Pkg.
Code
Pkg.
Type
Temp.
Grade
71V3579S65PFG
PKG100
TQFP
C
71V3579S65PFG8
PKG100
TQFP
C
Orderable Part ID
71V3579S75PFG
PKG100
TQFP
C
71V3579S75PFG8
PKG100
TQFP
C
71V3579S75PFGI
PKG100
TQFP
I
71V3579S75PFGI8
PKG100
TQFP
I
71V3579S80PFG
PKG100
TQFP
C
71V3579S80PFG8
PKG100
TQFP
C
71V3579S80PFGI
PKG100
TQFP
I
71V3579S80PFGI8
PKG100
TQFP
I
71V3579S85PFG
PKG100
TQFP
C
71V3579S85PFG8
PKG100
TQFP
C
71V3579S85PFGI
PKG100
TQFP
I
71V3579S85PFGI8
PKG100
TQFP
I
6.42
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Apr.26.21
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Orderable Part Information (con't)
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
71V3577S65PFG
PKG100
TQFP
C
80
71V3577S65PFG8
PKG100
TQFP
C
Speed
(ns)
65
75
Orderable Part ID
71V3577S75BG
BG119
PBGA
C
71V3577S75BG8
BG119
PBGA
C
71V3577S75BGG
BGG119
PBGA
C
71V3577S75BGG8
BGG119
PBGA
C
71V3577S75BGGI
BGG119
PBGA
I
71V3577S75BGGI8
BGG119
PBGA
I
71V3577S75BGI
BG119
PBGA
I
71V3577S75BGI8
BG119
PBGA
I
71V3577S75BQ
BQ165
CABGA
71V3577S75BQ8
BQ165
71V3577S75BQG
Pkg.
Code
Pkg.
Type
Temp.
Grade
BG119
PBGA
C
71V3577S80BG8
BG119
PBGA
C
71V3577S80BGG
BGG119
PBGA
C
71V3577S80BGG8
BGG119
PBGA
C
71V3577S80BGGI
BGG119
PBGA
I
71V3577S80BGGI8
Orderable Part ID
71V3577S80BG
BGG119
PBGA
I
71V3577S80BGI
BG119
PBGA
I
71V3577S80BGI8
BG119
PBGA
I
71V3577S80BQ
BQ165
CABGA
C
71V3577S80BQ8
BQ165
CABGA
C
71V3577S80BQI
BQ165
CABGA
I
C
71V3577S80BQI8
BQ165
CABGA
I
CABGA
C
71V3577S80PFG
PKG100
TQFP
C
BQ165
CABGA
C
71V3577S80PFG8
PKG100
TQFP
C
71V3577S75BQG8
BQ165
CABGA
C
71V3577S80PFGI
PKG100
TQFP
I
71V3577S75BQI
BQ165
CABGA
I
71V3577S80PFGI8
PKG100
TQFP
I
71V3577S75BQI8
BQ165
CABGA
I
71V3577S85BG
BG119
PBGA
C
71V3577S85BG8
BG119
PBGA
C
71V3577S85BGG
BGG119
PBGA
C
71V3577S85BGG8
BGG119
PBGA
C
71V3577S75PFG
PKG100
TQFP
C
71V3577S75PFG8
PKG100
TQFP
C
71V3577S75PFGI
PKG100
TQFP
I
71V3577S75PFGI8
PKG100
TQFP
I
85
71V3577S85BGI
BG119
PBGA
I
71V3577S85BGI8
BG119
PBGA
I
71V3577S85BQ
BQ165
CABGA
C
71V3577S85BQ8
BQ165
CABGA
C
71V3577S85BQG
BQG165
CABGA
C
71V3577S85BQG8
BQG165
CABGA
C
BQ165
CABGA
I
71V3577S85BQI8
BQ165
CABGA
I
71V3577S85PFG
PKG100
TQFP
C
71V3577S85PFG8
PKG100
TQFP
C
71V3577S85PFGI
PKG100
TQFP
I
71V3577S85PFGI8
PKG100
TQFP
I
71V3577S85BQI
6.42
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Apr.26.21
71V3577S_79S, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Datasheet Document History
01/30/04
04/17/06
04/02/12
04/26/21
Released Y generation die step datasheet
Added green (Restricted hazardous substance device) to the datasheet.
Added Industrial temp range values to the 7.5ns speed in the DC chars table
Removed die step indicator from the ordering information.
Added tape and reel and green to the ordering information.
Removed IDT from the ordering information.
Pg. 1, 12 & 21 Added 6.5ns speed only available in TQFP package and in commercial temp range.
Pg. 1 - 22
Rebranded as Renesas datasheet
Pg. 1 - 21
Removed all JTAG references in the datasheet
Pg. 5 - 8
Updated package codes and removed future options for BQ165, BQG165 pin configurations
Pg. 19 & 20
Added Orderable Part Information tables
Pg. 21
Pg. 9
Pg. 21
6.42
21
Apr.26.21
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