71V416S12BEI

71V416S 71V416L 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Description 256K x 16 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle times – Commercial and Industrial: 10/12/15ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 3.3V power supply Available in 44-pin, 400 mil plastic SOJ package and a 44pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. Green parts available, see ordering information The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized as 256K x 16. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V416 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. Functional Block Diagram OE Output Enable Buffer A0 - A17 Address Buffers Row / Column Decoders 8 CS Chip Select Buffer 8 4,194,304-bit Memory Array WE 16 Write Enable Buffer Sense Amps and Write Drivers 8 8 High Byte Output Buffer High Byte Write Buffer Low Byte Output Buffer Low Byte Write Buffer 8 I/O 15 8 I/O 8 8 8 I/O 7 I/O 0 BHE Byte Enable Buffers BLE 3624 drw 01 1 May.26.21 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configurations - SOJ/TSOP A0 A1 A2 A3 A4 CS I/O0 I/O1 I/O2 I/O3 VDD VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 44 43 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PHG44 or PBG44 44-Pin TSOP SOJ TopView 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Pin Configurations - BGA(1) (2) A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VDD I/O11 I/O10 I/O9 I/O8 NC(1) A14 BE48, BEG48 A13 A12 A11 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC B I/O0 BHE A3 A4 CS I/O8 C I/O1 I/O2 A5 A6 I/O10 I/O9 D VSS I/O3 A 17 A7 I/O11 VDD E VDD I/O4 NC A16 I/O12 VSS F I/O6 I/O5 A 14 A15 I/O13 I/O14 G I/O7 NC A12 A13 WE I/O15 H NC A8 A9 A10 A11 NC 3624 tbl 11 A10 Top View NOTE: 1. This text does not indicate orientation of actual part-marking. 3624 drw 02 NOTES: 1. Pin 28 can either be a NC or connected to Vss. 2. This text does not indicate orientation of actual part-marking. SOJ Capacitance (TA = +25°C, f = 1.0MHz) Pin Descriptions Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 3dV 7 pF CI/O I/O Capacitance VOUT = 3dV 8 A0 - A17 Address Inputs Input CS Chip Select Input WE Write Enable Input OE Output Enable Input BGA Capacitance BHE High Byte Enable Input (TA = +25°C, f = 1.0MHz) BLE Low Byte Enable Input Symbol Parameter(1) Conditions Max. Unit I/O0 - I/O15 Data Input/Output I/O CIN Input Capacitance VIN = 3dV 6 pF VDD 3.3V Power Pwr CI/O I/O Capacitance VOUT = 3dV 7 VSS Ground Gnd pF NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 3624 tbl 02b 3624 tbl 01 6.42 2 May.26.21 pF 3624 tbl 02 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Value Unit VDD Supply Voltage Relative to VSS -0.5 to +4.6 V -0.5 to VDD+0.5 V VIN, VOUT Terminal Voltage Relative to VSS TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o PT Power Dissipation 1 IOUT DC Output Current 50 C C Recommended Operating Temperature and Supply Voltage Grade Temperature VSS VDD Commercial 0OC to +70OC 0V See Below –40 C to +85 C 0V See Below Industrial O O 3624 tbl 05 W mA 3624 tbl 04 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V V VDD Supply Voltage VSS Ground VIH Input High Voltage 2.0 ____ VDD+0.3(1) VIL Input Low Voltage -0.3(2) ____ 0.8 V 3624 tbl 06 NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. Truth Table(1) CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 Function H X X X X High-Z High-Z Deselected - Standby L L H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATAOUT High Byte Read L L H L L DATAOUT DATAOUT Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled 3624 tbl 03 NOTE: 1. H = VIH, L = VIL, X = Don't care. 6.42 3 May.26.21 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) IDT71V416 Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = VSS to VDD ___ 5 µA |ILO| Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD ___ 5 µA VOL Output Low Voltage IOL = 8mA, VDD = Min. ___ 0.4 V VOH Output High Voltage IOH = -4mA, VDD = Min. 2.4 ___ V 3624 tbl 07 DC Electrical Characteristics(1, 2, 3) (VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V) 71V416S/L10 Symbol ICC ISB ISB1 Parameter 71V416S/L12 71V416S/L15 Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit mA Dynamic Operating Current CS < V LC, Outputs Open, V DD = Max., f = fMAX(4) S 200 200 180 180 170 170 L 180 180 170 170 160 160 Dynamic Standby Power Supply Current CS > V HC, Outputs Open, V DD = Max., f = fMAX(4) S 70 70 60 60 50 50 L 50 50 45 45 40 40 Full Standby Power Supply Current (static) CS > V HC, Outputs Open, V DD = Max., f = 0(4) S 20 20 20 20 20 20 L 10 10 10 10 10 10 mA 3624 tbl 08 NOTES: IDT71V416S/71V416L 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD -0.2V (High). 3. Power specifications are preliminary. 4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. AC Test Loads 3.3V +1.5V 320Ω 50Ω I/O mA DATA OUT Z0 = 50Ω 5pF* 30pF 350Ω 3624 drw 03 3624 drw 04 Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 7 • 6 ΔtAA, tACS (Typical, ns) 5 4 AC Test Conditions Input Pulse Levels • 3 • 2 • 1 • • • 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) 1.5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Figures 1,2 and 3 3624 tbl 09 Figure 3. Output Capacitive Derating 6.42 4 May.26.21 Input Rise/Fall Times AC Test Load 3624 drw 05 GND to 3.0V 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) 71V416S/L10 Symbol Parameter 71V416S/L12 71V416S/L15 Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ns 4 ____ 4 ____ ns 6 ____ 7 ns (1) Chip Select Low to Output in Low-Z 4 ____ (1) Chip Select High to Output in High-Z ____ 5 ____ tOE Output Enable Low to Output Valid ____ 5 ____ 6 ____ 7 ns tOLZ(1) Output Enable Low to Output in Low-Z 0 ____ 0 ____ 0 ____ ns ____ 5 ____ 6 ____ 7 ns 4 ____ 4 ____ 4 ____ ns ____ 5 ____ 6 ____ 7 ns 0 ____ 0 ____ 0 ____ ns tCLZ tCHZ tOHZ (1) Output Enable High to Output in High-Z tOH Output Hold from Address Change tBE Byte Enable Low to Output Valid (1) Byte Enable Low to Output in Low-Z (1) Byte Enable High to Output in High-Z ____ 5 ____ 6 ____ 7 ns tWC Write Cycle Time 10 ____ 12 ____ 15 ____ ns tAW Address Valid to End of Write 8 ____ 8 ____ 10 ____ ns tCW Chip Select Low to End of Write 8 ____ 8 ____ 10 ____ ns tBW Byte Enable Low to End of Write 8 ____ 8 ____ 10 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ ns tWR Address Hold from End of Write 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 8 ____ 8 ____ 10 ____ ns tDW Data Valid to End of Write 5 ____ 6 ____ 7 ____ ns tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tOW(1) Write Enable High to Output in Low-Z 3 ____ 3 ____ 3 ____ ns Write Enable Low to Output in High-Z ____ 6 ____ 7 ____ 7 ns tBLZ tBHZ WRITE CYCLE tWHZ (1) 3624 tbl 10 NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. Timing Waveform of Read Cycle No. 1(1,2,3) tRC ADDRESS tAA tOH tOH DATAOUT DATAOUT VALID PREVIOUS DATAOUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 3624 drw 06 6.42 5 May.26.21 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2 (1) tRC ADDRESS tOH tAA OE tOHZ (3) tOE tOLZ CS tCLZ (3) (3) tACS (2) tCHZ (3) BHE, BLE tBE tBLZ (2) tBHZ (3) (3) DATAOUT DATA OUT VALID 3624 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured ±200mV from steady state. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tCW (2) tCHZ (5) tBW BHE, BLE tWR WE tAS tWHZ (5) (5) tOW DATAOUT tBHZ tWP PREVIOUS DATA VALID (3) (5) DATA VALID tDW DATAIN tDH DATAIN VALID 3624 drw 08 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 6 May.26.21 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3) tWC ADDRESS tAW CS tCW (2) tAS tBW BHE, BLE tWP tWR WE DATAOUT tDH tDW DATAIN DATAIN VALID 3624 drw 09 Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,3) tWC ADDRESS tAW CS tCW (2) tAS tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 3624 drw 10 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. During this period, I/O pins are in the output state, and input signals must not be applied. 3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6.42 7 May.26.21 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Ordering Information X 71V416 X XX XXX Device Type Power Speed Package X X Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank Commercial (0°C to +70°C) Industrial (-40°C to +85°C) I G Green Y PH BE 44-pin, 400-mil SOJ (PBG44) 44-pin TSOP Type II (PHG44) 48 Ball Grid Array (BE48, BEG48) 10 12 15 Speed in nanoseconds S L Standard Power Low Power Orderable Part Information Speed Orderable Part ID (ns) 10 12 71V416L10BE 3624 drw 11a Pkg. Code Pkg. Type Temp. Grade Speed Orderable Part ID (ns) Pkg. Code Pkg. Type Temp. Grade BE48 CABGA C C BE48 CABGA C 71V416L10BEG BEG48 CABGA C 71V416S10BE8 BE48 CABGA 71V416L10BEG8 BEG48 CABGA C 71V416S10BEG BEG48 CABGA C 71V416L10PHG PHG44 TSOP C 71V416S10BEG8 BEG48 CABGA C 71V416L10PHG8 PHG44 TSOP C 71V416L10PHGI PHG44 TSOP I 71V416L10PHGI8 PHG44 TSOP I 71V416L10YG PBG44 SOJ C 71V416L10YG8 PBG44 SOJ C 71V416L12BE BE48 CABGA C 71V416L12BE8 BE48 CABGA C 71V416L12BEG BEG48 CABGA C 71V416L12BEG8 BEG48 CABGA C 71V416L12BEGI BEG48 CABGA I 71V416L12BEGI8 71V416L12BEI 10 12 71V416S10BE 71V416S10PHG PHG44 TSOP C 71V416S10PHG8 PHG44 TSOP C 71V416S10PHGI PHG44 TSOP I 71V416S10PHGI8 PHG44 TSOP I 71V416S10YG PBG44 SOJ C 71V416S10YG8 PBG44 SOJ C 71V416S12BE BE48 CABGA C 71V416S12BE8 BE48 CABGA C 71V416S12BEG BEG48 CABGA C BEG48 CABGA C BEG48 CABGA I 71V416S12BEG8 BE48 CABGA I 71V416S12BEI BE48 CABGA I BE48 CABGA I 71V416L12BEI8 BE48 CABGA I 71V416S12BEI8 71V416L12PHG PHG44 TSOP C 71V416S12PHG PHG44 TSOP C 71V416L12PHG8 PHG44 TSOP C 71V416S12PHG8 PHG44 TSOP C 71V416L12PHGI PHG44 TSOP I 71V416S12PHGI PHG44 TSOP I 71V416L12PHGI8 PHG44 TSOP I 71V416S12PHGI8 PHG44 TSOP I 71V416L12YG PBG44 SOJ C 71V416S12YG PBG44 SOJ C 71V416L12YG8 PBG44 SOJ C 71V416S12YG8 PBG44 SOJ C 71V416L12YGI PBG44 SOJ I 71V416S12YGI PBG44 SOJ I 71V416L12YGI8 PBG44 SOJ I 71V416S12YGI8 PBG44 SOJ I 3624 tbl 12a 3624 tbl 12b 6.42 8 May.26.21 71V416S, 71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Orderable Part Information (con't) Speed Orderable Part ID (ns) 15 71V416L15BE 71V416L15BE8 Pkg. Code Pkg. Type Temp. Grade BE48 CABGA C BE48 71V416L15BEG BEG48 CABGA Speed Orderable Part ID (ns) 15 C CABGA C Pkg. Code Pkg. Type Temp. Grade 71V416S15BE BE48 CABGA C 71V416S15BE8 BE48 CABGA C 71V416S15BEG BEG48 CABGA C 71V416S15BEG8 BEG48 CABGA C 71V416L15BEG8 BEG48 CABGA C 71V416L15BEGI BEG48 CABGA I 71V416L15BEGI8 BEG48 CABGA I 71V416S15BEI BE48 CABGA I 71V416L15BEI BE48 CABGA I 71V416S15BEI8 BE48 CABGA I 71V416L15BEI8 BE48 CABGA I 71V416S15PHG PHG44 TSOP C 71V416L15PHG PHG44 TSOP C 71V416S15PHG8 PHG44 TSOP C 71V416L15PHG8 PHG44 TSOP C 71V416S15PHGI PHG44 TSOP I PHG44 TSOP I 71V416S15BEGI BEG48 CABGA I 71V416S15BEGI8 BEG48 CABGA I 71V416L15PHGI PHG44 TSOP I 71V416S15PHGI8 71V416L15PHGI8 PHG44 TSOP I 71V416S15YG PBG44 SOJ C 71V416S15YG8 PBG44 SOJ C 71V416S15YGI PBG44 SOJ I 71V416S15YGI8 PBG44 SOJ 71V416L15YGI PBG44 SOJ I 71V416L15YGI8 PBG44 SOJ I I 3624 tbl 12c 3624 tbl 12d Datasheet Document History 08/05/99: 08/31/99: 03/24/00: 08/10/00: 09/11/ 02: 11/26/02: 07/31/03: 10/13/03: 01/30/04: 02/01/13: 11/18/16: 05/26/21: Pg 6 Pg. 1–9 Pg. 9 Pg. 6 Pg. 1 Pg. 2 Pg. 8 Pg. 8 Pg. 8 Pg. 8 Pg. 1 Pg. 8 Pg. 2 Pg.4 Pg. 5 Pg. 8 Pg. 8-9 Pg. 1 - 10 Pg. 2 & 8 Updated to new format Revised footnote for tCW on Write Cycle No. 1 diagram Added Industrial temperature range offering Added Datasheet Document History Changed note to Write cycle No. 1 according to footnotes Add 48 ball grid array package offering Correct TTL to LVTTL Updated TBD information for the 48 BGA Capacitance table Added "Die Revision" to ordering information Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y. Updated ordering information. Refer to 71V416YS and 71V416YL datasheet for latest generation die step. Added "Restricted hazardous substance device" to ordering information Removed IDT reference to fabrication Removed die revision information from the Ordering Information Updated the orderable part numbers for all pin configurations Added the corrected configuration title for the 48 BGA pin configuration Reformatted SOJ/TSOP pins & labels. No change in functionality. It remains the same Updated the Industrial values and the footnote references in the DC Electrical table Updated the footnote references in the AC Electrical table Updated the orderable part numbers in the Ordering Information Added orderable part information tables Rebranded as Renesas datasheet Updated package codes 6.42 9 May.26.21 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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