128K x 36, 3.3V Synchronous
IDT71V546S
™ Feature
SRAM with ZBT™
Burst Counter and Pipelined Outputs
Features
◆
◆
◆
◆
◆
128K x 36 memory configuration, pipelined outputs
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized registered outputs eliminate the
need to control OE
Single R/W (READ/WRITE) control pin
◆
◆
◆
◆
◆
◆
◆
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
Packaged in a JEDEC standard 100-pin TQFP package
Green parts available, see Ordering Information
Functional Block Diagram
128K x 36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
Q
Address
D
Q
Control
CE1, CE2, CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
Q
DO
Control Logic
Clk
Mux
Sel
D
Clk
Clock
Output Register
Q
Gate
OE
3821 drw 01
.
Data I/O [0:31], I/O P[1:4]
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
AUGUST 2017
1
©2017 Integrated Device Technology, Inc.
DSC-3821/07
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Description
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not active
when ADV/LD is low, no new memory operation can be initiated and any
burst that was in progress is stopped. However, any pending data
transfers (reads or writes) will be completed. The data bus will tri-state two
cycles after the chip is deselected or a write initiated.
The IDT71V546 has an on-chip burst counter. In the burst mode, the
IDT71V546 can provide four cycles of data for a single address presented
to the SRAM. The order of the burst sequence is defined by the LBO input
pin. The LBO pin selects between linear and interleaved burst sequence.
The ADV/LD signal is used to load a new external address (ADV/LD =
LOW) or increment the internal burst counter (ADV/LD = HIGH).
The IDT71V546 SRAM utilizes a high-performance, high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminate dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Thus it has been given the name ZBTTM,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later its associated data cycle occurs, be it
read or write.
The IDT71V546 contains data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to
disable the outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V546 to be
suspended as long as necessary. All synchronous inputs are ignored
when CEN is high and the internal device registers will hold their previous
values.
Pin Description Summary
A0 - A16
Address Inputs
Input
Synchronous
Three Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
Individual Byte Write Selects
Input
Synchronous
Clock
Input
N/A
Advance Burst Address / Load New Address
Input
Synchronous
Linear / Interleaved Burst Order
Input
Static
I/O
Synchronous
CE1, CE2, CE2
BW1, BW2, BW3, BW4
CLK
ADV/LD
LBO
I/O0 - I/O31, I/OP1 - I/OP4
Data Input/Output
VDD
3.3V Power
Supply
Static
VSS
Ground
Supply
Static
3821 tbl 01
2
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Pin Definitions
Commercial and Industrial Temperature Ranges
(1)
Symbol
Pin Function
I/O
Active
Description
A0 - A16
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a
combination of the rising edge of CLK and ADV/LD Low, CEN Low and true
chip enables.
ADV/LD
Address/Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with
new address and control when it is sampled low at the rising edge of clock with
the chip selected. When ADV/LD is low with the chip deselected, any burst in
progress is terminated. When ADV/LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses
are ignored when ADV/LD is sampled high.
R/W
Read/Write
I
N/A
R/W signal is a synchronous input that identified whether the current load cycle
initiated is a Read or Write access to the memory array. The data bus activity for
the current cycle takes place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchrono us Clock Enable Input. When CEN is sampled high, all other
synchronous inputs, includ ing clock are ignored and outputs remain unchanged.
The effect of CEN samp led high on the device outputs is as if the low to high
clock transition did not occur. For normal operation, CEN must be sampled low
at rising edge of clock.
BW1 - BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Enable 9-bit byte has its own active low byte
write enable. On load write cycles (When R/W and ADV/LD are sampled low)
the appropriate byte write signal (BW1 - BW4) must be valid. The byte write
signal must also be valid on each cycle of a burst write. Byte Write signals are
ignored when R/W is sampled high. The appropriate byte(s) of data are written
into the device two cycles later. BW1 - BW4 can all be tied low if always doing
write to the entire 36-bit word.
CE1, CE2
Chip Enables
I
LOW
Synchro nous active low chip enable. CE1 and CE2 are used with CE2 to
enable the IDT71V546. (CE1 or CE2 sampled high or CE2 sampled low) and
ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after
deselect is initiated.
CE2
Chip Enable
I
HIGH
Synchronout active high chip enable. CE2 is used with CE1 and CE2 to enable
the chip. CE2 has inverted polarity but otherwise identical to CE1 and CE2.
CLK
Clock
I
N/A
This is the clock input to the IDT71V546. Except for OE, all timing references for
the device are made with respect to the rising edge of CLK.
I/O0 - I/O31
I/OP1 - I/OP4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data
output path are registered and triggered by the rising edge of CLK.
LBO
Linear Burst
Order
I
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is
selected. When LBO is low the Linear burst sequence is selected. LBO is a
static DC input.
OE
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V546.
When OE is high the I/O pins are in a high-impedance state. OE does not need
to be actively controlled for read and write cycles. In normal operation, OE can
be tied low.
VDD
Power Supply
N/A
N/A
3.3V power supply input.
VSS
Ground
N/A
N/A
Ground pin.
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
3
6.42
3821 tbl 02
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
52
51
55
54
53
56
58
57
59
60
61
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
I/OP3
I/O16
I/O17
VDD
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDD
I/O22
I/O23
VDD(1)
VDD
VDD
VSS
I/O24
I/O25
VDD
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDD
I/O30
I/O31
I/OP4
100 TQFP
Top Vie
w
iew
NOTE:
1. Pin 14 does not have to be connected directly to VDD as long as the input voltage is > VIH.
4
A16
A15
A14
A13
A12
A11
A10
NC
NC
VDD
VSS
NC
NC
A0
A1
A2
A3
A4
A5
LBO
30
65
64
66
68
67
70
69
72
71
73
74
76
75
77
78
63
62
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
71V546
PKG100
1
NC
NC
ADV/LD
OE
CEN
R/W
CLK
VSS
VDD
CE2
BW1
BW2
BW3
BW4
CE2
CE1
A7
A6
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
2
A9
A8
79
80
I/OP2
I/O15
I/O14
VDD
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDD
I/O9
I/O8
VSS
VDD
VDD
VSS
I/O7
I/O6
VDD
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDD
I/O1
I/O0
I/OP1
Pin Configuration — 128K X 36
3821 drw 02a
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial &
Industrial Values
Unit
Symbol
VTERM(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6
V
VTERM(3)
Terminal Voltage
with Respect to GND
-0.5 to VDD+0.5
V
Commercial
Operating Ambient
Temperature
0 to +70
Industrial
Operating Ambient
Temperature
-40 to +85
o
C
TBIAS
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-55 to +125
o
C
PT
Power Dissipation
2.0
W
IOUT
DC Output Current
50
mA
TA(4)
o
VDD(3)
C
CIN
Input Capacitance
CI/O
I/O Capacitance
Unit
VIN = 3dV
5
pF
VOUT = 3dV
7
Unit
3.135
3.3
3.465
V
0
0
0
V
Ground
VIH
Input High Voltage - Inputs
2.0
____
4.6
V
VIH
Input High Voltage - I/O
2.0
____
VDD+0.3(2)
V
____
0.8
V
(1)
Input Low Voltage
-0.5
Recommended Operating
Temperature and Supply Voltage
Grade
Ambient
Temperature(1)
VSS
VDD
Commercial
0 C to +70 C
0V
3.3V±5%
Industrial
-40 C to +85 C
0V
3.3V±5%
O
O
O
O
3821 tbl 03
NOTES:
1. During production testing, the case temperature equals the ambient temperature.
(TA = +25°C, f = 1.0MHz, TQFP package)
Max.
Max.
3821 tbl 04
100 TQFP Capacitance
Conditions
Typ.
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
3. VDD needs to be ramped up smoothly to the operating level. If there are any
glitches on VDD that cause the voltage level to drop below 2.0 volts then the
device needs to be reset by holding VDD to 0.0 volts for a minimum of 100 ms.
3821 tbl 05
Parameter(1)
Supply Voltage
Min.
VSS
VIL
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VDD and Input terminals only.
3. I/O terminals.
4. During production testing, the case temperature equals the ambient temperature.
Symbol
Parameter
pF
3821 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
5
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
CEN
R/W
Chip(5)
Enable
ADV/LD
BWx
ADDRESS
USED
PREVIOUIS CYCLE
CURRENT CYCLE
I/O
(2 cycles later)
L
L
Select
L
Valid
External
X
LOAD WRITE
D(7)
L
H
Select
L
X
External
X
LOAD READ
Q(7)
L
X
X
H
Valid
Internal
LOAD WRITE/
BURST WRITE
BURST WRITE
(Advance Burst Counter)(2)
D(7)
L
X
X
H
X
Internal
LOAD READ/
BURST READ
BURST READ
(Advance Burst Counter)(2)
Q(7)
L
X
Deselect
L
X
X
X
DESELECT or STOP(3)
HiZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HiZ
H
X
X
X
X
X
(4)
X
SUSPEND
Previous Value
3821 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propagating through the part. The state of all the internal registers and the I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if either one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
Operation
R/W
BW1
BW2
BW3
BW4
READ
H
X
X
X
X
L
L
L
L
L
L
L
H
H
H
L
H
L
H
H
WRITE BYTE 3 (I/O [16:23], I/O P3)(2)
L
H
H
L
H
(2)
L
H
H
H
L
L
H
H
H
H
WRITE ALL BYTES
(2)
WRITE BYTE 1 (I/O [0:7], I/O P1)
(2)
WRITE BYTE 2 (I/O [8:15], I/O P2)
WRITE BYTE 4 (I/O [24:31], I/O P4)
NO WRITE
3821 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
6
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
Fourth Address
(1)
Sequence 4
3821 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
Fourth Address
(1)
Sequence 4
3821 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
A29
A30
A31
A32
A33
A34
A35
A36
A37
A37
C29
C30
C31
C32
C33
C34
C35
C36
C37
C37
D/Q27
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
CLOCK
ADDRESS
(A0 - A16)
(2)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
I/O [0:31], I/O P[1:4]
NOTES:
3821 drw 03
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
7
6.42
,
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load,
Burst, Deselect and NOOP Cycles(2)
Cycle
Address
R/W
ADV/LD
CE(1)
CEN
BWx
OE
I/O
n
A0
H
L
L
L
X
X
X
Load read
n+1
X
X
H
X
L
X
X
X
Burst read
n+2
A1
H
L
L
L
X
L
Q0
Load read
n+3
X
X
L
H
L
X
L
Q0+1
Deselect or STOP
n+4
X
X
H
X
L
X
L
Q1
NOOP
n+5
A2
H
L
L
L
X
X
Z
Load read
n+6
X
X
H
X
L
X
X
Z
Burst read
n+7
X
X
L
H
L
X
L
Q2
Deselect or STOP
n+8
A3
L
L
L
L
L
L
Q2+1
Load write
n+9
X
X
H
X
L
L
X
Z
Burst write
n+10
A4
L
L
L
L
L
X
D3
Load write
n+11
X
X
L
H
L
X
X
D3+1
Deselect or STOP
n+12
X
X
H
X
L
X
X
D4
NOOP
n+13
A5
L
L
L
L
L
X
Z
Load write
n+14
A6
H
L
L
L
X
X
Z
Load read
n+15
A7
L
L
L
L
L
X
D5
Load write
n+16
X
X
H
X
L
L
L
Q6
Burst write
n+17
A8
H
L
L
L
X
X
D7
Load read
n+18
X
X
H
X
L
X
X
D7+1
Burst read
n+19
A9
L
L
L
L
L
L
Q8
Load write
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
8
Comments
3821 tbl 11
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Read Operation(1)
Cycle
Address
R/W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock Setup Valid
n+2
X
X
X
X
X
X
L
Q0
Co ntents of Address A0 Read Out
Comments
3821 tbl 12
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Read Operation(1)
Cycle
Address
R/W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
H
X
L
X
X
X
Clock Setup Valid, Advance Counter
n+2
X
X
H
X
L
X
L
Q0
Ad dress A0 Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q0+1
Address A0+1 Read Out, Inc. Count
n+4
X
X
H
X
L
X
L
Q0+2
Address A0+2 Read Out, Inc. Count
n+5
A1
H
L
L
L
X
L
Q0+3
Address A0+3 Read Out, Load A1
n+6
X
X
H
X
L
X
L
Q0
Ad dress A0 Read Out, Inc. Count
n+7
X
X
H
X
L
X
L
Q1
Ad dress A1 Read Out, Inc. Count
n+8
A2
H
L
L
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
9
6.42
Comments
3821 tbl 13
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Write Operation(1)
Cycle
Address
R/W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
X
Clock Setup Valid
n+2
X
X
X
X
L
X
X
D0
Write to Address A0
Comments
3821 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
Cycle
Address
R/W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
H
X
L
L
X
X
Clock Setup Valid, Inc. Count
n+2
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+3
X
X
H
X
L
L
X
D0+1
Address A0+1 Write, Inc. Count
n+4
X
X
H
X
L
L
X
D0+2
Address A0+2 Write, Inc. Count
n+5
A1
L
L
L
L
L
X
D0+3
Address A0+3 Write, Load A1
n+6
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+7
X
X
H
X
L
L
X
D1
Address A1 Write, Inc. Count
n+8
A2
L
L
L
L
L
X
D1+1
Address A1+1 Write, Load A2
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
10
Comments
3821 tbl 15
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Read Operation With Clock Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored
n+2
A1
H
L
L
L
X
X
X
Clock Valid
n+3
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus
n+4
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus
n+5
A2
H
L
L
L
X
L
Q0
Address A0 Read out (but trans.)
n+6
A3
H
L
L
L
X
L
Q1
Ad dress A1 Read out (bus trans.)
n+7
A4
H
L
L
L
X
L
Q2
Ad dress A2 Read out (bus trans.)
Comments
3821 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE(2)
CEN
BWx
OE
I/O
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored
n+2
A1
L
L
L
L
L
X
X
Clock Valid
n+3
X
X
X
X
H
X
X
X
Clock Ignored
n+4
X
X
X
X
H
X
X
X
Clock Ignored
n+5
A2
L
L
L
L
L
X
D0
Write data D0
n+6
A3
L
L
L
L
L
X
D1
Write data D1
n+7
A4
L
L
L
L
L
X
D2
Write data D2
Comments
3821 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
11
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Read Operation With Chip Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE(1)
CEN
BWx
OE
I/O
n
X
X
L
H
L
X
X
?
Deselected
n+1
X
X
L
H
L
X
X
?
Deselected
n+2
A0
H
L
L
L
X
X
Z
Address and Control meet setup
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP
n+4
A1
H
L
L
L
X
L
Q0
Address A0 read out. Load A1
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP
n+6
X
X
L
H
L
X
L
Q1
Address A1 Read out. Deselected
n+7
A2
H
L
L
L
X
X
Z
Address and Control meet setup
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP
n+9
X
X
L
H
L
X
L
Q2
Address A2 read out. Deselected
Comments
3821 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation With Chip Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE(1)
CEN
BWx
OE
I/O
n
X
X
L
H
L
X
X
?
Deselected
n+1
X
X
L
H
L
X
X
?
Deselected
n+2
A0
L
L
L
L
L
X
Z
Address and Control meet setup
n+3
X
X
L
H
L
X
X
Z
Deselected or STOP
n+4
A1
L
L
L
L
L
X
D0
Address D0 Write In. Load A1
n+5
X
X
L
H
L
X
X
Z
Deselected or STOP
n+6
X
X
L
H
L
X
X
D1
Address D1 Write In. Deselected
n+7
A2
L
L
L
L
L
X
Z
Address and Control meet setup
n+8
X
X
L
H
L
X
X
Z
Deselected or STOP
n+9
X
X
L
H
L
X
X
D2
Address D2 Write In. Deselected
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
12
Comments
3821 tbl 19
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
___
5
µA
|ILI|
LBO Input Leakage Current(1)
VDD = Max., VIN = 0V to VDD
___
30
µA
|ILO|
Output Leakage Current
CE > VIH or OE > VIH, VOUT = 0V toVDD, VDD = Max.
___
5
µA
VOL
Output Low Voltage
IOL = 5mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -5mA, VDD = Min.
2.4
___
V
3821 tbl 20
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application.
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range(1) (VDD = 3.3V +/-5%, VHD = VDD–0.2V, VLD = 0.2V)
S133
Symbol
Parameter
Test Conditions
S100
Com'l
Ind
Com'l
Ind
300
310
250
260
40
45
40
45
Device Deselected, Outputs Open, V DD = Max., V IN >
V HD or < V LD, f = fMAX(2)
110
120
100
110
Device Selected, Outputs Open, CEN > V IH V DD = Max.,
V IN > V HD or < V LD, f = fMAX(2)
40
45
40
45
IDD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, V DD = Max., V IN > V IH or < V IL, f = fMAX(2)
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, V DD = Max., V IN >
V HD or < V LD, f = 0(2)
ISB2
Clock Running Power
Supply Current
ISB3
Idle Power
Supply Current
Unit
mA
mA
mA
mA
3821 tbl 21
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
AC Test Loads
AC Test Conditions
+1.5V
Input Pulse Levels
50Ω
I/O
Z0 = 50Ω
3821 drw 04
,
Input Rise/Fall Times
2ns
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
AC Test Load
See Figures 1
3821 tbl 22
Figure 1. AC Test Load
6
5
4
ΔtCD 3
(Typical, ns)
2
1
20 30 50
0 to 3V
80 100
Capacitance (pF)
200
3821 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
,
13
6.42
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
71V546S133
Symbol
Parameter
71V546S100
Min.
Max.
Min.
Max.
Unit
Clock Parameters
tCYC
Clock Cycle Time
7.5
____
10
____
ns
tF(1)
Clock Frequency
____
133
____
100
MHz
(2)
Clock High Pulse Width
2.5
____
3.5
____
ns
(2)
Clock Low Pulse Width
2.5
____
3.6
____
ns
tCH
tCL
Output Parameters
tCD
Clock High to Valid Data
____
4.2
____
5
ns
tCDC
1.5
____
ns
1.5
____
ns
tCLZ
Clock High to Data Change
1.5
____
(3,4,5)
Clock High to Output Active
1.5
____
(3,4,5)
Clock High to Data High-Z
1.5
3.5
1.5
3.5
ns
Output Enable Access Time
____
4.2
____
5
ns
0
____
0
____
ns
tCHZ
tOE
(3,4)
Output Enable Low to Data Active
(3.4)
Output Enable High to Data High-Z
____
3.5
____
3.5
ns
tSE
Clock Enable Setup Time
2.0
____
2.2
____
ns
tSA
Address Setup Time
2.0
____
2.2
____
ns
tSD
Data in Setup Time
1.7
____
2.0
____
ns
tSW
Read/Write (R/W) Setup Time
2.0
____
2.2
____
ns
tSADV
Advance/Load (ADV/LD) Setup Time
2.0
____
2.2
____
ns
tSC
Chip Enable/Select Setup Time
2.0
____
2.2
____
ns
tSB
Byte Write Enable (BWx) Setup Time
2.0
____
2.2
____
ns
tHE
Clock Enable Hold Time
0.5
____
0.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
ns
tHD
Data in Hold Time
0.5
____
0.5
____
ns
tHW
Read/Write (R/W) Hold Time
0.5
____
0.5
____
ns
tHADV
Advance/Load (ADV/LD) Hold Time
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
ns
tHB
Byte Write Enable (BWx) Hold Time
0.5
____
0.5
____
tOLZ
tOHZ
Setup Times
Hold Times
ns
3821 tbl 23
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 2.0V and LOW below 0.8V.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
14
15
6.42
A1
tSADV
tHA
tHW
tHE
tCLZ
tHC
Pipeline
Read
tSC
A2
tSA
tSW
tSE
tCD
Pipeline
Read
O1(A1)
tHADV
tCH
O1(A2)
tCDC
tCL
Q(A2+1)
Q(A2+2)
(CEN high, eliminates
current L-H clock edge)
Burst Pipeline Read
tCD
Q(A2+2)
tCDC
Q(A2+3)
O1(A2)
tCHZ
3821 drw 06
(Burst Wraps around
to initial state)
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the
burst sequence of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
DATA Out
OE
BW1,BW4
CE1,CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
16
A1
tSADV
tHA
tHW
tHE
tHB
tHC
Pipeline
Write
tSB
tSC
A2
tSA
tSW
tSE
tHD
Pipeline
Write
D(A1)
tSD
tHADV
tCH
tCL
D(A2)
.
D (A2+1)
Burst Pipeline Write
(CEN high, eliminates
current L-H clock edge)
tSD
D (A2+2)
tHD
3821 drw 07
D (A2+3)
(Burst Wraps around
to initial state)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
DATA In
OE
BW1,BW4
CE1,CE2
(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
D(A2)
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
17
6.42
A1
tSADV
tHA
tHW
tHE
tCD
tHB
tHC
Read
tSB
tSC
A2
tSA
tSW
tSE
A3
Q(A1)
Write
tHADV
tCH
tCHZ
Read
tCLZ
D(A2)
tSD tHD
A4
tCL
Q(A3)
tCDC
Write
A5
D(A4)
A6
Read
D(A5)
A7
Q(A6)
A8
Q(A7)
A9
3821 drw 08
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
DATA Out
DATA In
OE
BW1 - BW4
CE1, CE2
(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
.
18
A1
tSE
tSADV
tHE
tHA
tHW
tHB
tHC
tCD
tCLZ
B(A2)
tSB
tSC
A2
tSA
tSW
tCH
tHADV
Q(A1)
tCL
tCHZ
tCDC
Q(A1)
A3
D(A2)
tSD tHD
A4
.
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH..
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal
registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
DATA Out
DATA In
OE
BW1 - BW4
CE1, CE2 (2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
3821 drw 09
Q(A3)
A5
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
19
6.42
A1
tSADV
tHA
tHW
tHE
tSC
tCLZ
tCD
tHC
A2
tSA
tSW
tSE
Q(A1)
tHADV
tCH
tCDC
tCHZ
tHB
Q(A2)
tSB
A3
tCL
D(A3)
tSD tHD
A4
Q(A3)
A5
3821 drw 10
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states two cycles after the initiation
of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
DATA Out
DATA In
OE
BW1 - BW4
CE1,CE2 (2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
tOLZ
Valid
DATA Out
NOTE:
1. A read operation is assumed to be in progress.
3821 drw 11
Ordering Information
XXXXX
Device
Type
S
XX
Power Speed
XX
X
X
X
Process/
Temperature
Range
Package
Blank
8
Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
PF
100 pin Plastic Thin Quad Flatpack (PKG100)
133
100
Clock Frequency in Megahertz
S
Standard Power
71V546
128K x 36 Pipelined ZBT SRAM
3821 drw 13
NOTES:
1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
Orderable Part Information
Speed
(ns)
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
100
71V546S100PFG
PKG100
TQFP
C
71V546S100PFG8
PKG100
TQFP
C
71V546S100PFGI
PKG100
TQFP
I
133
71V546S100PFGI8
PKG100
TQFP
I
71V546S133PFG
PKG100
TQFP
C
71V546S133PFG8
PKG100
TQFP
C
71V546S133PFGI
PKG100
TQFP
I
71V546S133PFGI8
PKG100
TQFP
I
3821t25.tbl
20
IDT71V546 128K x 36, 3.3V Synchronous SRAM with
™ Feature, Burst Counter and Pipelined Outputs
ZBT™
Commercial and Industrial Temperature Ranges
Datasheet Document History
6/15/99
9/13/99
12/31/99
11/22/05
Pg. 12
Pg. 20
Pg. 3, 12, 13, 19
Pg. 3,4
02/23/07
10/18/08
08/18/17
Pg. 20
Pg. 20
Pg. 20
Pg. 1
Pg. 2
Pg. 4
Pg. 13
Pg. 14
Pg. 20
Updated to new format
Corrected ISB3 conditions
Added Datasheet Document History
Added Industrial Temperature range offerings
Moved Operating temperature & DC operating tables from page 3 to new page 5. Moved Absolute
rating & Capacitance tables from page 4 to new page 5. Add clarification note to Recommended
Operating Temperature and Absolute Max Ratings tables.
Updated order information with "Restricted hazardous substance device"
Added X generation die step to data sheet ordering information
Removed "IDT" for orderable part number
Removed all information for 71V546XS
In Features: Added text: "Green parts available, see Ordering Information"
Moved the FBD from page 3 to page 1 in accordance with our standard datasheet format
Removed the IDT in reference to fabrication
Updated the TQFP pin configuration by rotating package pin labels and pin numbers 90 degrees
counter clockwise added IDT logo & in accordance with the packaging code, changed the PK100
designation to PKG100 , changed the text to be in alignment with new diagram marking specs
Removed footnote 2 and the 2 annotation for NC pins 83 & 84 in the TQFP pin configuration
Removed 117 MHz speed grade offering from the DC Electrical table
Removed 117 MHz speed grade offering from the AC Electrical table
Removed Tube indicator, updated "Restricted hazardous substance" device to "Green"
Updated package code in Ordering Information from PK100 to PKG100 and removed the
117 MHz speed grade offering
Added Orderable Part Information
Removed the 100 Thin Quad Flatpack Packaging Table
21
6.42
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