256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs
Features
◆
◆
◆
◆
◆
◆
◆
◆
256K x 36, 512K x 18 memory configurations
Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
4-word burst capability (Interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
◆
◆
◆
◆
◆
◆
71V65703
71V65903
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V (±5%) I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram — 256K x 36
256K x 36 BIT
MEMORY ARRAY
LBO
Address A [0:17]
D
Q
Address
D
Q
Control
CE1, CE2, CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
DO
Control Logic
Q
Clk
Mux
Clock
Sel
Gate
OE
Data I/O [0:31], I/O P[1:4]
5298 drw 01
ZBT and Zero Bus Turnaround are trademarks of Renesas Electronics Corporation and the architecture is supported by Micron Technology and Motorola, Inc.
1
Oct.18.21
,
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Description
The IDT71V65703/5903 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18.
They are designed to eliminate dead bus cycles when turning the bus
around between reads and writes, or writes and reads. Thus they have
been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and on the next clock cycle the associated data cycle occurs,
be it read or write.
The IDT71V65703/5903 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65703/5903
tobesuspendedaslongasnecessary.Allsynchronousinputsareignoredwhen
CEN is high and the internal device registers will hold their previous values.
Commercial and Industrial Temperature Ranges
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71V65703/5903 have an on-chip burst counter. In the burst
mode, the IDT71V65703/5903 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V65703/5903 SRAMs utilize a high-performance CMOS
process and are packaged in a JEDEC Standard 14mm x 20mm 100pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and a 165
fine pitch ball grid array (fBGA).
Functional Block Diagram — 512K x 18
LBO
Address A [0:18]
512K x 18 BIT
MEMORY ARRAY
D
Q
Address
D
Q
Control
CE1, CE, CE2
R/W
Input Register
CEN
ADV/LD
BWx
D
DI
Q
DO
Control Logic
Clk
Mux
Clock
Sel
Gate
OE
Data I/O [0:15], I/O P[1:2]
5298 drw 01a
6.42
2
Oct.18.21
,
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Description Summary
A0-A 18
Address Inputs
Input
Synchronous
CE1, CE 2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/LD
Advance Burst Address/Load New Address
Input
Synchronous
LBO
Linear/Interleaved Burst Order
Input
Static
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31 , I/OP1-I/OP4
Data Input/Output
I/O
Synchronous
VDD, V DDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
Supply
Static
5298 tbl 01
6.42
3
Oct.18.21
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Pin Definitions
Commercial and Industrial Temperature Ranges
(1)
Symbol
Pin Function
I/O
Active
Description
A0-A18
Address Inputs
I
N/A
Synchro nous Address inputs. The address register is triggered by a co mbination of the rising edge of
CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchro nous input that is used to load the inte rnal registers with new address and control
when it is sample d low at the rising edge of clock with the chip selected. When ADV/LD is low with
the chip deselected, any burst in progress is terminated. When ADV/LD is sampled high then the
inte rnal burst counter is advanced for any burst that was in progress. The external addresses are
ignored when ADV/LD is sampled high.
R/W
Read / Write
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or
Write access to the memory array. The data bus activity for the curre nt cycle takes place one clock
cycle later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including
clock are ignored and outputs re main unchanged. The effect of CEN sampled high on the device
outputs is as if the low to high clock transition did no t occur. For normal operation, CEN must be
sampled low at rising edge of clock.
BW1-BW4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4)
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write
signals are ignored when R/W is sampled high. The appropriate byte(s) of data are written into the
device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word.
CE1, CE2
Chip Enables
I
LOW
Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V65703/5903
(CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates
a deselect cycle. The ZBTTM has a one cycle deselect, i.e., the data b us will tri-state one clock cycle
after deselect is initiated.
CE2
Chip Enable
I
HIGH
Synchrono us active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE 2 has
inverted po larity but otherwise identical to CE1 and CE2.
CLK
Clock
I
N/A
This is the clock input to the IDT71V65703/5903. Except for OE, all timing references for the device are
made with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4
Data Input/Output
I/O
N/A
Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The
data output path is flow-through (no output register).
LBO
Linear Burst
Order
I
LOW
Burst order selection input. When LBO is high the Inte rleaved burst sequence is selected. When LBO
is low the Linear burst sequence is selected. LBO is a static input, and it must not change during
device operation.
OE
Output Enable
I
LOW
Asynchronous output enable. OE must be low to read data from the 71V65703/5903. When OE is HIGH
the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and
write cycles. In normal operation, OE can be tied low.
ZZ
Sleep Mode
I
HIGH
Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V65703/5903 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.
VDD
Power Supply
N/A
N/A
3.3V core power supply.
VDDQ
Power Supply
N/A
N/A
3.3V I/O supply.
VSS
Ground
N/A
N/A
Ground.
5298 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
4
Oct.18.21
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
CE2
BW4
BW3
BW2
BW1
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
NC
A17
A8
A9
A6
A7
CE1
Pin Configuration — 256K x 36, PKG100(4)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
VDD(2)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
71
10
11
12
13
14
70
71V65703
PKG100
69
68
67
15
66
16
65
64
17
18
63
19
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
54
53
28
29
52
51
30
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VSS(1)
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LBO
A5
A4
A3
A2
A1
A0
DNU(3)
DNU(3)
VSS
VDD
DNU(3)
DNU(3)
A10
A11
A12
A13
A14
A15
A16
5298 drw 02
Top View
100 TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. DNU = Do not use. Pins 38, 39, 42 and 43 can be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
4. This text does not indicate the orientation of the actual part-marking.
6.42
5
Oct.18.21
,
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
A6
A7
CE1
CE2
NC
NC
BW2
BW1
CE2
VDD
VSS
CLK
R/W
CEN
OE
ADV/LD
NC
A18
A8
A9
Pin Configuration — 512K x 18, PKG100(4)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
2
79
3
78
VDDQ
VSS
NC
NC
I/O8
I/O9
VSS
VDDQ
I/O10
I/O11
VSS(1)
VDD
VDD(2)
VSS
I/O12
I/O13
VDDQ
VSS
I/O14
I/O15
I/OP2
NC
VSS
VDDQ
NC
NC
NC
4
77
5
6
76
75
7
74
8
73
9
72
71
10
11
12
13
14
70
71V65903
PKG100
69
68
67
15
66
16
65
64
17
18
19
63
62
20
61
21
60
22
59
23
24
58
57
25
56
26
55
27
54
53
28
29
52
51
30
A10
NC
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VSS(1)
VDD
ZZ
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
NC
,
LBO
A5
A4
A3
A2
A1
A0
DNU(3)
DNU(3)
VSS
VDD
DNU(3)
DNU(3)
A11
A12
A13
A14
A15
A16
A17
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5298 drw 02a
Top View
100 TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. DNU = Do not use. Pins 38, 39, 42 and 43 can be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
4. This text does not indicate the orientation of the actual part-marking.
6.42
6
Oct.18.21
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 256K x 36, BG119, BGG119(4)
1
2
3
4
5
6
7
A8
A16
VDDQ
A9
CE2
NC
A
VDDQ
A6
A4
B
NC
CE 2
A3
C
NC
A7
A2
VDD
A12
A15
NC
D
I/O16
I/OP3
VSS
NC
VSS
I/OP2
I/O15
E
I/O17
I/O18
VSS
CE1
VSS
I/O13
I/O14
F
VDDQ
I/O19
VSS
OE
VSS
I/O12
V DDQ
G
I/O 20
I/O 21
BW3
A17
BW 2
I/O11
I/O10
H
I/O 22
I/O 23
VSS
R/W
VSS
I/O 9
I/O8
VDD
VDD(2)
VDD
VSS(1)
VDD
VDDQ
CLK
VSS
I/O 6
I/O7
J
VDDQ
NC
ADV/LD
K
I/O 24
I/O 26
VSS
L
I/O 25
I/O 27
BW4
NC
BW1
I/O 4
I/O 5
M
VDDQ
I/O28
VSS
CEN
VSS
I/O 3
VDDQ
N
I/O 29
I/O30
VSS
A1
VSS
I/O 2
I/O1
P
I/O 31
I/OP4
VSS
A0
VSS
I/OP1
I/O 0
R
NC
A5
LBO
VDD
VSS(1)
A13
NC
T
NC
NC
A10
A11
A14
NC
ZZ
DNU(3)
DNU(3)
DNU(3)
DNU(3)
VDDQ
U
VDDQ
DNU(3)
Top View
5298 drw 13a
Pin Configuration — 512K x 18, BG119, BGG119(4)
1
2
3
4
5
6
7
A
VDDQ
A6
A4
NC
A8
A16
VDDQ
B
NC
CE2
A3
A9
CE2
NC
C
NC
A7
A2
VDD
A13
A17
NC
D
NC
ADV/LD
I/O 8
NC
VSS
NC
VSS
I/OP1
E
NC
I/O 9
VSS
CE1
VSS
NC
I/O7
F
VDDQ
NC
VSS
OE
VSS
I/O6
VDDQ
G
NC
I/O10
BW2
A18
VSS
NC
I/O5
H
I/O11
NC
VSS
R/W
VSS
I/O4
NC
J
VDDQ
VDD
VDD(2)
VDD
V SS(1)
VDD
VDDQ
K
NC
I/O12
VSS
CLK
VSS
NC
I/O3
L
I/O13
NC
VSS
NC
BW1
I/O2
NC
M
VDDQ
I/O14
VSS
CEN
VSS
NC
VDDQ
N
I/O15
NC
VSS
A1
VSS
I/O1
NC
VSS
A0
VSS
P
NC
I/OP2
NC
I/O0
R
NC
A5
LBO
VDD
VSS(1)
A12
NC
T
NC
A10
A15
NC
A14
A11
ZZ
DNU(3)
VDDQ
U
VDDQ
DNU(3)
DNU(3)
DNU(3)
Top View
DNU(3)
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
3. DNU = Do not use. Pins U2, U3, U4, U5 and U6 can be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
4. This text does not indicate the orientation of the actual part-marking.
6.42
7
Oct.18.21
5298 drw 13b
,
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 256K x 36, BQ165, BQG165(4)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A7
CE1
BW3
BW2
CE2
CEN
ADV/LD
A17
A8
NC
B
NC
A6
CE2
BW4
BW1
CLK
R/W
OE
NC
A9
NC
C
I/OP3
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP2
D
I/O17
I/O16
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O15
I/O14
E
I/O19
I/O18
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O13
I/O12
F
I/O21
I/O20
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O11
I/O10
G
I/O23
I/O22
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O9
I/O8
H
VSS
VDD
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
I/O25
I/O24
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O7
I/O6
K
I/O27
I/O26
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O5
I/O4
L
I/O29
I/O28
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
I/O2
M
I/O31
I/O30
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
I/O0
N
I/OP4
NC
VDDQ
VSS
DNU
NC
VSS
VSS
VDDQ
NC
I/OP1
P
NC
NC
A5
A2
DNU
A1
DNU
A10
A13
A14
NC
LBO
NC
A4
A3
DNU
A0
DNU
A11
A12
A15
R
(1)
(2)
(3)
(3)
(3)
(1)
(3)
(3)
A16
5298 tbl 25a
Pin Configuration — 512K x 18, BQ165, BQG165(4)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A7
CE1
BW2
NC
CE2
CEN
ADV/LD
A18
A8
A10
B
NC
A6
CE2
NC
BW1
CLK
R/W
OE
NC
A9
NC
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
I/OP1
D
NC
I/O8
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O7
E
NC
I/O9
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O6
F
NC
I/O10
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O5
G
NC
I/O11
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
I/O4
H
VSS(1)
VDD(2)
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
I/O12
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O3
NC
K
I/O13
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O2
NC
L
I/O14
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O1
NC
M
I/O15
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
I/O0
NC
N
I/OP2
NC
VDDQ
VSS
DNU(3)
NC
VSS(1)
VSS
VDDQ
NC
NC
P
NC
NC
A5
A2
(3)
DNU
A1
(3)
DNU
A11
A14
A15
NC
R
LBO
NC
A4
A3
DNU(3)
A0
DNU(3)
A12
A13
A16
A17
5298 tbl 25b
NOTES:
1. Pins H1 and N7 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin H2 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. DNU = Do not use. Pins P5, R5, P7, R7 and N5 can be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
4. This text does not indicate the orientation of the actual part-marking.
6.42
8
Oct.18.21
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Absolute Maximum Ratings(1)
Recommended DC Operating
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDQ
I/O Supply Voltage
3.135
3.3
3.465
V
VSS
Ground
0
0
0
V
VIH
Input High Voltage - Inputs
2.0
____
VDD + 0.3
V
VIH
Input High Voltage - I/O
2.0
____
VDDQ + 0.3
V
VIL
Input Low Voltage
-0.3(1)
____
0.8
Symbol
V
NOTE:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
Grade
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V
3.3V±5%
3.3V±5%
Industrial
-40°C to +85°C
0V
3.3V±5%
3.3V±5%
-0.5 to +4.6
V
VTERM(3,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD
V
VTERM(4,6)
Terminal Voltage with
Respect to GND
-0.5 to VDD +0.5
V
VTERM(5,6)
Terminal Voltage with
Respect to GND
-0.5 to VDDQ +0.5
V
Commercial
0 to +70
o
C
Industrial
-40 to +85
o
C
TBIAS
Temperature Under Bias
-55 to +125
o
C
TSTG
Storage Temperature
-55 to +125
o
C
PT
Power Dissipation
2.0
IOUT
DC Output Current
50
CIN
Input Capacitance
CI/O
I/O Capacitance
(TA = +25°°C, f = 1.0MHz)
Conditions
Max.
Unit
Symbol
VIN = 3dV
5
pF
CIN
Input Capacitance
VOUT = 3dV
7
pF
CI/O
I/O Capacitance
5298 tbl 07
165 fBGA Capacitance(1)
(TA = +25°°C, f = 1.0MHz)
Symbol
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 3dV
TBD
pF
VOUT = 3dV
TBD
pF
5298 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
9
Oct.18.21
mA
119 BGA Capacitance(1)
(TA = +25°°C, f = 1.0MHz)
Parameter
W
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the “instant on” case temperature.
100 TQFP Capacitance(1)
Symbol
Unit
5298 tbl 06
5298 tbl 05
NOTE:
1. TA is the “instant on” case temperature.
Commercial &
Industrial
Terminal Voltage with
Respect to GND
5298 tbl 04
Recommended Operating
Temperature and Supply Voltage
Rating
VTERM(2)
TA(7)
(1)
Commercial and Industrial Temperature Ranges
Parameter(1)
Conditions
Max.
Unit
VIN = 3dV
7
pF
VOUT = 3dV
7
pF
5298 tbl 07a
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
(1)
Synchronous Truth Table
CEN
R/W
CE 1,CE 2(5)
ADV/LD
BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L
L
L
L
Valid
External
X
LOAD WRITE
D(7)
L
H
L
L
X
External
X
LOAD READ
Q(7)
L
X
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
D(7)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
(Advance burst counter)(2)
Q(7)
L
X
H
L
X
X
X
DESELECT or STOP(3)
HIZ
L
X
X
H
X
X
DESELECT / NOOP
NOOP
HIZ
H
X
X
X
X
X
(4)
X
SUSPEND
Previous Value
5298 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propagating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
OPERATION
R/W
BW 1
BW 2
BW 3(3)
BW 4(3)
H
X
X
X
X
L
L
L
L
L
L
L
H
H
H
READ
WRITE ALL BYTES
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1)
(2)
WRITE BYTE 2 (I/O[8:15], I/OP2)
L
H
L
H
H
(2,3)
L
H
H
L
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4)
L
H
H
H
L
NO WRITE
L
H
H
H
H
WRITE BYTE 3 (I/O[16:23], I/OP3)
5298 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address (1)
1
1
1
0
0
1
0
0
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
6.42
10
Oct.18.21
5298 tbl 10
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
Fourth Address
(1)
5298 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
A29
A30
A31
A32
A33
A34
A35
A36
A37
C29
C30
C31
C32
C33
C34
C35
C36
C37
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
CLOCK
ADDRESS
(2)
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
DATA
(2)
I/O [0:31], I/O P[1:4]
5298 drw 03
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
11
Oct.18.21
,
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2)
Cycle
Address
R/W
ADV/LD
CE 1(1)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
D1
Load read
n+1
X
X
H
X
L
X
L
Q0
Burst read
n+2
A1
H
L
L
L
X
L
Q0+1
Load read
n+3
X
X
L
H
L
X
L
Q1
Deselect or STOP
n+4
X
X
H
X
L
X
X
Z
NOOP
n+5
A2
H
L
L
L
X
X
Z
Load read
n+6
X
X
H
X
L
X
L
Q2
Burst read
n+7
X
X
L
H
L
X
L
Q2+1
n+8
A3
L
L
L
L
L
X
Z
Load write
n+9
X
X
H
X
L
L
X
D3
Burst write
n+10
A4
L
L
L
L
L
X
D3+1
Load write
n+11
X
X
L
H
L
X
X
D4
Deselect or STOP
n+12
X
X
H
X
L
X
X
Z
NOOP
n+13
A5
L
L
L
L
L
X
Z
Load write
n+14
A6
H
L
L
L
X
X
D5
Load read
n+15
A7
L
L
L
L
L
L
Q6
Load write
n+16
X
X
H
X
L
L
X
D7
Burst write
n+17
A8
H
L
L
L
X
X
D7+1
Load read
n+18
X
X
H
X
L
X
L
Q8
Burst read
n+19
A9
L
L
L
L
L
L
Q8+1
Load write
Deselect or STOP
5298 tbl 12
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedance.
6.42
12
Oct.18.21
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation(1)
Cycle
Address
R/W
ADV/LD
CE 1(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
X
X
X
X
L
Q0
Contents of Address A0 Read Out
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5298 tbl 13
Burst Read Operation(1)
Cycle
Address
R/W
ADV/LD
CE 1(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
Address and Control meet setup
n+1
X
X
H
X
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+2
X
X
H
X
L
X
L
Q0+1
Address A0+1 Read Out, Inc. Count
n+3
X
X
H
X
L
X
L
Q0+2
Address A0+2 Read Out, Inc. Count
n+4
X
X
H
X
L
X
L
Q0+3
Address A0+3 Read Out, Load A1
n+5
A1
H
L
L
L
X
L
Q0
Address A0 Read Out, Inc. Count
n+6
X
X
H
X
L
X
L
Q1
Address A1 Read Out, Inc. Count
n+7
A2
H
L
L
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5298 tbl 14
Write Operation(1)
Cycle
Address
R/W
ADV/LD
CE 1(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
X
X
L
X
X
D0
Write to Address A0
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5298 tbl 15
Burst Write Operation(1)
Cycle
Address
R/W
ADV/LD
CE 1(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address and Control meet setup
n+1
X
X
H
X
L
L
X
D0
Address A0 Write, Inc. Count
n+2
X
X
H
X
L
L
X
D0+1
Address A0+1 Write, Inc. Count
n+3
X
X
H
X
L
L
X
D0+2
Address A0+2 Write, Inc. Count
n+4
X
X
H
X
L
L
X
D0+3
Address A0+3 Write, Load A1
n+5
A1
L
L
L
L
L
X
D0
Address A0 Write, Inc. Count
n+6
X
X
H
X
L
L
X
D1
Address A1 Write, Inc. Count
n+7
A2
L
L
L
L
L
X
D1+1
Address A1+1 Write, Load A2
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
13
Oct.18.21
5298 tbl 16
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE 1(2)
CEN
BWx
OE
I/O
Comments
n
A0
H
L
L
L
X
X
X
AddressA0 and Control meet setup
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored
n+2
A1
H
L
L
L
X
L
Q0
Address A0 Read out, Load A1
n+3
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+4
X
X
X
X
H
X
L
Q0
Clock Ignored. Data Q0 is on the bus.
n+5
A2
H
L
L
L
X
L
Q1
Address A1 Read out, Load A 2
n+6
A3
H
L
L
L
X
L
Q2
Address A2 Read out, Load A 3
n+7
A4
H
L
L
L
X
L
Q3
Address A3 Read out, Load A 4
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
5298 tbl 17
Write Operation with Clock Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE 1(2)
CEN
BWx
OE
I/O
Comments
n
A0
L
L
L
L
L
X
X
Address A0 and Control meet setup.
n+1
X
X
X
X
H
X
X
X
Clock n+1 Ignored.
n+2
A1
L
L
L
L
L
X
D0
Write data D0, Load A1.
n+3
X
X
X
X
H
X
X
X
Clock Ignored.
n+4
X
X
X
X
H
X
X
X
Clock Ignored.
n+5
A2
L
L
L
L
L
X
D1
Write Data D1, Load A2
n+6
A3
L
L
L
L
L
X
D2
Write Data D2, Load A3
n+7
A4
L
L
L
L
L
X
D3
Write Data D3, Load A4
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
6.42
14
Oct.18.21
5298 tbl 18
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE 1(2)
CEN
BWx
OE
I/O(3)
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
Z
Deselected.
n+2
A0
H
L
L
L
X
X
Z
Address A0 and Control meet setup.
n+3
X
X
L
H
L
X
L
Q0
Address A0 read out, Deselected.
n+4
A1
H
L
L
L
X
X
Z
Address A1 and Control meet setup.
n+5
X
X
L
H
L
X
L
Q1
Address A1 read out, Deselected.
n+6
X
X
L
H
L
X
X
Z
Deselected.
n+7
A2
H
L
L
L
X
X
Z
Address A2 and Control meet setup.
n+8
X
X
L
H
L
X
L
Q2
Address A2 read out, Deselected.
n+9
X
X
L
H
L
X
X
Z
Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
5298 tbl 19
Write Operation with Chip Enable Used(1)
Cycle
Address
R/W
ADV/LD
CE (2)
CEN
BWx
OE
I/O
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
Z
Deselected.
n+2
A0
L
L
L
L
L
X
Z
Address A0 and Control meet setup
n+3
X
X
L
H
L
X
X
D0
Data D0 Write In, Deselected.
n+4
A1
L
L
L
L
L
X
Z
Address A1 and Control meet setup
n+5
X
X
L
H
L
X
X
D1
Data D1 Write In, Deselected.
n+6
X
X
L
H
L
X
X
Z
Deselected.
n+7
A2
L
L
L
L
L
X
Z
Address A2 and Control meet setup
n+8
X
X
L
H
L
X
X
D2
Data D2 Write In, Deselected.
n+9
X
X
L
H
L
X
X
Z
Deselected.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
15
Oct.18.21
5298 tbl 20
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V±5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to V DD
___
5
µA
|ILI|
LBO Input Leakage Current(1)
VDD = Max., VIN = 0V to V DD
___
30
µA
|ILO|
Output Leakage Current
VOUT = 0V to V CC
___
5
µA
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
5298 tbl 21
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V±5%)
Symbol
Parameter
7.5ns
Test Conditions
8ns
8.5ns
Com'l
Ind
Com'l
Ind
Com'l
Ind
Unit
IDD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX(2)
275
295
250
60
225
60
mA
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = 0(2,3)
40
60
40
60
40
60
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = fMAX(2,3)
105
125
100
120
95
115
mA
ISB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX(2,3)
40
60
40
60
40
60
mA
IZZ
Full Sleep Mode
Supply Current
Device Selected, Outputs Open,
CEN < VIL, VDD = Max., ZZ > VHD
VIN > VHD or < VLD, f = fMAX(2,3)
40
60
40
60
40
60
mA
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Load
AC Test Conditions
VDDQ/2
Input Pulse Levels
50Ω
I/O
Z0 = 50Ω
,
5298 drw 04
6
Figure 1. AC Test Load
5
3
ΔtCD
(Typical, ns)
2
1
• •
20 30 50
80 100
200
,
5298 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
16
Oct.18.21
2ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Figure 1
5298 tbl 23
• •
Capacitance (pF)
0 to 3V
Input Rise/Fall Times
Output Load
•
4
5298 tbl 22
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)
7.5ns
Symbol
8.5ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock Cycle Time
10
____
10.5
____
11
____
ns
(1)
tCH
Clock High Pulse Width
2.5
____
2.7
____
3.0
____
ns
tCL(1)
Clock Low Pulse Width
2.5
____
2.7
____
3.0
____
ns
____
7.5
____
8
____
8.5
ns
tCYC
Parameter
8ns
Output Parameters
tCD
Clock High to Valid Data
tCDC
Clock High to Data Change
2
____
2
____
2
____
ns
tCLZ
Clock High to Output Active
3
____
3
____
3
____
ns
tCHZ(2,3,4)
Clock High to Data High-Z
____
5
____
5
____
5
ns
tOE
Output Enable Access Time
____
5
____
5
____
5
ns
tOLZ(2,3)
Output Enable Low to Data Active
0
____
0
____
0
____
ns
tOHZ(2,3)
Output Enable High to Data High-Z
____
5
____
5
____
5
ns
(2,3,4)
Set Up Times
tSE
Clock Enable Setup Time
2.0
____
2.0
____
2.0
____
ns
tSA
Address Setup Time
2.0
____
2.0
____
2.0
____
ns
tSD
Data In Setup Time
2.0
____
2.0
____
2.0
____
ns
tSW
Read/Write (R/W) Setup Time
2.0
____
2.0
____
2.0
____
ns
tSADV
Advance/Load (ADV/LD) Setup Time
2.0
____
2.0
____
2.0
____
ns
tSC
Chip Enable/Select Setup Time
2.0
____
2.0
____
2.0
____
ns
tSB
Byte Write Enable (BWx) Setup Time
2.0
____
2.0
____
2.0
____
ns
tHE
Clock Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tHD
Data In Hold Time
0.5
____
0.5
____
0.5
____
ns
tHW
Read/Write (R/W) Hold Time
0.5
____
0.5
____
0.5
____
ns
tHADV
Advance/Load (ADV/LD) Hold Time
0.5
____
0.5
____
0.5
____
ns
tHC
Chip Enable/Select Hold Time
0.5
____
0.5
____
0.5
____
ns
tHB
Byte Write Enable (BWx) Hold Time
0.5
____
0.5
____
0.5
____
Hold Times
ns
5298 tbl 24
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6.42
17
Oct.18.21
Oct.18.21
6.42
18
tCLZ
A1
tHA
tHW
tHE
tSC
tCD
tHC
A2
tSA
tSW
Q(A1)
Read
tSADV
tSE
Read
Q(A2)
tCDC
tHADV
tCH
Q(A2+1)
tCD
tCL
Burst Read
Q(A2+2)
Q(A2+3)
(CEN high, eliminates
current L-H clock edge)
tCDC
Q(A2+3)
Q(A2)
(Burst Wraps around
to initial state)
tCHZ
NOTES:
1. Q (A1) represents the first output from the external address A1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don’t care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
DATAOUT
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
5298 drw 06
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
Oct.18.21
6.42
19
B(A1)
A1
Write
tSADV
tHW
tHE
tHC
tHD
D(A1)
tSD
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
tSE
Write
D(A2)
B(A2+1)
tHADV
tCH
tHD
D(A2+1)
tSD
B(A2+2)
tCL
(CEN high, eliminates
current L-H clock edge)
Burst Write
D(A2+2)
B(A2+3)
D(A2+3)
(Burst Wraps around
to initial state)
B(A2)
D(A2)
5298 drw 07
,
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base
address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don’t care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles(1,2,3,4,5)
Oct.18.21
6.42
20
A1
tCD
tHW
tHE
tHC
tCHZ
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
Q(A1)
Read
tSADV
tSE
Write
A3
tCLZ
D(A2)
tSD tHD
tHADV
tCH
Read
Q(A3)
tCDC
B(A4)
A4
tCL
Write
D(A4)
B(A5)
A5
Write
D(A5)
A6
Read
Q(A6)
A7
Read
Q(A7)
B(A8)
A8
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
5298 drw 08
Write
D(A8)
A9
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
,
Oct.18.21
6.42
21
tCD
tCLZ
A1
Q(A1)
tSE
tSADV
tHE
tHW
tHC
Q(A1)
tCDC
tCHZ
tHB
B(A2)
tSB
tSC
tHA
A2
tSA
tSW
tCH
tHADV
tCL
tCD
D(A2)
tSD tHD
A3
Q(A3)
tCDC
A4
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCYC
5298 drw 09
Q(A4)
A5
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation(1,2,3,4)
,
Oct.18.21
6.42
22
DATAOUT
DATAIN
OE
BW1 - BW4
CE1, CE2(2)
ADDRESS
R/W
ADV/LD
CEN
CLK
tCD
tSC
Q(A1)
tHW
tHC
tHA
A2
tSA
tSW
tHE
tCHZ
tCDC
Q(A2)
tHADV
tCH
tHB
B(A3)
tSB
A3
tCL
D(A3)
tSD tHD
A4
Q(A4)
A5
5298 drw 10
Q(A5)
,,
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the
deselect cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one
cycle before the actual data is presented to the SRAM.
tCLZ
A1
tSADV
tSE
tCYC
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
tOE
tOHZ
DATAOUT
tOLZ
Q
Q
5298 drw 11c
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
XXXX
S
XX
X
Device
Type
Power
Speed
Package
X
X
Process/
Temperature
Range
X
Blank
8
Tray
Tape and Reel
Blank
I(2)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(3)
Green
PF
BG
BQ
100-pin Plastic Thin Quad Flatpack (PKG100)
119 Ball Grid Array (BG119, BGG119)
165 Fine Pitch Ball Grid Array (BQ165, BQG165)
75(1)
80
85
Access time (tCD) in tenths of nanoseconds
S
Standard Power
71V65703
71V65903
256Kx36 Flow-Through ZBT SRAM
512Kx18 Flow-Through ZBT SRAM
NOTES:
1. 71V65703 only.
2. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
3. Green parts available. For specific speeds, packages and powers contact your local sales office.
6.42
23
Oct.18.21
5298 drw 12
,
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Orderable Part Information
Speed
(ns)
7.5
8.0
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
71V65703S75BG
BG119
PBGA
C
8.5
71V65703S75BG8
BG119
PBGA
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
71V65703S85BG
BG119
PBGA
C
C
71V65703S85BG8
BG119
PBGA
C
Orderable Part ID
71V65703S75BGG
BGG119
PBGA
C
71V65703S85BGG
BGG119
PBGA
C
71V65703S75BGG8
BGG119
PBGA
C
71V65703S85BGG8
BGG119
PBGA
C
71V65703S75BQ
BQ165
CABGA
C
71V65703S85BGGI
BGG119
PBGA
I
71V65703S75BQ8
BQ165
CABGA
C
71V65703S85BGGI8
BGG119
PBGA
I
71V65703S75BQG
BQG165
CABGA
C
71V65703S85BGI
BG119
PBGA
I
BG119
PBGA
I
BQ165
CABGA
C
71V65703S75BQG8
BQG165
CABGA
C
71V65703S85BGI8
71V65703S75PFG
PKG100
TQFP
C
71V65703S85BQ
71V65703S75PFG8
PKG100
TQFP
C
71V65703S85BQ8
BQ165
CABGA
C
BQG165
CABGA
C
71V65703S75PFGI
PKG100
TQFP
I
71V65703S85BQG
71V65703S75PFGI8
PKG100
TQFP
I
71V65703S85BQG8
BQG165
CABGA
C
71V65703S80BG
BG119
PBGA
C
71V65703S85BQGI
BQG165
CABGA
I
71V65703S80BG8
BG119
PBGA
C
71V65703S85BQGI8
BQG165
CABGA
I
BQ165
CABGA
I
BQ165
CABGA
I
71V65703S80BGG
BGG119
PBGA
C
71V65703S85BQI
71V65703S80BGG8
BGG119
PBGA
C
71V65703S85BQI8
BQ165
CABGA
C
71V65703S85PFG
PKG100
TQFP
C
PKG100
TQFP
C
71V65703S80BQ
71V65703S80BQ8
BQ165
CABGA
C
71V65703S85PFG8
71V65703S80BQG
BQG165
CABGA
C
71V65703S85PFGI
PKG100
TQFP
I
71V65703S80BQG8
BQG165
CABGA
C
71V65703S85PFGI8
PKG100
TQFP
I
71V65703S80BQGI
BQG165
CABGA
I
71V65703S80BQGI8
BQG165
CABGA
I
71V65703S80BQI
BQ165
CABGA
I
71V65703S80BQI8
BQ165
CABGA
I
71V65703S80PFG
PKG100
TQFP
C
71V65703S80PFG8
PKG100
TQFP
C
71V65703S80PFGI
PKG100
TQFP
I
71V65703S80PFGI8
PKG100
TQFP
I
6.42
24
Oct.18.21
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Orderable Part Information (con’t)
Pkg.
Code
Pkg.
Type
Temp.
Grade
71V65903S80BG
BG119
PBGA
C
71V65903S80BG8
BG119
PBGA
C
71V65903S80BGI
BG119
PBGA
I
71V65903S80BGI8
BG119
PBGA
I
71V65903S80BQ
BQ165
CABGA
C
71V65903S80BQ8
BQ165
CABGA
C
71V65903S80BQG
BQG165
CABGA
C
71V65903S80BQG8
BQG165
CABGA
C
Speed
(ns)
8.0
8.5
Orderable Part ID
71V65903S80PFG
PKG100
TQFP
C
71V65903S80PFG8
PKG100
TQFP
C
71V65903S80PFGI
PKG100
TQFP
I
71V65903S80PFGI8
PKG100
TQFP
I
71V65903S85BG
BG119
PBGA
C
71V65903S85BG8
BG119
PBGA
C
71V65903S85BGG
BGG119
PBGA
C
71V65903S85BGG8
BGG119
PBGA
C
71V65903S85BGGI
BGG119
PBGA
I
71V65903S85BQ
BQ165
CABGA
C
71V65903S85BQ8
BQ165
CABGA
C
71V65903S85BQG
BQG165
CABGA
C
71V65903S85BQG8
BQG165
CABGA
C
71V65903S85PFG
PKG100
TQFP
C
71V65903S85PFG8
PKG100
TQFP
C
71V65903S85PFGI
PKG100
TQFP
I
71V65903S85PFGI8
PKG100
TQFP
I
6.42
25
Oct.18.21
Commercial and Industrial Temperature Ranges
71V65703, 71V65903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99
04/20/00
Pg.5,6
Pg. 7
Pg. 21
05/23/00
07/28/00
11/04/00
12/04/02
12/18/02
10/16/14
Pg. 23
Pg. 5-8
Pg. 7,8
Pg. 23
Pg. 8
Pg. 15
Pg. 1-25
Pg. 5,6,15,16,25
Pg. 1,2,5,6,7,8
Pg. 7
Pg. 1
Pg. 15
Pg. 22
10/18/21
Pg. 1-27
Pg. 5-8
Pg. 5-8 & 23
Pg. 7
Pg. 1 & 23
Pg. 24 & 25
Created new part number and datasheet from 71V657/59 to 71v65703/5903
Add JTAG reset pins to TQFP pin configuration; removed footnote
Add clarification note to Recommended Operating Temperature and Absolute Max Ratings tables
Add note to BGA pin configuration; corrected typo within pinout
InsertTQFP Package Diagram Outline
Add new package offering: 13mm x 15mm, 165 fine pitch ball grid array
Correction on 119 Ball Grid Array Package diagram Outline
Remove JTAG pins from TQFP, BG119 and BQ165 pinouts, refer to IDT71V656xx and
IDT71V658xx device errata sheet
Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout
Update BG119 package diagram dimensions
Add reference note to pin N5 on the BQ165 pinout, reserved for JTAG TRST
Add Izz to DC Electrical Characteristics
Changed datasheet from Preliminary to final release
Added I temp to datasheet
Removed JTAG functionality for current die revision
Corrected pin configuration on the x36, 119 BGA. Switched pins I/O0 and I/OP1.
Added green availability to Features and corrected a typo
DC Electrical Chars Table corrected typos for IDD in the Industrial Temp range for the
8.0ns & 8.5ns speed grades
Removed IDT from and added green and T&R indicators to the ordering information
Added (1) footnote annotation to 75 access speed in the ordering information table
Added the corresponding footnote to the text “71V65703 only”.
Source file updated to reflect previous Corporate Marketing rebranding
Updated footnotes for DNU = Do not use pins
Updated package codes
Pin Configuration 512K x18, BG119, BGG119 - I/O numbering corrected
Updated Industrial temp range and green availability
Added Orderable Part Information tables
6.42
26
Oct.18.21
IMPORTANT NOTICE AND DISCLAIMER
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(Rev.1.0 Mar 2020)
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