7281L15PA8

CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 DESCRIPTION: FEATURES: • • • • • • • • • • • • • • • • IDT7280 IDT7281 IDT7282 IDT7283 IDT7284 IDT7285 The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that load and empty data on a first-in/first-out basis. These devices are functional and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using high-speed CMOS technology. They are designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs Low power consumption — Active: 685 mW (max.) — Power-down: 83 mW (max.) Ultra high speed—12 ns access time Asynchronous and simultaneous read and write Offers optimal combination of data capacity, small foot print and functional flexibility Ideal for bi-directional, width expansion, depth expansion, bus-matching, and data sorting applications Status Flags: Empty, Half-Full, Full Auto-retransmit capability High-performance CMOS technology Space-saving TSSOP Industrial temperature range (–40°°C to +85°°C) is available FUNCTIONAL BLOCK DIAGRAM DATA INPUTS (DA0-DA8) WA WRITE CONTROL RAM ARRAY A 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 WRITE POINTER RSA DATA INPUTS (DB0-DB8) WB WRITE CONTROL WRITE POINTER READ POINTER READ CONTROL READ CONTROL RESET LOGIC FLAG LOGIC XOA/HFA RESET LOGIC FLAG LOGIC EXPANSION LOGIC XIA READ POINTER THREESTATE BUFFERS THREESTATE BUFFERS RA RAM ARRAY B 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 RSB EXPANSION LOGIC FFA EFA DATA OUTPUTS (QA0-QA8) RB FLA/RTA XIB XOB/HFB IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FFB EFB DATA OUTPUTS (QB0-QB8) FLB/RTB 3208 drw 01 NOVEMBER 2017 1 ©2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3208/10 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 PIN CONFIGURATION FFA QA0 QA1 QA2 QA3 QA8 GND RA QA4 QA5 QA6 QA7 XOA/HFA EFA FFB QB0 QB1 QB2 QB3 QB8 GND RB QB4 QB5 QB6 QB7 XOB/HFB EFB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Symbol VTERM XIA DA0 DA1 DA2 DA3 DA8 WA VCC DA4 DA5 DA6 DA7 FLA/RTA RSA XIB DB0 DB1 DB2 DB3 DB8 WB VCC DB4 DB5 DB6 DB7 FLB/RTB RSB TSTG IOUT Rating Terminal Voltage with Respect to GND Storage Temperature DC Output Current Com'l & Ind'l –0.5 to +7.0 Unit V –55 to +125 –50 to +50 °C mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS Symbol VCC GND VIH(1) VIL(2) TA TA 3208 drw 02 Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Commercial Operating Temperature Industrial Min. 4.5 0 2.0 — 0 Typ. 5.0 0 — — — Max. 5.5 0 — 0.8 70 Unit V V V V °C –40 — 85 °C NOTES: 1. For RT/RS/XI input, VIH = 2.6V (commercial). 2. 1.5V undershoots are allowed for 10ns once per cycle. TSSOP (SO56-2, order code: PA) TOP VIEW DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C) Symbol ILI(2) ILO(3) VOH VOL ICC1(4,5) ICC2(4,7) IDT7280L IDT7281L IDT7282L Commercial & Industrial(1) tA = 12, 15 ns Min. Max. –1 1 –10 10 2.4 — — 0.4 — 125(6) — 15 Parameter Input Leakage Current (Any Input) Output Leakage Current Output Logic “1” Voltage IOH = –2mA Output Logic “0” Voltage IOL = 8mA Active Power Supply Current (both FIFOs) Standby Current (R=W=RS=FL/RT=VIH) NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. Measurements with 0.4 ≤ VIN ≤ VCC. 3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs open (IOUT = 0). 5. Tested at f = 20 MHz. 6. Typical ICC1 = 2*[15 + 2*fS + 0.02*CL*fS] (in mA) with VCC = 5V, TA = 25oC, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 7. All Inputs = VCC - 0.2V or GND + 0.2V. AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load TO OUTPUT PIN CAPACITANCE (TA = +25 C, f = 1.0 MHz) Parameter Input Capacitance Output Capacitance Condition VIN = 0V VOUT = 0V Max. 8 8 Unit μA μA V V mA mA GND to 3.0V 5ns 1.5V 1.5V See Figure 1 5V o Symbol CIN COUT IDT7283L IDT7284L IDT7285lL Commercial & Industrial(1) tA = 12, 15 ns Min. Max. –1 — –10 10 2.4 — — 0.4 — 150 — 15 Unit pF pF 680Ω 1.1K 30pF* 3208 drw 03 or equivalent circuit Figure 1. Output Load NOTE: 1. Characterized values, not currently tested. * Includes scope and jig capacitances. 2 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C) Symbol Commercial IDT7280L12 IDT7281L12 IDT7282L12 IDT7283L12 IDT7284L12 IDT7285L12 Min. Max. Parameter Commercial & Industrial(2) IDT7280L15 IDT7281L15 IDT7282L15 IDT7283L15 IDT7284L15 IDT7285L15 Min. Max. Unit tS Shift Frequency — 50 — 40 MHz tRC Read Cycle Time 20 — 25 — ns tA Access Time — 12 — 15 ns tRR Read Recovery Time 8 — 10 — ns tRPW Read Pulse Width(3) 12 — 15 — ns (4) tRLZ Read Pulse Low to Data Bus at Low Z 3 — 3 — ns tWLZ Write Pulse High to Data Bus at Low Z(4,5) 5 — 5 — ns tDV Data Valid from Read Pulse High 5 — 5 — ns tRHZ Read Pulse High to Data Bus at High Z(4) — 12 — 15 ns tWC Write Cycle Time 20 — 25 — ns tWPW Write Pulse Width(3) 12 — 15 — ns tWR Write Recovery Time 8 — 10 — ns tDS Data Set-up Time 9 — 11 — ns tDH Data Hold Time 0 — 0 — ns tRSC Reset Cycle Time 20 — 25 — ns tRS Reset Pulse Width(3) 12 — 15 — ns tRSS Reset Set-up Time(4) 12 — 15 — ns tRSR Reset Recovery Time 8 — 10 — ns tRTC Retransmit Cycle Time 20 — 25 — ns tRT Retransmit Pulse Width(3) 12 — 15 — ns tRTS Retransmit Set-up Time(4) 12 — 15 — ns tRTR Retransmit Recovery Time 8 — 10 — ns tEFL Reset to Empty Flag Low — 12 — 25 ns tHFH,FFH Reset to Half-Full and Full Flag High — 17 — 25 ns tRTF Retransmit Low to Flags Valid — 20 — 25 ns tREF Read Low to Empty Flag Low — 12 — 15 ns tRFF Read High to Full Flag High — 14 — 15 ns tRPE Read Pulse Width after EF High 12 — 15 — ns tWEF Write High to Empty Flag High — 12 — 15 ns tWFF Write Low to Full Flag Low — 14 — 15 ns tWHF Write Low to Half-Full Flag Low — 17 — 25 ns tRHF Read High to Half-Full Flag High — 17 — 25 ns tWPF Write Pulse Width after FF High 12 — 15 — ns tXOL Read/Write to XO Low — 12 — 15 ns tXOH Read/Write to XO High — 12 — 15 ns tXI XI Pulse Width(3) 12 — 15 — ns tXIR XI Recovery Time 8 — 10 — ns tXIS XI Set-up Time 8 — 10 — ns NOTES: 1. Timings referenced as in AC Test Conditions. 2. Industrial temperature range product for the 15ns speed grade is available as a standard device. 3. Pulse widths less than minimum value are not allowed. 4. Values guaranteed by design, not currently tested. 5. Only applies to read data flow-through mode. 3 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 SIGNAL DESCRIPTIONS COMMERCIAL TEMPERATURE RANGE Device Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by grounding the Expansion In (XI). These devices can be made to retransmit data when the Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be in the HIGH state during retransmit. This feature is useful when less than 256/512/1,024/2,048/4,096/8,192 writes are performed between resets. The retransmit feature is not compatible with the Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on the relative locations of the read and write pointers. INPUTS: DATA IN (D0 – D8) Data inputs for 9-bit wide data. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power up before a write operation can take place. Both the Read Enable (R) and Write Enable (W) inputs must be in the HIGH state during the window shown in Figure 2, (i.e., tRSS before the rising edge of RS) and should not change until tRSR after the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after Reset (RS). EXPANSION IN (XI) This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate an operation in the single device mode. Expansion In (XI) is connected to Expansion Out (XO) of the previous device in the Depth Expansion or Daisy Chain Mode. WRITE ENABLE (W) A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of the Write Enable (W). Data is stored in the RAM array sequentially and independently of any on-going read operation. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further write operations. Upon the completion of a valid read operation, the Full Flag (FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO is full, the internal write pointer is blocked from W, so external changes in W will not affect the FIFO when it is full. OUTPUTS: FULL FLAG (FF) The Full Flag (FF) will go LOW, inhibiting further write operation, when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go LOW after 256 writes for IDT7280, 512 writes for the IDT7281, 1,024 writes for the IDT7282, 2,048 writes for the IDT7283, 4,096 writes for the IDT7284 and 8,192 writes for the IDT7285. EMPTY FLAG (EF) The Empty Flag (EF) will go LOW, inhibiting further read operations, when the read pointer is equal to the write pointer, indicating that the device is empty. EXPANSION OUT/HALF-FULL FLAG (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is grounded, this output acts as an indication of a half-full memory. After half of the memory is filled and at the falling edge of the next write operation, the Half-Full Flag (HF) will be set LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset by using rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previous device reaches the last location of memory. READ ENABLE (R) A read cycle is initiated on the falling edge of the Read Enable (R) provided the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis, independent of any ongoing write operations. After Read Enable (R) goes HIGH, the Data Outputs (Q0 – Q8) will return to a high impedance condition until the next Read operation. When all data has been read from the FIFO, the Empty Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read operations with the data outputs remaining in a high impedance state. Once a valid write operation has been accomplished, the Empty Flag (EF) will go HIGH after tWEF and a valid Read can then begin. When the FIFO is empty, the internal read pointer is blocked from R so external changes in R will not affect the FIFO when it is empty. DATA OUTPUTS (Q0 – Q8) Data outputs for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a HIGH state. FIRST LOAD/RETRANSMIT (FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is grounded to indicate that it is the first loaded (see Operating Modes). In the Single 4 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL TEMPERATURE RANGE tRSC tRS RS tRSS tRSR W tRSS R tEFL EF tHFH , tFFH HF, FF 3208 drw 04 NOTES: 1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS. Figure 2. Reset t RC t RPW tRR tA tA R t DV t RLZ Q0-Q8 t RHZ DATA OUT VALID t WPW t WC DATA OUT VALID t WR W t DS D0-D8 t DH DATA IN VALID DATA IN VALID 3208 drw 05 Figure 3. Asynchronous Write and Read Operation LAST WRITE IGNORED WRITE FIRST READ ADDITIONAL READS FIRST WRITE R W tWFF t RFF FF 3208 drw 06 Figure 4. Full Flag From Last Write to First Read 5 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 LAST READ IGNORED READ COMMERCIAL TEMPERATURE RANGE FIRST WRITE ADDITIONAL WRITES FIRST READ W R t WEF t REF EF tA DATA OUT VALID VALID 3208 drw 07 Figure 5. Empty Flag From Last Read to First Write tRTC tRT RT tRTS t RTR W,R t RTF HF, EF, FF FLAG VALID 3208 drw 08 Figure 6. Retransmit W tWEF EF tRPE R 3208 drw 09 Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse R t RFF FF t WPF W 3208 drw 10 Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse 6 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL TEMPERATURE RANGE W t RHF R t WHF HF HALF-FULL OR LESS HALF-FULL OR LESS MORE THAN HALF-FULL 3208 drw 11 Figure 9. Half-Full Flag Timing WRITE TO LAST PHYSICAL LOCATION W READ FROM LAST PHYSICAL LOCATION R tXOL tXOH tXOH tXOL 3208 drw 12 XO Figure 10. Expansion Out t XI tXIR XI t XIS W WRITE TO FIRST PHYSICAL LOCATION tXIS R READ FROM FIRST PHYSICAL LOCATION 3208 drw 13 Figure 11. Expansion In OPERATING MODES: 14 demonstrates a four-FIFO Depth Expansion using two IDT7280/7281/ 7282/7283/7284/7285s. Any depth can be attained by adding additional IDT7280/7281/7282/7283/7284/7285s. These FIFOs operate in the Depth Expansion mode when the following conditions are met: Care must be taken to assure that the appropriate flag is monitored by each system (i.e. FF is monitored on the device where W is used; EF is monitored on the device where R is used). 1. The first FIFO must be designated by grounding the First Load (FL) control input. 2. All other FIFOs must have FL in the HIGH state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (XI) pin of the next device. See Figure 14. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all must be set to generate the correct composite FF or EF). See Figure 14. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion Mode. SINGLE DEVICE MODE A single IDT7280/7281/7282/7283/7284/7285 may be used when the application requirements are for 256/512/1,024/2,048/4,096/8,192 words or less. These FIFOs are in a Single Device Configuration when the Expansion In (XI) control input is grounded (see Figure 12). DEPTH EXPANSION These devices can easily be adapted to applications when the requirements are for greater than 256/512/1,024/2,048/4,096/8,192 words. Figure 7 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 USAGE MODES: the FIFO permits a reading of a single word after writing one word of data into an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising edge of W, called the first write edge, and it remains on the bus until the R line is raised from LOW-to-HIGH, after which the bus would go into a three-state mode after tRHZ ns. The EF line would have a pulse showing temporary deassertion and then would be asserted. In the write flow-through mode (Figure 18), the FIFO permits the writing of a single word of data immediately after reading one word of data from a full FIFO. The R line causes the FF to be deasserted but the W line being LOW causes it to be asserted again in anticipation of a new data word. On the rising edge of W, the new word is loaded in the FIFO. The W line must be toggled when FF is not asserted to write new data in the FIFO and to increment the write pointer. WIDTH EXPANSION Word width may be increased simply by connecting the corresponding input control signals of multiple FIFOs. Status flags (EF, FF and HF) can be detected from any one FIFO. Figure 13 demonstrates an 18-bit word width by using the two FIFOs contained in the IDT7280/7281/7282/7283/7284/7285s. Any word width can be attained by adding FIFOs (Figure 13). BIDIRECTIONAL OPERATION Applications which require data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT7280/7281/7282/7283/7384/7285s as shown in Figure 16. Both Depth Expansion and Width Expansion may be used in this mode. COMPOUND EXPANSION The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 15). DATA FLOW-THROUGH Two types of flow-through modes are permitted, a read flow-through and write flow-through mode. For the read flow-through mode (Figure 17), (HALF-FULL FLAG) WRITE (W) (HF) FIFO A or B IDT 7280 7281 7282 7283 7284 7285 9 DATA IN (D) FULL FLAG (FF) RESET (RS) COMMERCIAL TEMPERATURE RANGE READ (R) 9 DATA OUT (Q) EMPTY FLAG (EF) RETRANSMIT (RT) 3208 drw 14 EXPANSION IN (XI) Figure 12. Block Diagram of One 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 FIFO Used in Single Device Mode 9 18 DATA IN (D) HFA HFB FIFO A FIFO B 9 WRITE (W) READ (R) EMPTY FLAG (EFB) FULL FLAG (FFA) RESET (RS) RETRANSMIT (RT) 9 XIA 7280/7281/7282/ 9 7283/7284/7285 XIB 18 DATA OUT (Q) 3208 drw 15 Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 FIFO Memory Used in Width Expansion Mode 8 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL TEMPERATURE RANGE TABLE 1 — RESET AND RETRANSMIT Single Device Configuration/Width Expansion Mode RS Inputs RT XI Reset Retransmit 0 1 X 0 0 0 Location Zero Location Zero Location Zero Unchanged 0 X 1 X 1 X Read/Write 1 1 0 Increment(1) Increment(1) X X X Mode Read Pointer Internal Status Write Pointer EF Outputs FF HF NOTE: 1. Pointer will increment if flag is High. TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE Depth Expansion/Compound Expansion Mode Mode Reset First Device Reset All Other Devices Read/Write RS Inputs FL XI Read Pointer 0 0 1 0 1 X (1) (1) (1) Location Zero Location Zero X Internal Status Write Pointer Location Zero Location Zero X Outputs EF FF 0 0 X 1 1 X NOTE: 1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expansion Input, HF = Half-Full Flag Output 10 XOA EFA FFA FIFO A FLA XIA 7280/7281/ 7282/7283/ 7284/7285 XOB W D 9 9 R EFB FFB FIFO B 9 FLB Q V CC XIB XOA FFA FULL EFA EMPTY FIFO A 9 FLA 7280/7281/ 7282/7283/ 7284/7285 FFB 9 XIA XOB EFB FIFO B RSA FLB XIB 3208 drw 16 Figure 14. Block Diagram of 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 FIFO Memory (Depth Expansion) 9 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Q0-Q8 Q(N-8)-QN Q9-Q17 Q9-Q17 Q0-Q8 R, W, RS COMMERCIAL TEMPERATURE RANGE IDT7280/7281/ 7282/7283/ 7284/7285 DEPTH EXPANSION BLOCK Q(N-8)-QN IDT7280/7281/ 7282/7283/ 7284/7285 DEPTH EXPANSION BLOCK D0-D8 IDT7280/7281/ 7282/7283/ 7284/7285 DEPTH EXPANSION BLOCK D(N-8)-DN D9-D17 D0-DN D18-DN D9-DN D(N-8)-DN 3208 drw 17 NOTES: 1. For depth expansion block see section on Depth Expansion and Figure 14. 2. For Flag detection see section on Width Expansion and Figure 13. Figure 15. Compound FIFO Expansion WA FFA D A0-8 SIDE 1 FIFO IDTA 7201A QA0-8 IDT 7280 7281 7282 7283 7284 7285 QB0-8 RB HF B EFB RA EFA HFA SIDE 2 D B0-8 FIFO B WB FFB 3208 drw 18 Figure 16. Bidirectional FIFO Mode 10 JUNE 29, 2012 IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 COMMERCIAL TEMPERATURE RANGE DATA IN W t RPE R EF t WLZ t WEF tA t REF DATA OUT DATA OUT VALID 3208 drw 19 Figure 17. Read Data Flow-Through Mode R t WPF W tRFF FF tDH t WFF DATA DATA IN tA DATA OUT IN VALID t DS DATA OUT VALID 3208 drw 20 Figure 18. Write Data Flow-Through Mode 11 JUNE 29, 2012 ORDERING INFORMATION XXXX X XXX X Device Type Power Speed Package X X X Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G(2) Green PA Thin Shrink SOIC (TSSOP, SO56-2) 12 15 Commercial Only Commercial and Industrial L Low Power 7280 7281 7282 7283 7284 7285 256 x 9 ⎯ CMOS Dual Asynchronous FIFO 512 x 9 ⎯ CMOS Dual Asynchronous FIFO 1,024 x 9 ⎯ CMOS Dual Asynchronous FIFO 2,048 x 9 ⎯ CMOS Dual Asynchronous FIFO 4,096 x 9 ⎯ CMOS Dual Asynchronous FIFO 8,192 x 9 ⎯ CMOS Dual Asynchronous FIFO Access Time (tA) Speed in Nanoseconds 3208 drw 21 NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. 2. Green parts are available. For specific speeds and packages contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 DATASHEET DOCUMENT HISTORY 07/13/2001 01/13/2009 06/29/2012 11/27/2017 pgs. 2, 3 and 12. pg. 12. pgs. 1 and 12. Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 12 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com