72V2103L6PF

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ NARROW BUS FIFO 131,072 x 18/262,144 x 9 IDT72V2103 262,144 x 18/524,288 x 9 IDT72V2113 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • • • • • • • • • • • • • Choose among the following memory organizations: IDT72V2103 ⎯ 131,072 x 18/262,144 x 9 IDT72V2113 ⎯ 262,144 x 18/524,288 x 9 Functionally compatible with the IDT72V255LA/72V265LA and IDT72V275/72V285 SuperSync FIFOs Up to 166 MHz Operation of the Clocks User selectable Asynchronous read and/or write ports (BGA Only) 6 ns read/write cycle time (4.0 ns access time) User selectable input and output port bus-sizing - x9 in to x9 out - x9 in to x18 out - x18 in to x9 out - x18 in to x18 out Big-Endian/Little-Endian user selectable byte representation 5V tolerant inputs Fixed, low first word latency Zero latency retransmit Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings FUNCTIONAL BLOCK DIAGRAM *Available on the BGA package only. • • • • • • • • • • • • • • Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state Easily expandable in depth and width JTAG port, provided for Boundary Scan function (BGA Only) Independent Read and Write Clocks (permit reading and writing simultaneously) Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball Grid Array (BGA) (with additional features) Pin compatible to the SuperSync II (IDT72V223/72V233/72V243/ 72V253/72V263/72V273/72V283/72V293) family High-performance submicron CMOS technology Industrial temperature range (–40°°C to +85°°C) is available Green parts available, see ordering information D0 -Dn (x9 or x18) INPUT REGISTER *ASYW LD SEN * WEN WCLK/WR OFFSET REGISTER FF/IR PAF EF/OR PAE HF FWFT/SI PFM FSEL0 FSEL1 FLAG LOGIC WRITE CONTROL LOGIC RAM ARRAY 131,072 x 18 or 262,144 x 9 262,144 x 18 or 524,288 x 9 WRITE POINTER BE IP CONTROL LOGIC IW OW BUS CONFIGURATION MRS PRS RESET LOGIC TCK *TRST * TMS **TDI *TDO JTAG CONTROL (BOUNDARY SCAN) READ POINTER OUTPUT REGISTER READ CONTROL LOGIC RT RM ASYR * * RCLK/RD REN * 6119 drw01 OE Q0 -Qn (x9 or x18) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 © 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. MARCH 2018 DSC-6119/17 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 DESCRIPTION: COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES • The period required by the retransmit operation is now fixed and short. • The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is now fixed and short. (The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated on this SuperSync family.) • Asynchronous/Synchronous translation on the read or write ports. • High density offerings up to 4 Mbit. Bus-Matching SuperSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. The IDT72V2103/72V2113 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls and a flexible Bus-Matching x9/x18 data flow. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • Flexible x9/x18 Bus-Matching on both read and write ports. • The limitation of the frequency of one clock input with respect to the other has been removed. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. WCLK PRS MRS LD FWFT/SI FF/IR PAF OW FSEL0 HF FSEL1 BE IP VCC PAE PFM EF/OR RM RCLK REN PIN CONFIGURATIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 INDEX 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RT OE VCC Q17 Q16 GND GND Q15 Q14 VCC Q13 Q12 GND Q11 GND Q10 VCC Q9 Q8 Q7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 WEN SEN DNC(1) VCC DNC(1) IW GND D17 VCC D16 D15 D14 D13 GND D12 D11 D10 D9 D8 VCC D7 D6 GND D5 D4 D3 D2 D1 D0 GND Q0 Q1 GND Q2 Q3 VCC Q4 Q5 GND Q6 6119 drw02 NOTE: 1. DNC = Do Not Connect. TQFP (PN80, order code: PF) TOP VIEW 2 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 DESCRIPTION (CONTINUED) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, and the OE input used to provide three-state control of the outputs, Qn. The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW) and Output Width (OW) during the Master Reset cycle. The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW). The output port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. PIN CONFIGURATIONS (CONTINUED) A1 BALL PAD CORNER A WCLK PRS LD PAF FSEL0 BE ASYR PFM RM REN WEN MRS FWFT/SI OW HF FSEL1 IP PAE EF/OR RCLK ASYW SEN FF/IR VCC VCC VCC VCC VCC RT OE D17 IW VCC GND GND GND GND VCC Q16 Q17 D16 D15 VCC GND GND GND GND VCC Q14 Q15 D13 D14 VCC GND GND GND GND VCC Q13 Q12 D11 D12 VCC GND GND GND GND VCC Q11 Q10 D8 D9 D10 VCC VCC VCC VCC Q1 Q9 Q8 D6 D7 D2 D0 TMS TCK TDO Q2 Q4 Q7 D5 D4 D3 D1 TRST TDI Q0 Q3 Q5 Q6 3 4 5 6 7 8 9 B C D E F G H J K 1 2 10 6119 drw02b BGA: 1mm pitch, 11mm x 11mm (BC100, order code: BC) TOP VIEW 3 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 DESCRIPTION (CONTINUED) For serial programming, SEN together with LD on each rising edge of WCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected. During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE and PAF flags. If asynchronous PAE/PAF configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW- not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins. PARTIAL RESET (PRS) MASTER RESET (MRS) READ CLOCK (RCLK/RD*) WRITE CLOCK (WCLK/WR*) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE (OE) LOAD (LD) (x9 or x18) DATA IN (D0 - Dn) SERIAL ENABLE(SEN) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT 72V2103 72V2113 (x9 or x18) DATA OUT (Q0 - Qn) RETRANSMIT (RT) EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE ALMOST-EMPTY (PAE) FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) HALF-FULL FLAG (HF) FULL FLAG/INPUT READY (FF/IR) BIG-ENDIAN/LITTLE-ENDIAN (BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) PROGRAMMABLE ALMOST-FULL (PAF) INPUT WIDTH (IW) OUTPUT WIDTH (OW) Figure 1. Single Device Configuration Signal Flow Diagram 4 6119 drw03 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the long word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin. The Interspersed/Non-Interspersed Parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit position D8 during the parallel programming of the flag offsets. If Non-Interspersed Parity mode is selected, then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode is selected during Master Reset by the state of the IP input pin. This mode is relevant only when the input width is set to x18 mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V2103/72V2113 are fabricated using IDT’s high speed submicron CMOS technology. to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin. The Retransmit function allows data to be reread from the FIFO more than once. A LOW on the RT input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. A zero-latency retransmit timing mode can be selected using the Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zerolatency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero-latency retransmit operation is selected the first data word to be retransmitted will be placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being LOW. Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer to Figure 13 and 14 for Retransmit Timing with zero-latency. A Big-Endian/Little-Endian data word format is provided. This function is useful when data is written into the FIFO in long word format (x18) and read out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then the most significant byte (word) of the long word written into the FIFO will be read TABLE 1 — BUS-MATCHING CONFIGURATION MODES IW OW Write Port Width Read Port Width L L x18 x18 L H x18 x9 H L x9 x18 H H x9 x9 5 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION (TQFP & BGA PACKAGES) Symbol Name (1) BE *Big-Endian/ Little-Endian D0–D17 Data Inputs I/O Description I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will select Little-Endian format. I Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D0–D17 are used. When in 9-bit mode, D0–D8 are used and the unused inputs, D9–D17, should be tied LOW. EF/OR Empty Flag/ O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In Output Ready FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the Input Ready FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. FSEL0(1) Flag Select Bit 0 I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable flags PAE and PAF. There are up to eight possible settings available. (1) FSEL1 Flag Select Bit 1 I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable flags PAE and PAF. There are up to eight possible settings available. FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions Through/Serial In as a serial input for loading offset registers. HF Half-Full Flag O HF indicates whether the FIFO memory is more or less than half-full. (1) IP Interspersed Parity I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. (1) IW Input Width I This pin selects the bus width of the write port. During Master Reset, when IW is LOW, the write port will be configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width. LD Load I This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the offset registers. MRS Master Reset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes. OE Output Enable I OE controls the output impedance of Qn. (1) OW Output Width I This pin selects the bus width of the read port. During Master Reset, when OW is LOW, the read port willbe configured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width. PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset Almost-Empty Flag register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n. PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the Almost-Full Flag Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m. (1) PFM Programmable I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM Flag Mode will select Synchronous Programmable flag timing mode. PRS Partial Reset I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. Q0–Q17 Data Outputs O Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are used, and the unused outputs, Q9-Q17 should not be connected. Outputs are not 5V tolerant regardless of the state of OE. REN RCLK/ RD Read Enable Read Clock/ Read Strobe I I REN enables RCLK for reading data from the FIFO memory and offset registers. If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW. Asynchronous operation of the RCLK/RD input is only available in the BGA package. NOTE: 1. Inputs should not change state after Master Reset. 6 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES) Symbol RM(1) RT Name Retransmit Timing Mode Retransmit SEN WCLK/ WR Serial Enable Write Clock/ Write Strobe WEN V CC Write Enable +3.3V Supply I/O Description I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select normal latency mode. I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. RT is useful to reread data from the first physical location of the FIFO. I SEN enables serial loading of programmable flag offsets. I If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). Asynchronous operation of the WCLK/WR input is only available in the BGA package. I I WEN enables WCLK for writing data into the FIFO memory and offset registers. These are VCC supply inputs and must be connected to the 3.3V supply rail. NOTE: 1. Inputs should not change state after Master Reset. PIN DESCRIPTION (BGA PACKAGE ONLY) Symbol ASYR(1) ASYW(1) Name Asynchronous Read Port Asynchronous Write Port I/O Description I A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. I A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW will select Asynchronous operation. TCK(2) JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(2) JTAG Test Data Input I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(2) JTAG Test Data Output O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. TMS(2) JTAG Mode I TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST(2) JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller will automatically reset upon power-up. If the JTAG function is not used then this signal should to be tied to GND. NOTES: 1. Inputs should not change state after Master Reset. 2. These pins are for the JTAG port. Please refer to pages 41-45 and Figures 31-33. 7 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 ABSOLUTE MAXIMUM RATINGS Symbol VTERM (2) TSTG IOUT Rating Com'l & Ind'l Unit Terminal Voltage with respect to GND –0.5 to +4.5 V Storage Temperature –55 to +125 DC Output Current –50 to +50 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RECOMMENDED DC OPERATING CONDITIONS Symbol °C mA NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminal only. Min. Typ. Max. Unit VCC(1) Supply Voltage (Com'l & Ind'l) Parameter 3.15 3.3 3.45 V GND Supply Voltage (Com'l & Ind'l) 0 0 0 V (2) VIH Input High Voltage (Com'l & Ind'l) 2.0 — 5.5 V VIL(3) Input Low Voltage (Com'l & Ind'l) — — 0.8 V TA Operating Temperature Commercial 0 — +70 °C TA Operating Temperature Industrial -40 — +85 °C NOTES: 1. VCC=3.3V ± 0.15V, JEDEC JESD8-A compliant. 2. Outputs are not 5V tolerant. 3. 1.5V undershoots are allowed for 10ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant) IDT72V2103L IDT72V2113L Commercial and Industrial(1) tCLK = 6, 7-5, 10, 15 ns Symbol ILI ILO(3) VOH VOL ICC1(4,5,6) ICC1(4,5,6) ICC2(4,7) (2) Parameter Input Leakage Current Output Leakage Current Output Logic “1” Voltage, IOH = –2 mA Output Logic “0” Voltage, IOL = 8 mA Active Power Supply Current (x9 Input to x9 Output) Active Power Supply Current (x18 Input to x18 Output) Standby Current Min. Max. Unit –1 –10 2.4 — — — — 1 10 — 0.4 30 35 15 μA μA V V mA mA mA NOTES: 1. Industrial temperature range product for the 7-5ns and 10ns speed grades are available as a standard device. All other speed grades are available by special order. 2. Measurements with 0.4 ≤ VIN ≤ VCC. 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs open (IOUT = 0). 5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz. 6. For x 18 bus widths, typical ICC1 = 5 + fS + 0.002*CL*fS (in mA); for x 9 bus widths, typical ICC1 = 5 + 0.775*fS + 0.002*CL*fS (in mA). These equations are valid under the following conditions: VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN(2) COUT(1,2) Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V Max. 10 Unit pF VOUT = 0V 10 pF NOTES: 1. With output deselected, (OE ≥ VIH). 2. Characterized values, not currently tested. 8 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant) Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tLDS tLDH tRS tRSS tRSR tRSF tRTS tOLZ tOE tOHZ tWFF tREF tPAFA tPAFS tPAEA tPAES tHF tSKEW1 tSKEW2 Parameter Clock Cycle Frequency Data Access Time(5) Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Load Setup Time Load Hold Time Reset Pulse Width(3) Reset Setup Time Reset Recovery Time Reset to Flag and Output Time Retransmit Setup Time Output Enable to Output in Low Z(4) Output Enable to Output Valid(5) Output Enable to Output in High Z(4,5) Write Clock to FF or IR Read Clock to EF or OR Clock to Asynchronous Programmable Almost-Full Flag Write Clock to Synchronous Programmable Almost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag Read Clock to Synchronous Programmable Almost-Empty Flag Clock to HF Skew time between RCLK and WCLK for EF/OR and FF/IR Skew time between RCLK and WCLK for PAE and PAF Commercial BGA & TQFP Com’l & Ind’l(2) BGA & TQFP Com’l & Ind’l(2) TQFP Only Commercial TQFP Only IDT72V2103L6 IDT72V2113L6 Min. Max. — 166 1 4 6 — 2.7 — 2.7 — 2 — 0.5 — 2 — 0.5 — 3 — 0.5 — 10 — 15 — 10 — — 15 3 — 0 — 1 4 1 4 — 4 — 4 — 10 — 4 — 10 — 4 — 10 4 — 5 — IDT72V2103L7-5 IDT72V2113L7-5 Min. Max. — 133.3 1(5) 5 7.5 — 3.5 — 3.5 — 2.5 — 0.5 — 2.5 — 0.5 — 3.5 — 0.5 — 10 — 15 — 10 — — 15 3.5 — 0 — 1(5) 6 1(5) 6 — 5 — 5 — 12.5 — 5 — 12.5 — 5 — 12.5 5 — 7 — IDT72V2103L10 IDT72V2113L10 Min. Max. — 100 1(5) 6.5 10 — 4.5 — 4.5 — 3.5 — 0.5 — 3.5 — 0.5 — 3.5 — 0.5 — 10 — 15 — 10 — — 15 3.5 — 0 — 1(5) 6 1(5) 6 — 6.5 — 6.5 — 16 — 6.5 — 16 — 6.5 — 16 7 — 10 — IDT72V2103L15 IDT72V2113L15 Min. Max. — 66.7 1(5) 10 15 — 6 — 6 — 4 — 1 — 4 — 1 — 4 — 1 — 15 — 15 — 15 — — 15 4 — 0 — 1(5) 8 1(5) 8 — 10 — 10 — 20 — 10 — 20 — 10 — 20 9 — 14 — NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for the 7-5ns and 10ns are available as a standard device. All other speed grades are available by special order. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. 5. TQFP package only: for speed grades 7-5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns. 9 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS(1) — ASYNCHRONOUS TIMING (Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant) Symbol fA(4) tAA(4) tCYC(4) tCYH(4) tCYL(4) tRPE(4) tFFA(4) tEFA(4) tPAFA(4) tPAEA(4) Parameter Cycle Frequency (Asynchronous mode) Data Access Time Cycle Time Cycle HIGH Time Cycle LOW Time Read Pulse after EF HIGH Clock to Asynchronous FF Clock to Asynchronous EF Clock to Asynchronous Programmable Almost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. Parameters apply to the BGA package only. 10 Commercial Com’l & Ind’l IDT72V2103L6 IDT72V2113L6 Min. Max. — 100 0.6 8 10 — 4.5 — 4.5 — 8 — — 8 — 8 — 8 — 8 IDT72V2103L7-5 IDT72V2113L7-5 Min. Max. — 83 0.6 10 12 — 5 — 5 — 10 — — 10 — 10 — 10 — 10 Unit MHz ns ns ns ns ns ns ns ns ns BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES AC TEST LOADS - 6ns, 7.5ns Speed Grades AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for tCLK = 10ns, 15 ns Output Load for tCLK = 6ns, 7.5ns GND to 3.0V 3ns(1) 1.5V 1.5V See Figure 2a See Figure 2b & 2c 1.5V 50Ω Z0 = 50Ω I/O 6119 drw04a NOTE: 1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns. Figure 2b. AC Test Load AC TEST LOADS - 10ns, 15ns Speed Grades 6 tCD (Typical, ns) 5 3.3V 330Ω 4 3 2 1 D.U.T. 20 30 50 30pF* 510Ω 80 100 Capacitance (pF) Figure 2c. Lumped Capacitive Load, Typical Derating 6119 drw04 Figure 2a. Output Load * Includes jig and scope capacitances. OUTPUT ENABLE & DISABLE TIMING Output Enable Output Disable VIH OE VIL tOE & tOLZ Output VCC Normally 2 LOW Output Normally VCC 2 HIGH 200 6119 drw04b tOHZ VCC 2 100mV 100mV VOL VOH 100mV 100mV VCC 2 6119 drw04c NOTE: 1. REN is HIGH. 11 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 FUNCTIONAL DESCRIPTION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent read operations will cause PAF and HF to go HIGH at the conditions described in Table 3. If further read operations occur, without write operations, PAE will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, the EF will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in IDT Standard mode, the EF and FF outputs are double register-buffered outputs. Relevant timing diagrams for IDT Standard mode can be found in Figure 7, 8 and 11. TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V2103/72V2113 support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the state of the FWFT/SI input. If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. Various signals, both input and output signals operate differently depending on which timing mode is in effect. FIRST WORD FALL THROUGH MODE (FWFT) In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 4. To write data into the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go HIGH after n+2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If one continued to write data into the FIFO, and we assumed no read operations were taking place, the HF would toggle to LOW once the (D/2 + 2) words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D/2 + 2) = the 65,538th word for the IDT72V2103 and 131,074th word for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, (D/2 + 2) = the 131,074th word for the IDT72V2103 and 262,146th word for the IDT72V2113. Continuing to write data into the FIFO will cause the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (131,073-m) writes for the IDT72V2103 and (262,145-m) writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (262,145-m) writes for the IDT72V2103 and (524,289-m) writes for the IDT72V2113. The offset m is the full offset value. The default setting for these values are stated in the footnote of Table 2. When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations. If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 131,073 writes for the IDT72V2103 and 262,145 writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 writes for the IDT72V2103 and 524,289 writes for the IDT72V2113, respectively. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. If the FIFO is full, the first read operation will cause the IR flag to go LOW. Subsequent read operations will cause the PAF and HF to go HIGH at the conditions described in Table 4. If further read operations occur, without write operations, the PAE will go LOW when there are n+1 words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered. Relevant timing diagrams for FWFT mode can be found in Figure 9, 10 and 12. IDT STANDARD MODE In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full flag (HF) would toggle to LOW once (D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width is selected, (D/2 + 1) = the 65,537th word for the IDT72V2103 and 131,073rd word for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, (D/2 + 1) = the 131,073rd word for the IDT72V2103 and 262,145th word for the IDT72V2113. Continuing to write data into the FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (131,072-m) writes for the IDT72V2103 and (262,144-m) writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (262,144-m) writes for the IDT72V2103 and (524,288-m) writes for the IDT72V2113. The offset “m” is the full offset value. The default setting for these values are stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading. When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 131,072 writes for the IDT72V2103 and 262,144 writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 writes for the IDT72V2103 and 524,288 writes for the IDT72V2113, respectively. 12 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72V2103/ 72V2113 has internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 2. Offset values can also be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the LD (Load) pin. During Master Reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A HIGH on LD during Master Reset selects serial loading of offset values. A LOW on LD during Master Reset selects parallel loading of offset values. In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Offset values can be read via the parallel output port Q0-Qn, regardless of the programming mode selected (serial or parallel). It is not possible to read the offset values in serial fashion. Figure 3, Programmable Flag Offset Programming Sequence, summaries the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows. The offset registers may be programmed (and reprogrammed) any time after Master Reset, regardless of whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D-1. SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION The IDT72V2103/72V2113 can be configured during the Master Reset cycle with either synchronous or asynchronous timing for PAF and PAE flags by use of the PFM pin. If synchronous PAF/PAE configuration is selected (PFM, HIGH during MRS), the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK only and not WCLK. For detail timing diagrams, see Figure 18 for synchronous PAF timing and Figure 19 for synchronous PAE timing. If asynchronous PAF/PAE configuration is selected (PFM, LOW during MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 20 for asynchronous PAF timing and Figure 21 for asynchronous PAE timing. TABLE 2 — DEFAULT PROGRAMMABLE FLAG OFFSETS IDT72V2103, IDT72V2113 LD L L L H H H H FSEL0 L H H L L H H FSEL1 H L H H L L H Offsets n,m 16,383 8,191 4,095 2,047 1,023 511 255 L L L 127 LD FSEL0 FSEL1 Program Mode H L X X X X Serial(3) Parallel(4) COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES NOTES: 1. n = empty offset for PAE. 2. m = full offset for PAF. 3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1. 4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1. 13 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE IW = OW = x9 IW ≠ OW or IW = OW = x18 IDT72V2103 IDT72V2103 IDT72V2113 0 0 1 to n 1 to n Number of Words in FIFO IDT72V2113 FF PAF HF PAE EF 0 H H H L L 1 to n H H H L H H H H H H (n+1) to 65,536 (n+1) to 131,072 (n+1) to 262,144 65,537 to (131,072-(m+1)) 131,073 to (262,144-(m+1)) 262,145 to (524,288-(m+1)) H H L H H (524,288-m) to 524,287 H L L H H 524,288 L L L H H (131,072-m) to 131,071 (262,144-m) to 262,143 131,072 262,144 NOTE: 1. See Table 2 for values for n, m. TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE IW = OW = x9 IW ≠ OW or IW = OW = x18 Number of Words in FIFO(2) IDT72V2103 IDT72V2103 IDT72V2113 0 0 IDT72V2113 IR PAF HF PAE OR 0 L H H L H 1 to n+1 1 to n+1 1 to n+1 L H H L L (n+2) to 65,537 (n+2) to 131,073 (n+2) to 262,145 L H H H L 65,538 to (131,073-(m+1)) 131,074 to (262,145-(m+1)) 262,146 to (524,289-(m+1)) L H L H L L L L H L H L L H (131,073-m) to 131,072 131,073 NOTE: 1. See Table 2 for values for n, m. 2. Number of Words in FIFO = FIFO Depth + Output Register (524,289-m) to 524,288 (262,145-m) to 262,144 262,145 524,289 L 4666 drw05 14 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 1st Parallel Offset Write/Read Cycle D/Q8 D/Q0 EMPTY OFFSET REGISTER 8 7 6 5 4 1st Parallel Offset Write/Read Cycle Data Inputs/Outputs D/Q17 D/Q16 3 2 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 1 D/Q8 D/Q8 D/Q0 14 13 12 # of Bits Used 2nd Parallel Offset Write/Read Cycle Data Inputs/Outputs EMPTY OFFSET (MSB) REGISTER D/Q17 D/Q16 EMPTY OFFSET REGISTER 15 D/Q0 EMPTY OFFSET (LSB) REGISTER 2nd Parallel Offset Write/Read Cycle 16 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 11 10 9 Non-Interspersed Parity Interspersed Parity D/Q0 18 17 18 17 3rd Parallel Offset Write/Read Cycle D/Q8 D/Q0 EMPTY OFFSET REGISTER 3rd Parallel Offset Write/Read Cycle Data Inputs/Outputs FULL OFFSET (LSB) REGISTER D/Q17 D/Q16 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 8 7 6 5 4 3 16 15 14 13 12 11 10 9 4th Parallel Offset Write/Read Cycle D/Q8 D/Q0 D/Q0 2 1 2 1 D/Q8 FULL OFFSET REGISTER 4th Parallel Offset Write/Read Cycle 8 7 6 5 4 3 2 1 D/Q17 D/Q16 Data Inputs/Outputs FULL OFFSET (MSB) REGISTER 4666 drw 06 5th Parallel Offset Write/Read Cycle D/Q8 D/Q0 D/Q0 18 17 18 17 FULL OFFSET REGISTER 16 15 14 13 12 11 10 IDT72V2103/72V2113⎯ x18 Bus Width 9 6119 drw 06 x9 to x9 Mode 6th Parallel Offset Write/Read Cycle D/Q8 # of Bits Used: D/Q0 18 bits for the IDT72V2103 19 bits for the IDT72V2113 Note: All unused bits of the LSB & MSB are don’t care FULL OFFSET REGISTER 19 18 17 All Other Modes IDT72V2103/72V2113⎯ x9 Bus Width # of Bits Used: 17 bits for the IDT72V2103 18 bits for the IDT72V2113 Note: All unused bits of the LSB & MSB are don’t care Figure 3. Programmable Flag Offset Programming Sequence 15 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 LD WEN REN SEN WCLK 0 0 1 1 0 1 0 1 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V2103 IDT72V2113 RCLK Parallel write to registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) X Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) X x9 to x9 Mode 0 1 1 0 X X 1 1 1 1 0 X X 1 X 0 X X 1 1 1 X X X Serial shift into registers: 36 bits for the IDT72V2103 38 bits for the IDT72V2113 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) All Other Modes Serial shift into registers: 34 bits for the IDT72V2103 36 bits for the IDT72V2113 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) X No Operation X Write Memory Read Memory X No Operation 6119 drw06b NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 3. Programmable Flag Offset Programming Sequence (Continued) 16 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds as follows: when LD and SEN are set LOW, data on the SI input are written, one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. If x9 to x9 mode is selected, a total of 36 bits for the IDT72V2103 and 38 bits for the IDT72V2113. For any other mode of operation (that includes x18 bus width on either the Input or Output), minus 2 bits from the values above. So, a total of 34 bits for the IDT72V2103 and 36 bits for the IDT72V2113. See Figure 15, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode. Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid status only after the complete set of bits (for all offset registers) has been entered. The registers can be reprogrammed as long as the complete set of new offset bits is entered. When LD is LOW and SEN is HIGH, no serial write to the registers can occur. Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select number of bits can be written to the SI input and then, by bringing LD and SEN HIGH, data can be written to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored to a LOW, the next offset bit in sequence is written to the registers via SI. If an interruption of serial programming is desired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN are both restored to a LOW level, serial offset programming continues. From the time serial programming has begun, neither programmable flag will be valid until the full set of bits required to fill all the offset registers has been written. Measuring from the rising WCLK edge that achieves the above criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2. It is not possible to read the flag offset values in a serial mode. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Note that for x9 bus width, one extra Write cycle is required for both the Empty Offset Register and Full Offset Register. See Figure 16, Parallel Loading of Programmable Flag Registers, for the timing diagram for this mode. The act of writing offsets in parallel employs a dedicated write offset register pointer. The act of reading offsets employs a dedicated read offset register pointer. The two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers. A Master Reset initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has no effect on the position of these pointers. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D0-Dn used during parallel programming. Write operations to the FIFO are allowed before and during the parallel programming sequence. In this case, the programming of all offset registers does not have to occur at one time. One, two or more offset registers can be written and then by bringing LD HIGH, write operations can be redirected to the FIFO memory. When LD is set LOW again, and WEN is LOW, the next offset register in sequence is written to. As an alternative to holding WEN LOW and toggling LD, parallel programming can also be interrupted by setting LD LOW and toggling WEN. Note that the status of a programmable flag (PAE or PAF) output is invalid during the programming process. From the time parallel programming has begun, a programmable flag output will not be valid until the appropriate offset word has been written to the register(s) pertaining to that flag. Measuring from the rising WCLK edge that achieves the above criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2. The act of reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers can be read on the Q0-Qn pins when LD is set LOW and REN is set LOW. If the FIFO is configured for an input bus width and output bus width both set to x9, then the total number of read operations required to read the offset registers is 6 for the IDT72V2103/ 72V2113. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D0-Dn used during parallel programming. If the FIFO is configured for an input to output bus width of x9 to x18, x18 to x9 or x18 to x18, then the following number of read operations are required: for an output bus width of x18 a total of 4 read operations will be required for the IDT72V2103/72V2113. For an output bus width of x9 a total of 6 will be required for the IDT72V2103/72V2113. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram. For example, reading PAE and PAF on the IDT72V2103/72V2113 configured for x18 bus width proceeds as follows: data are read via Qn from the Empty Offset Register on the first and second LOW-to-HIGH transition of RCLK. Upon the third and fourth LOW-to-HIGH transition of RCLK, data are read from the Full Offset Register. The fifth and sixth transition of RCLK reads, once again, from the Empty Offset Register. Note that for a x9 bus width, one extra Read cycle is required for both the Empty Offset Register and Full Offset Register. See Figure 17, Parallel Read of Programmable Flag Registers, for the timing diagram for this mode. It is permissible to interrupt the offset register read sequence with reads or writes to the FIFO. The interruption is accomplished by deasserting REN, LD, or both together. When REN and LD are restored to a LOW level, reading of the offset registers continues where it left off. It should be noted, and care should be taken from the fact that when a parallel read of the flag offsets is performed, the data word that was present on the output lines Qn will be overwritten. Parallel reading of the offset registers is always permitted regardless of which timing mode (IDT Standard or FWFT modes) has been selected. PARALLEL PROGRAMMING MODE If Parallel Programming mode has been selected, as described above, then programming of PAE and PAF values can be achieved by using a combination of the LD, WCLK , WEN and Dn input pins. If the FIFO is configured for an input bus width and output bus width both set to x9, then the total number of write operations required to program the offset registers is 6 for the IDT72V2103/ 72V2113. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D0-Dn used during parallel programming. If the FIFO is configured for an input to output bus width of x9 to x18, x18 to x9 or x18 to x18, then the following number of write operations are required. For an input bus width of x18 total of 4 write operations will be required for the IDT72V2103/72V2113. For an input bus width of x9 a total of 6 will be required for the IDT72V2103/72V2113. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram. For example, programming PAE and PAF on the IDT72V2103/72V2113 configured for x18 bus width proceeds as follows: when LD and WEN are set LOW, data on the inputs Dn are written into the LSB of the Empty Offset Register on the first LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of WCLK, data are written into the MSB of the Empty Offset Register. On the third LOW-to-HIGH transition of WCLK, data are written into the LSB of the Full Offset Register. On the fourth LOW-to-HIGH transition of WCLK, data are written into the MSB of the Full Offset Register. The fifth LOW-to-HIGH transition of WCLK, data are written, once again to the Empty Offset Register. 17 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES is selected, every word read including the first word following Retransmit setup requires a LOW on REN to enable the rising edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant timing diagram. If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes LOW, Retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. Since FWFT mode is selected, the first word appears on the outputs, no LOW on REN is necessary. Reading all subsequent words requires a LOW on REN to enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. For either IDT Standard mode or FWFT mode, updating of the PAE, HF and PAF flags begin with the rising edge of RCLK that the RT is setup on. PAE is synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup, the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK that RT is setup will update HF. PAF is synchronized to WCLK, thus the second rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that RT is setup will update PAF. RT is synchronized to RCLK. The Retransmit function has the option of 2 modes of operation, either "normal latency" or "zero latency". Figure 11 and Figure 12 mentioned previously, relate to "normal latency". Figure 13 and Figure 14 show "zero latency" retransmit operation. Zero latency basically means that the first data word to be retransmitted, is placed onto the output register with respect to the RCLK pulse that initiated the retransmit. RETRANSMIT OPERATION The Retransmit operation allows data that has already been read to be accessed again. There are 2 modes of Retransmit operation, normal latency and zero latency. There are two stages to Retransmit: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of memory. Retransmit setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. When zero latency is utilized, REN does not need to be HIGH before bringing RT LOW. At least two words, but no more than D - 2 words should have been written into the FIFO, and read from the FIFO, between Reset (Master or Partial) and the time of Retransmit setup. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode, if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard mode 18 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 SIGNAL DESCRIPTION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Asynchronous operation of the read port will be selected. During Asynchronous operation of the read port the RCLK input becomes RD input, this is the Asynchronous read strobe input. A rising edge on RD will read data from the FIFO via the output register and Qn port. (REN must be tied LOW during Asynchronous operation of the read port). The OE input provides three-state control of the Qn output bus, in an asynchronous manner. When the read port is configured for Asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissible if the read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous manner, that is, the empty flag will be updated based on both a read operation and a write operation. Refer to figures 25, 26, 27 and 28 for relevant timing and operational waveforms. INPUTS: DATA IN (D0 - Dn) Data inputs for 18-bit wide data (D0-D17) or data inputs for 9-bit wide data (D0-D8). CONTROLS: MASTER RESET (MRS) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH. If FWFT/SI is LOW during Master Reset then the IDT Standard mode, along with EF and FF are selected. EF will go LOW and FF will go HIGH. If FWFT/ SI is HIGH, then the First Word Fall Through mode (FWFT), along with IR and OR, are selected. OR will go HIGH and IR will go LOW. All control settings such as OW, IW, BE, RM, PFM and IP are defined during the Master Reset cycle. During a Master Reset, the output register is initialized to all zeroes. A Master Reset is required after power up, before a write operation can take place. MRS is asynchronous. See Figure 5, Master Reset Timing, for the relevant timing diagram. RETRANSMIT (RT) The Retransmit operation allows data that has already been read to be accessed again. There are 2 modes of Retransmit operation, normal latency and zero latency. There are two stages to Retransmit: first, a setup procedure that resets the read pointer to the first location of memory, then the actual retransmit, which consists of reading out the memory contents, starting at the beginning of the memory. Retransmit setup is initiated by holding RT LOW during a rising RCLK edge. REN and WEN must be HIGH before bringing RT LOW. When zero latency is utilized, REN does not need to be HIGH before bringing RT LOW. If IDT Standard mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting EF LOW. The change in level will only be noticeable if EF was HIGH before setup. During this period, the internal read pointer is initialized to the first location of the RAM array. When EF goes HIGH, Retransmit setup is complete and read operations may begin starting with the first location in memory. Since IDT Standard mode is selected, every word read including the first word following Retransmit setup requires a LOW on REN to enable the rising edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant timing diagram. If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit setup by setting OR HIGH. During this period, the internal read pointer is set to the first location of the RAM array. When OR goes LOW, Retransmit setup is complete; at the same time, the contents of the first location appear on the outputs. Since FWFT mode is selected, the first word appears on the outputs, no LOW on REN is necessary. Reading all subsequent words requires a LOW on REN to enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing diagram. In Retransmit operation, zero-latency mode can be selected using the Retransmit Mode (RM) pin during a Master Reset. This can be applied to both IDT Standard mode and FWFT mode. PARTIAL RESET (PRS) A Partial Reset is accomplished whenever the PRS input is taken to a LOW state. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH, and HF goes HIGH. Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall Through mode is active, then OR will go HIGH, and IR will go LOW. Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel or serial) currently active at the time of Partial Reset is also retained. The output register is initialized to all zeroes. PRS is asynchronous. A Partial Reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient. See Figure 6, Partial Reset Timing, for the relevant timing diagram. ASYNCHRONOUS WRITE (ASYW) The write port can be configured for either Synchronous or Asynchronous mode of operation. If during Master Reset the ASYW input is LOW, then Asynchronous operation of the write port will be selected. During Asynchronous operation of the write port the WCLK input becomes WR input, this is the Asynchronous write strobe input. A rising edge on WR will write data present on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write port in Asynchronous mode). When the write port is configured for Asynchronous operation the full flag (FF) operates in an asynchronous manner, that is, the full flag will be updated based in both a write operation and read operation. Note, if Asynchronous mode is selected, FWFT is not permissable. Refer to Figures 23, 24, 27 and 28 for relevant timing and operational waveforms. RETRANSMIT LATENCY MODE (RM) A zero-latency retransmit timing mode can be selected using the Retransmit timing Mode pin (RM). During Master Reset, a LOW on RM will select zerolatency retransmit. A HIGH on RM during Master Reset will select normal latency. If zero-latency retransmit operation is selected the first data word to be retransmitted will be placed on the output register with respect to the same RCLK edge that initiated the retransmit based on RT being LOW. Refer to Figure 13 for Retransmit Timing with zero latency (IDT Standard Mode). Refer to Figure 14 for Retransmit Timing with zero latency (FWFT Mode). ASYNCHRONOUS READ (ASYR) The read port can be configured for either Synchronous or Asynchronous mode of operation. If during a Master Reset the ASYR input is LOW, then 19 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI) This is a dual purpose pin. During Master Reset, the state of the FWFT/ SI input determines whether the device will operate in IDT Standard mode or First Word Fall Through (FWFT) mode. If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF) to indicate whether or not there are any words present in the FIFO memory. It also uses the Full Flag function (FF) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF offsets into the programmable registers. The serial input function can only be used when the serial loading method has been selected during Master Reset. Serial programming using the FWFT/SI pin functions the same way in both IDT Standard and FWFT modes. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags will not be updated. (Note that RCLK is only capable of updating the HF flag to HIGH). The Write and Read Clocks can be independent or coincident. If Asynchronous operation has been selected this input is RD (Read Strobe) . Data is Asynchronously read from the FIFO via the output register whenever there is a rising edge on RD. In this mode the REN input must be tied LOW. The OE input is used to provide Asynchronous control of the threestate Qn outputs. READ ENABLE (REN) When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. In the IDT Standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF will go HIGH allowing a read to occur. The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle. In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK + tSKEW after the first write. REN does not need to be asserted LOW. In order to access all other words, a read must be executed using REN. The RCLK LOW to HIGH transition after the last word has been read from the FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read operations. REN is ignored when the FIFO is empty. If Asynchronous operation of the Read port has been selected, then REN must be held active, (tied LOW). WRITE STROBE & WRITE CLOCK (WR/WCLK) If Synchronous operation of the write port has been selected via ASYW, this input behaves as WCLK. A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met with respect to the LOW-to-HIGH transition of the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/ IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of updating HF flag to LOW). The Write and Read Clocks can either be independent or coincident. If Asynchronous operation has been selected this input is WR (write strobe). Data is Asynchronously written into the FIFO via the Dn inputs whenever there is a rising edge on WR. In this mode the WEN input must be tied LOW. SERIAL ENABLE (SEN) The SEN input is an enable used only for serial programming of the offset registers. The serial programming method must be selected during Master Reset. SEN is always used in conjunction with LD. When these lines are both LOW, data at the SI input can be loaded into the program register one bit for each LOW-to-HIGH transition of WCLK. When SEN is HIGH, the programmable registers retains the previous settings and no offsets are loaded. SEN functions the same way in both IDT Standard and FWFT modes. WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLKcycle. To prevent data overflow in the IDT Standard mode, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to occur. The FF is updated by two WCLK cycles + tSKEW after the RCLK cycle. To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing a write to occur. The IR flag is updated by two WCLK cycles + tSKEW after the valid RCLK cycle. WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode. If Asynchronous operation of the Read port has been selected, then WEN must be held active, (tied LOW). OUTPUT ENABLE (OE) When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes into a high impedance state. LOAD (LD) This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, LD enables write operations to and read operations from the offset registers. Only the offset loading method currently selected can be used to write to the registers. Offset registers can be read only in parallel. After Master Reset, the LD pin is used to activate the programming process of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading or parallel load or read of these offset values. READ STROBE & READ CLOCK (RD/RCLK) If Synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge of the RCLK input. 20 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information. In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR will go HIGH after D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. See Figure 9, Write Timing (FWFT Mode), for the relevant timing information. The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in IDT Standard mode. FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs. BUS-MATCHING (IW, OW) The pins IW and OW are used to define the input and output bus widths. During Master Reset, the state of these pins is used to configure the device bus sizes. See Table 1 for control settings. All flags will operate based on the word/ byte size boundary as defined by the selection of the widest input or output bus width. BIG-ENDIAN/LITTLE-ENDIAN (BE) During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset will select Little-Endian format. This function is useful when data is written into the FIFO in word format (x18) and read out of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is selected, then the most significant byte of the word written into the FIFO will be read out of the FIFO first, followed by the least significant byte. If Little-Endian format is selected, then the least significant byte of the word written into the FIFO will be read out first, followed by the most significant byte. The mode desired is configured during master reset by the state of the Big-Endian (BE) pin. Refer to Figure 4, Bus-Matching Byte Arrangement, for a diagram showing the byte arrangement. PROGRAMMABLE FLAG MODE (PFM) During Master Reset During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-toHIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-toHIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF configuration is selected (PFM, HIGH during MRS) , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin. EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for the relevant timing information. In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing information. EF/OR is synchronous and updated on the rising edge of RCLK. In IDT Standard mode, EF is a double register-buffered output. In FWFT mode, OR is a triple register-buffered output. INTERSPERSED PARITY (IP) During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity mode. The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If Interspersed Parity mode is selected, then the FIFO will assume that the parity bit is located in bit position D8 and D17 during the parallel programming of the flag offsets, and will therefore ignore D8 when loading the offset register in parallel mode. This is also applied to the output register when reading the value of the offset register. If Interspersed Parity is selected then output Q8 will be invalid. If Non-Interspersed Parity mode is selected, then D16 and D17 are the parity bits and are ignored during parallel programming of the offsets. (D8 becomes a valid bit). Additionally, output Q8 will become a valid bit when performing a read of the offset register. IP mode is selected during Master Reset by the state of the IP input pin. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect the data written to and read from the FIFO. PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full flag (PAF) will go LOW when the FIFO reaches the almost-full condition. In IDT Standard mode, if no reads are performed after reset (MRS), PAF will go LOW after (D-m) words are written to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (131,072-m) writes for the IDT72V2103 and (262,144-m) writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, (D-m) = (262,144-m) writes for the IDT72V2103 and (524,288-m) writes for the IDT72V2113. The offset “m” is the full offset value. The default setting for this value is stated in Table 2. In FWFT mode, if x18 Input or x18 Output bus Width is selected, the PAF will go LOW after (131,073-m) writes for the IDT72V2103 and (262,145-m) writes for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, the PAF will go LOW after (262,145-m) writes for the IDT72V2103 and (524,289-m) writes for the IDT72V2113. The offset m is the full offset value. The default setting for this value is stated in Table 2. See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. OUTPUTS: FULL FLAG (FF/IR) This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function is selected. When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full. If no reads are performed 21 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES HALF-FULL FLAG (HF) This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF LOW. The flag remains LOW until the difference between the write and read pointers becomes less than or equal to half of the total depth of the device; the rising RCLK edge that accomplishes this condition sets HF HIGH. In IDT Standard mode, if no reads are performed after reset (MRS or PRS), HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode, if no reads are performed after reset (MRS or PRS), HF will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. Because HF is updated by both RCLK and WCLK, it is considered asynchronous. If asynchronous PAF configuration is selected, the PAF is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF configuration is selected, the PAF is updated on the rising edge of WCLK. See Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Mode). PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words or less in the FIFO. The offset “n” is the empty offset value. The default setting for this value is stated in Table 2. In FWFT mode, the PAE will go LOW when there are n+1 words or less in the FIFO. The default setting for this value is stated in Table 2. See Figure 19, Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. If asynchronous PAE configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE configuration is selected, the PAE is updated on the rising edge of RCLK. See Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. DATA OUTPUTS (Q0-Qn) (Q0 - Q17) data outputs for 18-bit wide data or (Q0 - Q8) data outputs for 9bit wide data. 22 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT: BE IW OW L L L BE IW OW H L L D17-D9 D8-D0 A B Q17-Q9 Q8-Q0 A B COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Write to FIFO Read from FIFO (a) x18 INPUT to x18 OUTPUT - BIG ENDIAN Q17-Q9 Q8-Q0 B A Read from FIFO (b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN Q17-Q9 BE IW OW L L H Q8-Q0 A Q17-Q9 1st: Read from FIFO Q8-Q0 B 2nd: Read from FIFO (c) x18 INPUT to x9 OUTPUT - BIG ENDIAN Q17-Q9 BE IW OW H L H Q8-Q0 B Q17-Q9 1st: Read from FIFO Q8-Q0 A 2nd: Read from FIFO (d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN BYTE ORDER ON INPUT PORT: D17-D9 D8-D0 A D17-Q9 D8-Q0 B BYTE ORDER ON OUTPUT PORT: BE IW OW L H L 1st: Write to FIFO Q17-Q9 Q8-Q0 A B 2nd: Write to FIFO Read from FIFO (a) x9 INPUT to x18 OUTPUT - BIG ENDIAN BE IW OW H H L Q17-Q9 Q8-Q0 B A Read from FIFO (a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN 6119 drw07 Figure 4. Bus-Matching Byte Arrangement 23 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tRS MRS tRSS tRSR tRSS tRSR tRSS tRSR tRSS tRSR REN WEN FWFT/SI LD tRSS ASYW, ASYR tRSS FSEL0, FSEL1 tRSS OW, IW tRSS BE tRSS RM tRSS PFM tRSS IP tRSS RT tRSS SEN If FWFT = HIGH, OR = HIGH tRSF EF/OR If FWFT = LOW, EF = LOW tRSF If FWFT = LOW, FF = HIGH FF/IR If FWFT = HIGH, IR = LOW tRSF PAE tRSF PAF, HF tRSF OE = HIGH Q0 - Q n OE = LOW Figure 5. Master Reset Timing 24 6119 drw08 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tRS PRS tRSS tRSR REN tRSS tRSR WEN tRSS RT tRSS SEN If FWFT = HIGH, OR = HIGH tRSF EF/OR If FWFT = LOW, EF = LOW If FWFT = LOW, FF = HIGH tRSF FF/IR If FWFT = HIGH, IR = LOW tRSF PAE tRSF PAF, HF tRSF OE = HIGH Q0 - Qn OE = LOW Figure 6. Partial Reset Timing 25 6119 drw09 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLK tCLKH NO WRITE WCLK tCLKL NO WRITE 2 1 1 tSKEW1(1) tDS D0 - Dn tDH 2 tSKEW1(1) tDH tDS DX DX+1 tWFF tWFF tWFF tWFF FF WEN RCLK tENS tENS tENH tENH REN tA tA Q0 - Qn DATA IN OUTPUT REGISTER NEXT DATA READ DATA READ 6119 drw10 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle. 2. LD = HIGH, EF = HIGH Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode) tCLK tCLKH RCLK 1 tENS tCLKL 2 tENS tENH REN tENH tENS tENH NO OPERATION NO OPERATION tREF tREF tREF EF tA tA Q0 - Qn LAST WORD tOLZ LAST WORD D1 tOLZ tOHZ tOE tA D0 OE tSKEW1(1) WCLK tENS tENH tENS tDHS tDS tENH WEN tDS D0 - Dn D0 tDH D1 6119 drw11 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle. 2. LD = HIGH. 3. First data word latency: tSKEW1 + 1*TRCLK + tREF. Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode) 26 27 tDS tENS W1 W2 2 DATA IN OUTPUT REGISTER 1 tSKEW1(1) tDH W3 3 tREF tA W4 tDS W1 W[n +2] W[n+3] 1 tSKEW2 (2) 2 tPAES W[n+4] W[ D-1 ] tDS W[ D-1 ] tHF W[ D-1 ] W[D-m-2] tDS W[D-m-1] W[D-m] 1 W[D-m+1] 2 tPAFS W[D-m+2] W[D-1] WD 6119 drw12 tWFF tENH Figure 9. Write Timing and First Data Word Latency Timing (First Word Fall Through Mode) NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then OR assertion may be delayed one extra RCLK cycle. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 3. LD = HIGH, OE = LOW 4. n = PAE offset, m = PAF offset and D = maximum FIFO depth. 5. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. 6. First data word latency: tSKEW1 + 2*TRCLK + tREF. IR PAF HF PAE OR Q0 - Q17 REN RCLK D0 - D17 WEN WCLK BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 28 tDS tENS W1 tOHZ WD tENS tWFF tDH tENH W1 tOE tA W2 1 (1) tSKEW1 tA 2 tWFF W3 (2) Wm+2 tSKEW2 W[m+3] tA tPAFS W[m+4] W[ D-1 ] tHF W[ tA D-1 ] W[D-n-1] tA W[D-n] 1 W[D-n+1] 2 tPAES W[D-n+2] W[D-1] tA tENS WD 6119 drw13 tREF Figure 10. Read Timing (First Word Fall Through Mode) NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle. 2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle. 3. LD = HIGH 4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth. 5. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. IR PAF HF PAE OR Q0 - Q17 OE REN RCLK D0 - D17 WEN WCLK FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 2 1 RCLK tENS tENH COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tENS tRTS tENH REN tA Q0 - Qn tA Wx tA W1(3) Wx+1 W2(3) tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT tREF tREF EF tPAES PAE tHF HF tPAFS PAF 6119 drw14 NOTES: 1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin. 2. OE = LOW. 3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset. 4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. 5. There must be at least two words written to and two words read from the FIFO before a Retransmit operation can be invoked. 6. RM is set HIGH during MRS. Figure 11. Retransmit Timing (IDT Standard Mode) 29 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 1 RCLK tENH tENS COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3 2 4 tENH tENS tRTS REN tA Q0 - Qn tA tA (4) Wx+1 Wx W1 W2 (4) tA W3(4) W4 tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT tREF tREF OR tPAES PAE tHF HF tPAFS PAF 6119 drw15 NOTES: 1. Retransmit setup is complete after OR returns LOW. 2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. 3. OE = LOW 4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. 6. RM is set HIGH during MRS. Figure 12. Retransmit Timing (FWFT Mode) 30 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 RCLK COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2 1 3 tENH tENS REN Q0 - Qn tA tA tA Wx W2(3) W1(3) Wx+1 tA tA W3(3) W4 tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT EF(1) tPAES PAE tHF HF tPAFS PAF 6119 drw16 NOTES: 1. If the part is empty at the point of Retransmit, the Empty Flag (EF) will be updated based on RCLK (Retransmit clock cycle). Valid data will also appear on the output. 2. OE = LOW: enables data to be read on outputs Q0-Qn. 3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset. 4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. 5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked. 6. RM is set LOW during MRS. Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode) 31 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 RCLK 2 1 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 4 3 5 tENH tENS REN tA Q0 - Qn Wx tA Wx+1 tA tA W1 W2 (3) W3 tA (3) W4 (3) W5 tSKEW2 1 WCLK 2 tRTS WEN tENS tENH RT OR tPAES PAE tHF HF tPAFS PAF 6119 drw17 NOTES: 1. If the part is empty at the point of Retransmit, the output ready flag (OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output. 2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. 3. OE = LOW 4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset. 5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked. 6. RM is set LOW during MRS. Figure 14. Zero Latency Retransmit Timing (FWFT Mode) WCLK tENS tENH tENH SEN tLDS tLDH tLDH LD tDS SI tDH BIT X(1) BIT 0 BIT X(1) BIT 0 FULL OFFSET EMPTY OFFSET NOTES: 1. x9 to x9 mode: X = 17 for the IDT72V2103 and X = 18 for the IDT72V2113. 2. All other modes: X = 16 for the IDT72V2103 and X = 17 for the IDT72V2113. Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) 32 6119 drw18 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLK tCLKH tCLKL WCLK tLDS tLDH tLDH tENS tENH tENH tDS tDH LD WEN tDS tDS tDH tDS tDH tDH D0 - D16 PAE OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (LSB) 6119 drw19 PAF OFFSET (MSB) NOTE: 1. This diagram is based on programming the IDT72V2103/72V2113 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width. Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) tCLK tCLKH tCLKL RCLK tLDS tLDH tLDH tENS tENH tENH LD REN tA Q0 - Q16 tA PAE OFFSET (LSB) DATA IN OUTPUT REGISTER tA tA PAF OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (MSB) NOTES: 1. OE = LOW. 2. This diagram is based on programming the IDT72V2103/72V2113 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width. 6119 drw20 Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK 1 tENS 1 2 2 tENH WEN tPAFS PAF tPAFS (2) (2) D-(m+1) words in FIFO D - m words in FIFO tSKEW2(3) D-(m+1) words in FIFO(2) RCLK tENS tENH REN 6119 drw21 NOTES: 1. m = PAF offset . 2. D = maximum FIFO depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. 3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle. 4. PAF is asserted and updated on the rising edge of WCLK only. 5. Select this mode by setting PFM HIGH during Master Reset. Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes) 33 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 tCLKH COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLKL WCLK tENS tENH WEN PAE n words in FIFO (2), n+1 words in FIFO (3) tSKEW2(4) RCLK tPAES 1 n words in FIFO (2), n+1 words in FIFO(3) n+1 words in FIFO (2), n+2 words in FIFO (3) 2 tPAES 1 2 tENH tENS REN 6119 drw22 NOTES: 1. n = PAE offset. 2. For IDT Standard mode 3. For FWFT mode. 4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 5. PAE is asserted and updated on the rising edge of WCLK only. 6. Select this mode by setting PFM HIGH during Master Reset. Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK tENS tENH WEN tPAFA PAF D ⎯ m words in FIFO D ⎯ (m + 1) words in FIFO D ⎯ (m + 1) words in FIFO tPAFA RCLK tENS REN 6119 drw23 NOTES: 1. m = PAF offset. 2. D = maximum FIFO Depth. In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the DT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. 3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition. 4. Select this mode by setting PFM LOW during Master Reset. Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes) 34 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 tCLKH COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCLKL WCLK tENS tENH WEN PAE tPAEA n words in FIFO(2), n + 1 words in FIFO(3) n words in FIFO(2), n + 1 words in FIFO(3) n + 1 words in FIFO(2), n + 2 words in FIFO(3) tPAEA RCLK tENS REN 6119 drw24 NOTES: 1. n = PAE offset. 2. For IDT Standard Mode. 3. For FWFT Mode. 4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition. 5. Select this mode by setting PFM LOW during Master Reset. Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK tENH tENS WEN [ D2 + 1] words in FIFO(1), [ D +2 1 ] + 1 words in FIFO tHF HF D/2 words in FIFO(1), (2) [ D 2+ 1 ] words in FIFO(2) D/2 words in FIFO(1), [ D +2 1 ] words in FIFO(2) tHF RCLK tENS REN 6119 drw25 NOTES: 1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,072 for the IDT72V2103 and 262,144 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,144 for the IDT72V2103 and 524,288 for the IDT72V2113. 2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 131,073 for the IDT72V2103 and 262,145 for the IDT72V2113. If both x9 Input and x9 Output bus Widths are selected, D = 262,145 for the IDT72V2103 and 524,289 for the IDT72V2113. Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes) 35 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RCLK tENS REN tENH tA Qn W0 W1 tFFA FF tFFA tFFA tCYC WR tDS Dn tCYH tDH WD WD+1 6119 drw26 NOTE: 1. OE = LOW and WEN = LOW. Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode) 1 RCLK 2 tENS REN tENH tA tA Qn Last Word W1 W0 tREF tREF EF tCYL tSKEW WR tCYH tCYC tDH tDS Dn W0 tDH tDS W1 6119 drw27 NOTE: 1. OE = LOW and WEN = LOW. Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode) 36 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES No Write WCLK 1 2 WEN Dn DF tWFF DF+1 tWFF FF tCYC tSKEW tCYL tCYH RD tAA tAA Qn Last Word WX WX+1 6119 drw28 NOTES: 1. OE = LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) WCLK tENS tENH WEN tDS Dn EF tDH W0 tEFA tRPE RD tEFA tCYH tAA Qn Last Word in Output Register W0 6119 drw29 NOTES: 1. OE = LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode) 37 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 tCYH tCYC COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tCYL WR tDH Dn tDH tDS W0 W1 RD tAA tAA Qn W1 W0 Last Word in O/P Register tRPE tEFA tEFA EF 6119 drw30 NOTES: 1. OE = LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode) tCYC tCYH tCYL WR tDH tDS Dn tDS tDH Wy+1 Wy tCYC tCYH tCYL RD tAA Qn Wx tAA Wx+1 Wx+2 tFFA tFFA FF 6119 drw31 NOTES: 1. OE = LOW, WEN = LOW, and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only. Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode) 38 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 OPTIONAL CONFIGURATIONS COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO, and separately ORing IR of every FIFO. Figure 29 demonstrates a width expansion using two IDT72V2103/ 72V2113 devices. If x18 Input or x18 Output bus Width is selected, D0-D17 from each device form a 36-bit wide input bus and Q0-Q17 from each device form a 36-bit wide output bus. If both x9 Input and x9 Output bus Widths are selected, D0-D8 from each device form an 18-bit wide input bus and Q0-Q8 from each device form an 18-bit wide output bus. Any word width can be attained by adding additional IDT72V2103/72V2113 devices. WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the EF and FF functions in IDT Standard mode and the IR and OR functions in FWFT mode. Because of variations in skew between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary by one cycle between FIFOs. In IDT Standard mode, such problems can be avoided by creating composite flags, that is, ANDing EF PARTIAL RESET (PRS) MASTER RESET (MRS) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) RETRANSMIT (RT) DATA IN m+n Dm+1 - Dn D0 - Dm m n READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) LOAD (LD) IDT 72V2103 72V2113 IDT 72V2103 72V2113 OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) FULL FLAG/INPUT READY (FF/IR) #1 EMPTY FLAG/OUTPUT READY (EF/OR) #1 (1 ) GATE FULL FLAG/INPUT READY (FF/IR) #2 EMPTY FLAG/OUTPUT READY (EF/OR) #2 PROGRAMMABLE (PAF) HALF-FULL FLAG (HF) n FIFO #1 m Qm+1 - Qn m+n FIFO #2 Q0 - Qm NOTES: 1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode. 2. Do not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. Figure 29. Block Diagram of Width Expansion For the x18 Input or x18 Output bus Width: 131,072 x 36 and 262,144 x 36 For both x9 Input and x9 Output bus Widths: 262,144 x 18 and 524,288 x 18 39 (1 ) GATE DATA OUT 6119 drw32 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES FWFT/SI TRANSFER CLOCK WRITE CLOCK WCLK WRITE ENABLE WEN INPUT READY IR FWFT/SI IDT 72V2103 72V2113 OR n Dn WEN REN OE DATA IN WCLK RCLK IR FWFT/SI IDT 72V2103 72V2113 GND Qn n Dn READ CLOCK RCLK REN READ ENABLE OR OUTPUT READY OE OUTPUT ENABLE Qn n DATA OUT 6119 drw33 Figure 30. Block Diagram of Depth Expansion For the x18 Input or x18 Output bus Width: 262,144 x 18 and 524,288 x 18 For both x9 Input and x9 Output bus Widths: 524,288 x 9 and 1,048,576 x 9 DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72V2103 can easily be adapted to applications requiring depths greater than 131,072 when the x18 Input or x18 Output bus Width is selected and 262,144 for the IDT72V2113. When both x9 Input and x9 Output bus Widths are selected, depths greater than 262,144 can be adapted for the IDT72V2103 and 524,288 for the IDT72V2113. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 30 shows a depth expansion using two IDT72V2103/72V2113 devices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next ("ripple down") until it finally appears at the outputs of the last FIFO in the chain–no read operation is necessary but the RCLK of each FIFO must be free-running. Each time the data word appears at the outputs of one FIFO, that device's OR line goes LOW, enabling a write to the next FIFO in line. For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's outputs) after a word has been written to the first FIFO is the sum of the delays for each individual FIFO: specification is not met between WCLK and transfer clock, or RCLK and transfer clock, for the OR flag. The "ripple down" delay is only noticeable for the first word written to an empty depth expansion configuration. There will be no delay evident for subsequent words written to the configuration. The first free location created by reading from a full depth expansion configuration will "bubble up" from the last FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO to write a word to fill it. For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: (N – 1)*(3*transfer clock) + 2 TWCLK where N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and transfer clock, for the IR flag. The Transfer Clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain. (N – 1)*(4*transfer clock) + 3*TRCLK where N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 40 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES tTCK tJTCKR tJTCKF tJTCKL tJTCKH TCK TDI/ TMS tDS tDH TDO TDO tDO tJRSR 6119 drw34 TRST(1) tJRST NOTE: 1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. Figure 31. Standard JTAG Timing JTAG AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ± 5%; Tcase = 0°C to +85°C) Parameter SYSTEM INTERFACE PARAMETERS Symbol Data Output tDO(1) Data Output Hold tDOH(1) Data Input tDS tDH Test Conditions Min. - trise=3ns tfall=3ns Max. Units - 100 - ns JTAG Clock HIGH tJTCKH - 40 - ns JTAG Clock Low tJTCKL - 40 - ns ns JTAG Clock Rise Time t JTCKR - - 5(1) ns (1) Max. Units 20 Test Conditions Min. JTAG Clock Input Period tTCK IDT72V2103 IDT72V2113 Parameter Symbol 0 - ns JTAG Clock Fall Time t JTCKF - - 5 ns 10 10 - ns JTAG Reset tJRST - 50 - ns JTAG Reset Recovery tJRSR - 50 - ns NOTE: 1. Guaranteed by design. NOTE: 1. 50pf loading on external output signals. 41 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 JTAG INTERFACE COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES The Standard JTAG interface consists of four basic elements: • Test Access Port (TAP) • TAP controller • Instruction Register (IR) • Data Register Port (DR) Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72V2103/72V2113 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). The Figure below shows the standard Boundary-Scan Architecture DeviceID Reg. Mux Boundary Scan Reg. Bypass Reg. TDO TDI T A TMS TCLK TRST P TAP clkDR, ShiftDR UpdateDR Controller Instruction Decode clklR, ShiftlR UpdatelR Instruction Register Control Signals 6119 drw35 Figure 32. Boundary Scan Architecture THE TAP CONTROLLER The Tap controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and update of data. TEST ACCESS PORT (TAP) The Tap interface is a general-purpose port that provides access to the internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST) and one output port (TDO). 42 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 1 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Test-Logic Reset 0 0 Run-Test/ Idle 1 SelectDR-Scan 1 SelectIR-Scan 1 0 1 0 Capture-IR 1 Capture-DR 0 0 0 Shift-DR 1 1 Input = TMS Exit1-DR 1 0 1 Exit2-DR Exit2-IR 0 1 1 Update-IR Update-DR 0 0 Pause-IR 1 1 1 Exit1-IR 0 0 Pause-DR 0 0 Shift-IR 1 0 6119 drw36 NOTE: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. Figure 33. TAP Controller State Diagram Capture-IR In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of fixed values on the rising edge of TCK. The last two significant bits are always required to be “01”. Shift-IR In this controller state, the instruction register gets connected between TDI and TDO, and the captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI pin is also shifted in to the instruction register. Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made. Pause-IR This state is provided in order to allow the shifting of instruction register to be temporarily halted. Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made. Update-IR In this controller state, the instruction in the instruction register is latched in to the latch bank of the Instruction Register on every falling edge of TCK. This instruction also becomes the current instruction once it is latched. Capture-DR In this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of TCK. Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path. Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram. All state transitions within the TAP controller occur at the rising edge of the TCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. The TAP controller takes precedence over the Queue and must be reset after power up of the device. See TRST description for more details on TAP controller reset. Test-Logic-Reset All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP controller state machine is designed in such a way that, no matter what the initial state of the controller is, the TestLogic-Reset state can be entered by holding TMS at high and pulsing TCK five times. This is the reason why the Test Reset (TRST) pin is optional. Run-Test-Idle In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it will be executed when the controller enters this state. The test logic in the IC is idles otherwise. Select-DR-Scan This is a controller state where the decision to enter the Data Path or the Select-IR-Scan state is made. Select-IR-Scan This is a controller state where the decision to enter the Instruction Path is made. The Controller can return to the Test-Logic-Reset state other wise. 43 FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH 3.3V DENSITY IITM NARROW IDT72V263/273/283/293/103/113 HIGHSUPERSYNC DENSITY SUPERSYNC IITM BUS NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x x9 9/18, 256K x 9/18, 512K x9 THE INSTRUCTION REGISTER JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: • Select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip operation and the selected data register. • Define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode 16 different possible instructions. Instructions are decoded as follows. The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to select the test to be performed, or the test data register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process when the TAP controller is at UpdateIR state. The instruction register must contain 4 bit instruction register-based cells which can hold instruction data. These mandatory cells are located nearest the serial outputs they are the least significant bits. Hex Value 0x00 0x02 0x01 0x03 0x0F TEST DATA REGISTER The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register. These registers are connected in parallel between a common serial input and a common serial data output. The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). Instruction Function EXTEST IDCODE SAMPLE/PRELOAD HIGH-IMPEDANCE BYPASS Select Boundary Scan Register Select Chip Identification data register Select Boundary Scan Register JTAG Select Bypass Register Table 6. JTAG Instruction Register Decoding The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). TEST BYPASS REGISTER The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in serial path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state. The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction. EXTEST The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. As such, the EXTEST instruction is the workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. THE BOUNDARY-SCAN REGISTER The Boundary Scan Register allows serial data TDI be loaded in to or read out of the processor input/output ports. The Boundary Scan Register is a part of the IEEE 1149.1-1990 Standard JTAG Implementation. IDCODE The optional IDCODE instruction allows the IC to remain in its functional mode and selects the optional device identification register to be connected between TDI and TDO. The device identification register is a 32-bit shift register containing information regarding the IC manufacturer, device type, and version code. Accessing the device identification register does not interfere with the operation of the IC. Also, access to the device identification register should be immediately available, via a TAP data-scan operation, after power-up of the IC or after the TAP has been reset using the optional TRST pin or by otherwise moving to the Test-Logic-Reset state. THE DEVICE IDENTIFICATION REGISTER The Device Identification Register is a Read Only 32-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72V2103/72V2113, the Part Number field contains the following values: Device IDT72V2103 IDT72V2113 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Part# Field 042E 042F SAMPLE/PRELOAD The required SAMPLE/PRELOAD instruction allows the IC to remain in a normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register can be accessed via a date scan operation, to take a sample of the functional data entering and leaving the IC. This instruction is also used to preload test data into the boundary-scan register before loading an EXTEST instruction. 31(MSB) 28 27 12 11 1 0(LSB) Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) 0X0 0X33 1 IDT72V2103/72V2113 JTAG Device Identification Register 44 BUS FIFO BUS FIFO IDT72V2103/72V2113 3.3V HIGH DENSITY IITM NARROW IDT72V263/273/283/293/103/113 3.3V HIGHSUPERSYNC DENSITY SUPERSYNC IITM NARROW 8K x 18, x16K x 9/18, 32K 9/18, 64K x 9/18, 128K 131,072 18/262,144 x 9,x262,144 x 18/524,288 x 9x 9/18, 256K x 9/18, 512K x9 HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types) of an IC to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES BYPASS The required BYPASS instruction allows the IC to remain in a normal functional mode and selects the one-bit bypass register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the IC. 45 ORDERING INFORMATION XXXXX X Device Type Power XX X Speed Package X X Process / Temperature Range X BLANK 8 Tube or Tray Tape and Reel BLANK I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G (2) Green PF BC Thin Plastic Quad Flatpack (TQFP, PN80-1) Ball Grid Array (BGA, BC100-1) 6 7-5 10 15 Commercial Only, BGA & TQFP Com‘l & Ind’l, BGA & TQFP Com‘l & Ind’l, TQFP Only Commercial, TQFP Only L Low Power 72V2103 72V2113 131,072 x 18/262,144 x 9 ⎯ 3.3V SuperSync II™ FIFO 262,144 x 18/524,288 x 9 ⎯ 3.3V SuperSync II™ FIFO Clock Cycle Time (tCLK) Speed in Nanoseconds 6119 drw37 NOTES: 1. Industrial temperature range product for 7-5ns and 10ns are available as standard device. All other speed grades are available by special order. 2. Green parts are available. For specific speeds and packages contact you sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-02 DATASHEET DOCUMENT HISTORY 12/18/2000 03/27/2001 04/06/2001 12/14/2001 12/16/2002 02/11/2003 06/26/2003 07/15/2003 07/21/2003 09/29/2003 11/02/2005 04/06/2006 10/22/2008 06/01/2010 08/14/2014 03/08/2018 pgs. 7, 8, 9, and 37. pgs. 9 and 37. pgs. 4, 5, and 21. pgs. 1-35. pgs. 1-11, 19, 20, 24, and 36-45. pgs. 7 and 43. pgs. 1, 3, 9, 10, and 45. pgs. 3, 19, and 36-38. pgs. 7, 41,and 43-45. pg. 8. pgs. 1, 8-10, and 46. pg. 4. pg. 46. pg. 1. pgs. 1-3 and 46. Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 46 for Tech Support: 408-360-1753 email: FIFOhelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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