72V225L10TF8

3.3 VOLT CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72V205, IDT72V215, IDT72V225, IDT72V235, IDT72V245 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • • • • • • • • • • • • • • • • • • 256 x 18-bit organization array (IDT72V205) 512 x 18-bit organization array (IDT72V215) 1,024 x 18-bit organization array (IDT72V225) 2,048 x 18-bit organization array (IDT72V235) 4,096 x 18-bit organization array (IDT72V245) 10 ns read/write cycle time 5V input tolerant IDT Standard or First Word Fall Through timing Single or double register-buffered Empty and Full flags Easily expandable in depth and width Asynchronous or coincident Read and Write Clocks Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings Half-Full flag capability Output enable puts output data bus in high-impedance state High-performance submicron CMOS technology Available in a 64-lead thin quad flatpack (TQFP/STQFP) Industrial temperature range (–40°°C to +85°°C) is available Green parts available, see ordering information DESCRIPTION: The IDT72V205/72V215/72V225/72V235/72V245 are functionally compatible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB, designed to run off a 3.3V supply for exceptionally low power consumption. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. FUNCTIONAL BLOCK DIAGRAM WEN WCLK D0-D17 INPUT REGISTER WRITE CONTROL LOGIC WRITE POINTER FL WXI (HF)/WXO RXI RXO RS LD OFFSET REGISTER FLAG LOGIC RAM ARRAY 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 FF/IR PAF EF/OR PAE HF/(WXO) READ POINTER READ CONTROL LOGIC EXPANSION LOGIC OUTPUT REGISTER RESET LOGIC OE Q0-Q17 IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES RCLK REN 4294 drw 01 MARCH 2018 1 ©2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4294/8 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DESCRIPTION (CONTINUED) operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. These devices are depth expandable using a Daisy-Chain technique or First Word Fall Through mode (FWFT). The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, First Load (FL) is grounded on the first device and set to HIGH for all other devices in the Daisy Chain. The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using high-speed submicron CMOS technology. The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available when the FIFO is used in a single device configuration. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall-Through (FWFT) mode. In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read D16 D17 GND RCLK REN LD OE RS VCC GND EF Q17 Q16 GND Q15 VCC PIN CONFIGURATIONS FL WCLK WEN WXI VCC PAF RXI FF WXO/HF RXO Q0 Q1 GND Q2 Q3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PAE D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN 1 TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW 2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC 4294 drw 02 IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PIN DESCRIPTION Symbol D0–D17 RS Data Inputs Reset I I WCLK WEN Write Clock Write Enable I I RCLK REN Read Clock Read Enable I I OE Output Enable I LD Load I FL First Load I WXI Write Expansion Input I RXI Read Expansion Input I FF/IR Full Flag/ Input Ready O EF/OR Empty Flag/ Output Ready Programmable Almost-Empty Flag O PAE PAF WXO/HF RXO Q0–Q17 V CC GND Name O Programmable Almost-Full Flag Write Expansion Out/Half-Full Flag O Read Expansion Out Data Outputs Power Ground O O O I/O Description Data inputs for an 18-bit bus. When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up. When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full. When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW. When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty. When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW. When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW. In the single device or width expansion configuration, FL together with WXI and RXI determine if the mode is IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration, FL is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain. In the single device or width expansion configuration, WXI together with FL and RXI determine if the mode is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration, WXI is connected to WXO (Write Expansion Out) of the previous device. In the single device or width expansion configuration, RXI together with FL and WXI, determine if the mode is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous. (See Table 1.) In the Daisy Chain Depth Expansion configuration, RXI is connected to RXO (Read Expansion Out) of the previous device. In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset at reset is 31 from empty for IDT72V205, 63 from empty for IDT72V215, and 127 from empty for IDT72V225/ 72V235/72V245. When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at reset is 31 from full for IDT72V205, 63 from full for IDT72V215, and 127 from full for IDT72V225/72V235/72V245. In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the FIFO is written. In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location in the FIFO is read. Data outputs for an 18-bit bus. +3.3V power supply pins. Seven ground pins. 3 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial Unit VTERM Terminal Voltage with respect to GND –0.5 to +5 V TSTG Storage Temperature –55 to +125 °C (2) IOUT DC Output Current –50 to +50 RECOMMENDED DC OPERATING CONDITIONS Symbol VCC mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminal only. Parameter Supply Voltage Commercial/Industrial Min. 3.0 Typ. 3.3 Max. 3.6 Unit V GND Supply Voltage 0 0 0 V VIH Input High Voltage Commercial/Industrial 2.0 — 5.5 V VIL(1) Input Low Voltage Commercial/Industrial -0.5 — 0.8 V TA Operating Temperature Commercial 0 — 70 °C TA Operating Temperature Industrial -40 ⎯ 85 °C NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C) Min. IDT72V205 IDT72V215 IDT72V225 IDT72V235 IDT72V245 Commercial & Industrial(1) tCLK = 10, 15, 20 ns Typ. Max. Unit — 1 µA Symbol Parameter LI(2) I Input Leakage Current (any input) –1 LO(3) I Output Leakage Current –10 — 10 µA VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — V VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 V CC1(4,5,6) I Active Power Supply Current — — 30 mA ICC2(4.7) Standby Current — — 5 mA NOTES: 1. Industrial Temperature Range Product for the 15ns speed grade is available as a standard device. 2. Measurements with 0.4 ≤ VIN ≤ VCC. 3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC. 4. Tested with outputs disabled (IOUT = 0). 5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz. 6. Typical ICC1 = 2.04 + 0.88*fS + 0.02*CL*fS (in mA). These equations are valid under the following conditions: VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF). 7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit (2) CIN Input Capacitance VIN = 0V 10 pF COUT(1,2) Output Capacitance VOUT = 0V 10 pF NOTES: 1. With output deselected, (OE ≥ VIH). 2. Characterized values, not currently tested. 4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C) Symbol fS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAFA tPAFS tPAEA tPAES tHF tXO tXI tXIS tSKEW1 Parameter Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(2) Reset Set-up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low-Z(3) Output Enable to Output Valid Output Enable to Output in High-Z(3) Write Clock to Full Flag Read Clock to Empty Flag Clock to Asynchronous Programmable Almost-Full Flag Write Clock to Synchronous ProgrammableAlmost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag Read Clock to Synchronous Programmable Almost-Empty Flag Clock to Half-Full Flag Clock to Expansion Out Expansion In Pulse Width Expansion In Set-Up Time Skew time between Read Clock & Write Clock for FF/IR and EF/OR tSKEW2(4) Skew time between Read Clock & Write Clock for PAE and PAF Commercial Com'l & Ind'l(1) Commercial IDT72V205L10 IDT72V215L10 IDT72V225L10 IDT72V235L10 IDT72V245L10 IDT72V205L15 IDT72V215L15 IDT72V225L15 IDT72V235L15 IDT72V245L15 IDT72V205L20 IDT72V215L20 IDT72V225L20 IDT72V235L20 IDT72V245L20 Min. — 2 10 4.5 4.5 3 0.5 3 0.5 10 8 8 — 0 — 1 — — — — — — — — 3 3 5 Max. 100 6.5 — — — — — — — — — — 15 — 6 6 6.5 6.5 17 8 17 8 17 6.5 — — — Min. — 2 15 6 6 4 1 4 1 15 10 10 — 0 3 3 — — — — — — — — 6.5 5 6 Max. 66.7 10 — — — — — — — — — — 15 — 8 8 10 10 20 10 20 10 20 10 — — — 14 — 18 — Min. — 2 20 8 8 5 1 5 1 20 12 12 — 0 3 3 — — — — — — — — 8 8 8 20 NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. tSKEW2 applies to synchronous PAE and synchronous PAF only. 3.3V 330Ω D.U.T. AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 510Ω GND to 3.0V 3ns 1.5V 1.5V See Figure 1 30pF* 4294 drw 03 Figure 1. Output Load * Includes jig and scope capacitances. 5 Max. 50 12 — — — — — — — — — — 20 — 10 10 12 12 22 12 22 12 22 12 — — — Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns — ns IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 FUNCTIONAL DESCRIPTION COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 72V245. Continuing read operations will cause the FIFO to be empty. When the last word has been read from the FIFO, the EF will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty. TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72V205/72V215/72V225/72V235/72V245 support two different timing modes of operation. The selection of which mode will operate is determined during configuration at Reset (RS). During a RS operation, the First Load (FL), Read Expansion Input ( RXI), and Write Expansion Input (WXI) pins are used to select the timing mode per the truth table shown in Table 3. In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating Read Enable (REN) and enabling a rising Read Clock (RCLK) edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. Various signals, both input and output signals operate differently depending on which timing mode is in effect. FIRST WORD FALL THROUGH MODE (FWFT) In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the manner outlined in Table 2. To write data into to the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for this value is stated in the footnote of Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If one continued to write data into the FIFO, and we assumed no read operations were taking place, the HF would toggle to LOW once the 130th (72V205), 258th (72V215), 514th (72V225), 1,026th (72V235), and 2,050th (72V245) word respectively was written into the FIFO. Continuing to write data into the FIFO will cause the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW after (257-m) writes for the IDT72V205, (513-m) writes for the IDT72V215, (1,025-m) writes for the IDT72V225, (2,049–m) writes for the IDT72V235 and (4,097–m) writes for the IDT72V245, where m is the full offset value. The default setting for this value is stated in the footnote of Table 2. When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations. If no reads are performed after a reset, IR will go HIGH after D writes to the FIFO. D = 257 writes for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. If the FIFO is full, the first read operation will cause the IR flag to go LOW. Subsequent read operations will cause the PAF and HF to go HIGH at the conditions described in Table 2. If further read operations occur, without write operations, the PAE will go LOW when there are n + 1 words in the FIFO, where n is the empty offset value. If there is no empty offset specified, the PAE will be LOW when the device is 32 away from completely empty for IDT72V205, 64 away from completely empty for IDT72V215, and 128 away from completely empty for IDT72V225/72V235/72V245. Continuing read operations will cause the FIFO to be empty. When the last word has been read from the FIFO, OR will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty. IDT STANDARD MODE In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the manner outlined in Table 1. To write data into to the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for this value is stated in the footnote of Table 1. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If one continued to write data into the FIFO, and we assumed no read operations were taking place, the Half-Full Flag (HF) would toggle to LOW once the 129th (72V205), 257th (72V215), 513th (72V225), 1,025th (72V235), and 2,049th (72V245) word respectively was written into the FIFO. Continuing to write data into the FIFO will cause the Programmable Almost-Full Flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW after (256-m) writes for the IDT72V205, (512-m) writes for the IDT72V215, (1,024-m) writes for the IDT72V225, (2,048-m) writes for the IDT72V235 and (4,096–m) writes for the IDT72V245. The offset “m” is the full offset value. This parameter is also user programmable. See section on Programmable Flag Offset Loading. If there is no full offset specified, the PAF will be LOW when the device is 31 away from completely full for IDT72V205, 63 away from completely full for IDT72V215, and 127 away from completely full for the IDT72V225/72V235/72V245. When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245, respectively. If the FIFO is full, the first read operation will cause FF to go HIGH. Subsequent read operations will cause PAF and the Half-Full Flag (HF) to go HIGH at the conditions described in Table 1. If further read operations occur, without write operations, the Programmable Almost-Empty Flag (PAE) will go LOW when there are n words in the FIFO, where n is the empty offset value. If there is no empty offset specified, the PAE will be LOW when the device is 31 away from completely empty for IDT72V205, 63 away from completely empty for IDT72V215, and 127 away from completely empty for IDT72V225/72V235/ PROGRAMMABLE FLAG LOADING Full and Empty flag offset values can be user programmable. The IDT72V205/ 72V215/72V225/72V235/72V245 has internal registers for these offsets. Default settings are stated in the footnotes of Table 1 and Table 2. Offset values are loaded into the FIFO using the data input lines D0-D11. To load the offset registers, the Load (LD) pin and WEN pin must be held LOW. Data present on D0-D11 will be transferred in to the Empty Offset register on the first LOW-to-HIGH transition of WCLK. By continuing to hold the LD and WEN pin low, data present on D0-D11 will be transferred into the Full Offset register on the next transition of the WCLK. The third transition again writes to the Empty Offset register. Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing the LD pin HIGH, the FIFO is returned to normal read/write operation. When the LD pin and WEN are again set LOW, the next offset register in sequence is written. 6 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 If synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK. For detail timing diagrams, see Figure 22 for synchronous PAE timing and Figure 23 for synchronous PAF timing. The contents of the offset registers can be read on the data output lines Q0Q11 when the LD pin is set LOW and REN is set LOW. Data can then be read on the next LOW-to-HIGH transition of RCLK. The first transition of RCLK will present the empty offset value to the data output lines. The next transition of RCLK will present the full offset value. Offset register content can be read out in the IDT Standard mode only. It cannot be read in the FWFT mode. REGISTER-BUFFERED FLAG OUTPUT SELECTION The IDT72V205/72V215/72V225/72V235/72V245 can be configured during the "Configuration at Reset" cycle described in Table 4 with single, double or triple register-buffered flag output signals. The various combinations available are described in Table 4 and Table 5. In general, going from single to double or triple buffered flag outputs removes the possibility of metastable flag indications on boundary states (i.e, empty or full conditions). The trade-off is the addition of clock cycle delays for the respective flag to be asserted. Not all combinations of register-buffered flag outputs are supported. Register-buffered outputs apply to the Empty Flag and Full Flag only. Partial flags are not effected. Table 4 and Table 5 summarize the options available. SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION The IDT72V205/72V215/72V225/72V235/72V245 can be configured during the "Configuration at Reset" cycle described in Table 3 with either asynchronous or synchronous timing for PAE and PAF flags. If asynchronous PAE/PAF configuration is selected (as per Table 3), the PAE is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing diagrams, see Figure 13 for asynchronous PAE timing and Figure 14 for asynchronous PAF timing. TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE IDT72V205 IDT72V215 Number of Words in FIFO IDT72V225 IDT72V235 IDT72V245 FF PAF HF PAE EF 0 0 0 0 0 H H H L L 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) H H H L H (n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1,024 (n + 1) to 2,048 H H H H H 129 to (256-(m+1))(2) 257 to (512-(m+1))(2) 513 to (1,024-(m+1))(2) 1,025 to (2,048-(m+1))(2) 2,049 to (4,096-(m+1))(2) H H L H H (256-m) to 255 (512-m) to 511 (1,024-m) to 1,023 (2,048-m) to 2,047 (4,096-m) to 4,095 H L L H H 256 512 1,024 2,048 4,096 L L L H H IDT72V235 IDT72V245 IR PAF HF PAE OR L NOTES: 1. n = Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127) 2. m = Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127) TABLE 2 — STATUS FLAGS FOR FWFT MODE IDT72V205 IDT72V215 0 Number of Words in FIFO IDT72V225 0 0 0 0 (1) 1 to (n + 1) 1 to (n + 1)(1) 1 to (n + 1)(1) 1 to (n + 1)(1) 1 to (n + 1)(1) L H (n + 2) to 129 (n + 2) to 257 (n + 2) to 513 (n + 2) to 1,025 (n + 2) to 2,049 L H L H L 130 to (257-(m+1))(2) 258 to (513-(m+1))(2) 514 to (1,025-(m+1))(2) 1,026 to (2,049-(m+1))(2) 2,050 to (4,097-(m+1))(2) H H L H H L L H H L H L (257-m) to 256 (513-m) to 512 (1,025-m) to 1,024 (2,049-m) to 2,048 (4,097-m) to 4,096 L L L H L 257 513 1,025 2,049 4,097 H L L H L NOTES: 1. n = Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127) 2. m = Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127) 7 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET FL RXI WXI 0 0 0 0 0 1 0 1 0 0(1) 1 1 1 0 0 1 0 1 1 1 0 1(2) 1 1 EF/OR Single register-buffered Empty Flag Triple register-buffered Output Ready Flag Double register-buffered Empty Flag Single register-buffered Empty Flag Single register-buffered Empty Flag Triple register-buffered Output Ready Flag Double register-buffered Empty Flag Single register-buffered Empty Flag FF/IR PAE, PAF Single register-buffered Full Flag Double register-buffered Input Ready Flag Double register-buffered Full Flag Single register-buffered Full Flag Single register-buffered Full Flag Double register-buffered Input Ready Flag Double register-buffered Full Flag Single register-buffered Full Flag FIFO Timing Mode Asynchronous Standard Asynchronous FWFT Asynchronous Standard Asynchronous Standard Synchronous Standard Synchronous FWFT Synchronous Standard Synchronous Standard NOTES: 1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device. 2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device. TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE Empty Flag (EF) Buffered Output Full Flag (FF) Buffered Output Partial Flags Timing Mode Programming at Reset FL RXI WXI Flag Timing Diagrams Single Single Asynch 0 0 0 Figure 9, 10 Single Single Sync 1 0 0 Figure 9, 10 Double Double Asynch 0 1 0 Figure 24, 26 Double Double Synch 1 1 0 Figure 24, 26 TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE Output Ready (OR) Input Ready (IR) Partial Flags Programming at Reset FL RXI WXI Flag Timing Diagrams Triple Double Asynch 0 0 1 Figure 27 Triple Double Sync 1 0 1 Figure 20, 21 8 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 SIGNAL DESCRIPTIONS: In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK + tSKEW after the first write. REN does not need to be asserted LOW. In order to access all other words, a read must be executed using REN. The RCLK LOW to HIGH transition after the last word has been read from the FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read operations. REN is ignored when the FIFO is empty. INPUTS: DATA IN (D0 - D17) Data inputs for 18-bit wide data. CONTROLS: RESET (RS) Reset is accomplished whenever the Reset (RS) input is taken to a LOW state. During reset, both internal read and write pointers are set to the first location. A reset is required after power-up before a write operation can take place. The Half-Full Flag (HF) and Programmable Almost-Full Flag (PAF) will be reset to HIGH after tRSF. The Programmable Almost-Empty Flag (PAE) will be reset to LOW after tRSF. The Full Flag (FF) will reset to HIGH. The Empty Flag (EF) will reset to LOW in IDT Standard mode but will reset to HIGH in FWFT mode. During reset, the output register is initialized to all zeros and the offset registers are initialized to their default values. OUTPUT ENABLE (OE) When Output Enable (OE) is enabled (LOW), the parallel output buffers receive data from the output register. When OE is disabled (HIGH), the Q output data bus is in a high-impedance state. LOAD (LD) The IDT72V205/72V215/72V225/72V235/72V245 devices contain two 12-bit offset registers with data on the inputs, or read on the outputs. When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH transition of the Write Clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full Offset register on the second LOW-to-HIGH transition of WCLK. The third transition of WCLK again writes to the Empty Offset register. However, writing all offset registers does not have to occur at one time. One or two offset registers can be written and then by bringing the LD pin HIGH, the FIFO is returned to normal read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. WRITE CLOCK (WCLK) A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock (WCLK). Data setup and hold times must be met with respect to the LOW-to-HIGH transition of WCLK. The Write and Read Clocks can be asynchronous or coincident. WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the IDT Standard Mode, FF will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF will go HIGH allowing a write to occur. The FF flag is updated on the rising edge of WCLK. To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR will go LOW allowing a write to occur. The IR flag is updated on the rising edge of WCLK. WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode. LD WEN 0 0 WCLK Selection Writing to offset registers: Empty Offset Full Offset 0 1 No Operation 1 0 Write Into FIFO 1 1 No Operation NOTE: 1. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK. READ CLOCK (RCLK) Data can be read on the outputs on the LOW-to-HIGH transition of the Read Clock (RCLK), when Output Enable (OE) is set LOW. The Write and Read Clocks can be asynchronous or coincident. Figure 2. Writing to Offset Registers 17 0 11 EMPTY OFFSET REGISTER READ ENABLE (REN) When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. In the IDT Standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN. When the last word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF will go HIGH allowing a read to occur. The EF flag is updated on the rising edge of RCLK. DEFAULT VALUE 001FH (72V205) 003FH (72V215): 007FH (72V225/72V235/72V245) 17 11 0 FULL OFFSET REGISTER DEFAULT VALUE 001FH (72V205) 003FH (72V215): 007FH (72V225/72V235/72V245) 4294 drw 04 NOTE: 1. Any bits of the offset register not being programmed should be set to zero. Figure 3. Offset Register Location and Default Values 9 IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled; then a signal at this input can neither increment the write offset register pointer, nor execute a write. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOWto-HIGH transition of the Read Clock (RCLK). The act of reading the control registers employs a dedicated read offset register pointer. (The read and write pointers operate independently). Offset register content can be read out in the IDT Standard mode only. It is inhibited in the FWFT mode. A read and a write should not be performed simultaneously to the offset registers. FIRST LOAD (FL) For the single device mode, see Table 3 for additional information. In the Daisy Chain Depth Expansion configuration, FL is grounded to indicate it is the first device loaded and is set to HIGH for all other devices in the Daisy Chain. (See Operating Configurations for further details.) WRITE EXPANSION INPUT (WXI) This is a dual purpose pin. For single device mode, see Table 3 for additional information. WXI is connected to Write Expansion Out (WXO) of the previous device in the Daisy Chain Depth Expansion mode. READ EXPANSION INPUT (RXI) This is a dual purpose pin. For single device mode, see Table 3 for additional information. RXI is connected to Read Expansion Out (RXO) of the previous device in the Daisy Chain Depth Expansion mode. OUTPUTS: FULL FLAG/INPUT READY (FF/IR) This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function is selected. When the FIFO is full, FF will go LOW, inhibiting further write operations. When FF is HIGH, the FIFO is not full. If no reads are performed after a reset, FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. IR will go HIGH after D writes to the FIFO. D = 257 writes for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. FF/IR is synchronous and updated on the rising edge of WCLK. EMPTY FLAG/OUTPUT READY (EF/OR) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF) function is selected. When the FIFO is empty, EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes LOW again. EF/OR is synchronous and updated on the rising edge of RCLK. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES PROGRAMMABLE ALMOST-FULL FLAG (PAF) The Programmable Almost-Full Flag (PAF) will go LOW when FIFO reaches the almost-full condition. In IDT Standard mode, if no reads are performed after Reset (RS), the PAF will go LOW after (256-m) writes for the IDT72V205, (512-m) writes for the IDT72V215, (1,024-m) writes for the IDT72V225, (2,048–m) writes for the IDT72V235 and (4,096–m) writes for the IDT72V245. The offset “m” is defined in the Full Offset register. In FWFT mode, if no reads are performed, PAF will go LOW after 257-m for the IDT72V205, 513-m for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. The default values for m are noted in Table 1 and 2. If asynchronous PAF configuration is selected, the PAF is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF configuration is selected (see Table 3), the PAF is updated on the rising edge of WCLK. PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) The PAE flag will go LOW when the FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW when there are n words or less in the FIFO. In FWFT mode, the PAE will go LOW when there are n + 1 words or less in the FIFO. The offset "n" is defined as the empty offset. The default values for n are noted in Table 1 and 2. If there is no empty offset specified, the Programmable Almost-Empty Flag (PAE) will be LOW when the device is 31 away from completely empty for IDT72V205, 63 away from completely empty for IDT72V215, and 127 away from completely empty for IDT72V225/72V235/72V245. If asynchronous PAE configuration is selected, the PAE is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE configuration is selected (see Table 3), the PAE is updated on the rising edge of RCLK. WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF) This is a dual-purpose output. In the Single Device and Width Expansion mode, when Write Expansion In (WXI) and/or Read Expansion In (RXI) are grounded, this output acts as an indication of a half-full memory. After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is asynchronous. In the Daisy Chain Depth Expansion mode, WXI is connected to WXO of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device writes to the last location of memory. READ EXPANSION OUT (RXO) In the Daisy Chain Depth Expansion configuration, Read Expansion In (RXI) is connected to Read Expansion Out (RXO) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse when the previous device reads from the last location of memory. DATA OUTPUTS (Q0-Q17) Q0-Q17 are data outputs for 18-bit wide data. 10 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 tRS RS tRSR REN, WEN, LD tRSS (1) FL, RXI, WXI RCLK, WCLK tRSR CONFIGURATION SETTING (4) (2) tRSF IDT Standard Mode FF/IR FWFT Mode tRSF FWFT Mode EF/OR IDT Standard Mode tRSF PAF, WXO/ HF, RXO tRSF PAE tRSF (3) OE = 1 Q0 - Q17 OE = 0 NOTES: 1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND). 2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally. 3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1. 4. In FWFT mode IR goes LOW based on the WCLK edge after Reset. 4294 drw 05 Figure 5. Reset Timing(2) tCLKH tCLK tCLKL WCLK tDS tDH D0 - D17 DATA IN VALID tENS tENH NO OPERATION WEN tWFF tWFF FF tSKEW1 (1) RCLK REN 4294 drw 06 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. 2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset. Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode) 11 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 tCLK tCLKH tCLKL RCLK tENS tENH NO OPERATION REN tREF tREF EF tA Q0 - Q17 VALID DATA tOLZ tOHZ tOE OE (1) tSKEW1 WCLK WEN 4294 drw 07 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. 2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset. Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode) WCLK tDS D0 - D17 D0 (first valid write) D1 D2 D3 tA tA D4 tENS WEN tFRL (1) tSKEW1 RCLK tREF EF tENS REN Q0 - Q17 D0 D1 tOLZ tOE OE 4294 drw 08 NOTES: 1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 2. The first word is available the cycle after EF goes HIGH, always. 3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset. Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode) 12 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 NO WRITE WCLK NO WRITE (1) tSKEW1 (1) tSKEW1 tDS D0 - D17 tDS DATA WRITE DATA WRITE tWFF tWFF tWFF FF WEN RCLK tENS tENH tENS tENH REN OE LOW tA tA Q0 - Q17 DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ 4294 drw 09 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge. 2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset. Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode) WCLK tDS tDS DATA WRITE 1 D0 - D17 tENS DATA WRITE 2 tENS tENH tENH WEN (1) tFRL tFRL (1) tSKEW1 tSKEW1 RCLK tREF tREF tREF EF REN OE LOW tA Q0 - Q17 DATA READ DATA IN OUTPUT REGISTER 4294 drw 10 NOTES: 1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW1, or tCLK + tSKEW1. The Latency Timing apply only at the Empty Boundary (EF = LOW). 2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset. Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode) 13 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 tCLK tCLKH tCLKL WCLK tENS tENH LD tENS WEN tDS tDH PAE OFFSET D0 - D15 PAE OFFSET PAF OFFSET D0 - D11 4294 drw 11 Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes) tCLKH tCLK tCLKL RCLK tENS tENH LD tENS REN tA Q0 - Q15 PAE OFFSET UNKNOWN PAE OFFSET PAF OFFSET 4294 drw 12 Figure 12. Read Programmable Registers (IDT Standard Mode) tCLKH tCLKL WCLK tENS tENH WEN PAE tPAEA n words in FIFO(2), n + 1 words in FIFO(3) n + 1 words in FIFO(2), n + 2 words in FIFO(3) n words in FIFO(2), n + 1 words in FIFO(3) tPAEA RCLK tENS REN NOTES: 1. n = PAE offset. 2. For IDT Standard Mode. 3. For FWFT Mode. 4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition. 5. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset. Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) 14 4294 drw 13 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 tCLKH tCLKL WCLK tENS tENH WEN tPAFA PAF D - m words in FIFO D - (m + 1) words in FIFO (1) D - (m + 1) words in FIFO tPAFA RCLK tENS REN 4294 drw 14 NOTES: 1. m = PAF offset. 2. D = maximum FIFO Depth. In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. 3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition. 4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset. Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK tENH tENS WEN tHF HF D/2 + 1 words in FIFO(2), D/2 words in FIFO(2), [D-1 2 [D-1 2 ] + 1 words in FIFO(3) ] + 2 words in FIFO(3) D/2 words in FIFO(2), [D-1 2 ] + 1 words in FIFO(3) tHF RCLK tENS REN 4294 drw 15 NOTES: 1. D = maximum FIFO Depth. In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. 2. For IDT Standard Mode. 3. For FWFT Mode. 4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset. Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes) 15 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 tCLKH WCLK Note 1 tXO tXO WXO tENS WEN 4294 drw 16 NOTE: 1. Write to Last Physical Location. Figure 16. Write Expansion Out Timing tCLKH RCLK Note 1 tXO tXO RXO tENS REN 4294 drw 17 NOTE: 1. Read from Last Physical Location. Figure 17. Read Expansion Out Timing tXI WXI tXIS WCLK 4294 drw 18 Figure 18. Write Expansion In Timing tXI RXI tXIS RCLK 4294 drw 19 Figure 19. Read Expansion In Timing 16 17 tDS W1 tENS W2 2 DATA IN OUTPUT REGISTER 1 tSKEW1 tDH W3 3 tREF tA W4 tDS W[n +2] 1 W[n+3] tPAES tSKEW2 (2) W[n+4] W[ D-1 2 ] +1 tDS W[ D-1 2 ] +2 tHF W[ D-1 2 W1 ] +3 W[D-m-2] tDS W[D-m-1] W[D-m] W[D-m+1] tPAFS 1 W[D-m+2] W[D-1] WD 4294 drw 20 tWFF tENH Figure 20. Write Timing with Synchronous Programmable Flags (FWFT Mode) NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WLCK and the rising edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 3. LD = HIGH, OE = LOW 4. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 257 words for the IDT72V205, 513 words for the IDT72V215, 1,025 words for the IDT72V225, 2,049 words for the IDT72V235 and 4,097 words for the IDT72V245. 5. Select this mode by setting (FL, RXI, WXI) = (1,0,1) during Reset. IR PAF HF PAE OR Q0 - Q17 REN RCLK D0 - D17 WEN WCLK IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 18 tDS tENS W1 tOHZ WD tENS tWFF tDH tENH W1 tOE tA W2 1 (1) tSKEW1 tA 2 tWFF W3 (2) Wm+2 tSKEW2 tPAFS W[m+3] tA W[m+4] W[ D-1 ] tHF W[ tA D-1 ] W[D-n-1] tA W[D-n] 1 tPAES W[D-n+1] W[D-n+2] W[D-1] tA tENS WD 4294 drw 21 tREF Figure 21. Read Timing with Synchronous Programmable Flags (FWFT Mode) NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK plus tWFF. If the time between the rising edge of RLCK and the rising edge of WCLK is less than tSKEW1, then the IR assertion may be delayed an extra WCLK cycle. 2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle. 3. LD = HIGH 4. n = PAE offset, m = PAF offset, D = maximum FIFO depth = 257 words for the IDT72V205, 513 words for the IDT72V215, 1,025 words for the IDT72V225, 2,049 words for IDT72V235 and 4,097 words for IDT72V245. 5. Select this mode by setting (FL, RXI, WXI) = (1,0,1) during Reset. IR PAF HF PAE OR Q0 - Q17 OE REN RCLK D0 - D17 WEN WCLK IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 tCLKH tCLKL WCLK tENS tENH WEN PAE n words in FIFO(2), n + 1words in FIFO(3) n Words in FIFO(2), n + 1 words in FIFO(3) n + 1 words in FIFO(2), n + 2 words in FIFO(3) tSKEW2 (4) tPAES tPAES RCLK tENS tENH REN 4294 drw 22 NOTES: 1. n = PAE offset. 2. For IDT Standard Mode. 3. For FWFT Mode. 4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle. 5. PAE is asserted and updated on the rising edge of RCLK only. 6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset. Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) tCLKH tCLKL WCLK tENS tENH WEN tPAFS PAF PAFS ttPAFS D - (m + 1) Words in FIFO D - (m + 1) Words in FIFO D - m Words in FIFO tSKEW2(3) RCLK tENS tENH REN 4294 drw 23 NOTES: 1. m = PAF offset. 2. D = maximum FIFO Depth. In IDT Standard Mode: D = 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT Mode: D = 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. 3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle. 4. PAF is asserted and updated on the rising edge of WCLK only. 5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset. Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes) 19 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 NO WRITE NO WRITE WCLK 2 1 1 tDS (1) tSKEW1 2 (1) tSKEW1 D0 - D17 DATA WRITE tDS Wd tWFF tWFF tWFF FF WEN RCLK tENH tENS tENS tENH REN OE LOW tA tA Q0 - Q17 DATA IN OUTPUT REGISTER NEXT DATA READ DATA READ 4294 drw 24 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle. 2. LD = HIGH. 3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset. Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode) tCLK t CLKH WCLK 1 tCLKL 2 tDS tDH D0 - D17 DATA IN VALID tENS tENH WEN NO OPERATION tWFF tWFF FF tSKEW1(1) RCLK REN 4294 drw 25 NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1. then the FF deassertion may be delayed an extra WCLK cycle. 2. LD = HIGH. 3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset. Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode) 20 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 tCLK tCLKH 1 RCLK tCLKL 2 tENH tENS REN NO OPERATION tREF tREF EF tA Q0 - Q17 LAST WORD tOLZ tOHZ tOE OE (1) tSKEW1 WCLK tENH tENS WEN tDH tDS D0 - D17 FIRST WORD 4294 drw 26 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle. 2. LD = HIGH 3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset. Figure 26. Read Cycle Timing with Double Register-Buffered EF (IDT Standard Timing) WCLK tENH tENS WEN tDS D0 - D17 tDH W1 tDS W2 t SKEW1 RCLK W3 W4 W[n+3] W[n +2] (1) 1 2 3 REN tA Q0 - Q17 W1 DATA IN OUTPUT REGISTER tREF tREF OR 4294 drw 27 NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the rising edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle. 2. LD = HIGH, OE = LOW 3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset. Figure 27. OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode) 21 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 OPERATING CONFIGURATIONS These FIFOs are in a single Device Configuration when the First Load (FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure 28). SINGLE DEVICE CONFIGURATION A single IDT72V205/72V215/72V225/72V235/72V245 may be used when the application requirements are for 256/512/1,024/2,048/4,096 words or less. RESET (RS) WRITE CLOCK (WCLK) READ CLOCK (RCLK) WRITE ENABLE (WEN) READ ENABLE (REN) LOAD (LD) OUTPUT ENABLE (OE) IDT 72V205 72V215 72V225 72V235 72V245 DATA IN (D0 - D17) FULL FLAG/INPUT READY (FF/IR) DATA OUT (Q0 - Q17) EMPTY FLAG/OUTPUT READY (EF/OR) PROGRAMMABLE (PAE) PROGRAMMABLE (PAF) HALF-FULL FLAG (HF) FL RXI WXI 4294 drw 28 Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting together the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the Empty Flag/Output Ready and Full Flag/Input Ready. Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and deassertion to vary by one cycle between FIFOs. To avoid problems the user must create composite flags by gating the Empty Flags/Output Ready of every FIFO, and separately gating all Full Flags/Input Ready. Figure 29 demonstrates a 36-word width by using two IDT72V205/72V215/72V225/ 72V235/72V245s. Any word width can be attained by adding additional IDT72V205/72V215/72V225/72V235/72V245s. These FIFOs are in a single Device Configuration when the First Load (FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure 29). Please see the Application Note AN-83. RESET (RS) RESET (RS) DATA IN (D) 36 18 18 READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN) WRITE ENABLE (WEN) OUTPUT ENABLE (OE) LOAD (LD) PROGRAMMABLE (PAE) HALF FULL FLAG (HF) FULL FLAG/INPUT READY (FF/IR) 72V205 72V215 72V225 72V235 72V245 72V205 72V215 72V225 72V235 72V245 FF/IR EF/OR FL FF/IR FL WXI RXI PROGRAMMABLE (PAF) EMPTY FLAG/OUTPUT READY (EF/OR) EF/OR WXI RXI 18 DATA OUT (Q) 36 18 4294 drw 29 NOTE: 1. Do not connect any output control signals directly together. Figure 29. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36 Synchronous FIFO Memory Used in a Width Expansion Configuration 22 IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requiring more than 256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth Expansion using three IDT72V205/72V215/72V225/72V235/72V245s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. See Figure 30. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. See Figure 30. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in this Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together every respective flags for monitoring. The composite PAE and PAF flags are not precise. 8. In Daisy Chain mode, the flag outputs are single register-buffered and the partial flags are in asynchronous timing mode. WXO RXO WCLK WEN RS LD RCLK REN OE IDT 72V205 72V215 72V225 72V235 72V245 Dn Vcc Qn FL FF/IR PAF EF/OR PAE WXI RXI WXO RXO WCLK WEN RCLK RS REN OE LD IDT 72V205 72V215 72V225 72V235 72V245 Dn DATA IN Vcc DATA OUT Qn FL FF/IR PAF EF/OR PAE WXI RXI WRITE CLOCK WRITE ENABLE WXO RXO WCLK RCLK READ CLOCK WEN READ ENABLE RS Dn RESET LD LOAD FF/IR FF/IR PAF REN IDT 72V205 72V215 72V225 72V235 72V245 OE Qn OUTPUT ENABLE EF/OR EF/OR PAE PAF WXI RXI PAE FIRST LOAD (FL) 4294 drw 30 Figure 30. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration 23 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 specification is not met between WCLK and transfer clock, or RCLK and transfer clock, for the OR flag. The “ripple down” delay is only noticeable for the first word written to an empty depth expansion configuration. There will be no delay evident for subsequent words written to the configuration. The first free location created by reading from a full depth expansion configuration will “bubble up” from the last FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling the preceding FIFO to write a word to fill it. For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for each individual FIFO: DEPTH EXPANSION CONFIGURATION (FWFT MODE) In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 31 shows a depth expansion using two IDT72V205/72V215/72V225/72V235/72V245 devices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next (“ripple down”) until it finally appears at the outputs of the last FIFO in the chain–no read operation is necessary but the RCLK of each FIFO must be free-running. Each time the data word appears at the outputs of one FIFO, that device’s OR line goes LOW, enabling a write to the next FIFO in line. For an empty expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum of the delays for each individual FIFO: (N – 1)*(3*transfer clock) + 2 TWCLK where N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and transfer clock, for the IR flag. The Transfer Clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain. (N – 1)*(4*transfer clock) + 3*TRCLK where N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 HF PAF WRITE CLOCK TRANSFER CLOCK WCLK WRITE ENABLE WEN INPUT READY IR DATA IN n HF PAE Dn RCLK OR 72V205 72V215 72V225 72V235 72V245 REN OE FL RXI WXI (0,1) GND VCC Qn RCLK WEN REN READ ENABLE OR OUTPUT READY 72V205 72V215 72V225 72V235 72V245 IR GND OE OUTPUT ENABLE n Dn FL RXI (0,1) GND WXI Qn n DATA OUT 4294 drw 31 VCC Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous FIFO Memory With Programmable Flags used in Depth Expansion Configuration 24 READ CLOCK WCLK ORDERING INFORMATION XXXXX X Device Type Power XX Speed X X Package X X Process / Temperature Range Blank 8 Tube or Tray Tape and Reel BLANK I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G(2) Green PF TF Thin Plastic Quad Flatpack (TQFP, PN64-1) Slim Thin Plastic Quad Flatpack (STQFP, PP64-1) 10 15 20 Commercial Only Com'l & Ind'l Commercial Only L Low Power 72V205 72V215 72V225 72V235 72V245 256 x 18 ⎯ 3.3V SyncFIFO 512 x 18 ⎯ 3.3V SyncFIFO 1,024 x 18 ⎯ 3.3V SyncFIFO 2,048 x 18 ⎯ 3.3V SyncFIFO 4,096 x 18 ⎯ 3.3V SyncFIFO Clock Cycle Time (tCLK) Speed in Nanoseconds 4294 drw 32 NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are available. For specific speeds and packages contact your sales office. LEAD FINISH (SNPB) PARTS ARE IN EOL PROCESS. PRODUCT DISCONTINUATION NOTICE - PDN# SP-17-02 DATASHEET DOCUMENT HISTORY 05/02/2001 01/11/2002 02/01/2002 02/22/2006 10/22/2008 03/21/2013 03/19/2018 pgs. 4, 5 and 25. pg. 4. pg. 4. pgs. 1 and 25. pg. 25. pg. 2 and 25. Product Discontinuation Notice - PDN# SP-17-02 Last time buy expires June 15, 2018. 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