72V3613L20PF8

3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 FEATURES: • • • • • • • • • • • • • • • • 64 x 36 storage capacity FIFO buffering data from Port A to Port B Supports clock frequencies up to 67MHz Fast access times of 10ns Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) Mailbox bypass registers in each direction Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word), and 9 bits (byte) Selection of Big- or Little-Endian format for word and byte bus sizes Three modes of byte-order swapping on Port B Programmable Almost-Full and Almost-Empty flags Microprocessor interface control logic FF , AF flags synchronized by CLKA EF , AE flags synchronized by CLKB IDT72V3613 OBSOLETE PART Passive parity checking on each Port Parity Generation can be selected for each Port Available in space saving 120-pin thin quad flat package (TQFP) Green parts available, see ordering information DESCRIPTION: The IDT72V3613 is designed to run off a 3.3V supply for exceptionally lowpower consumption. This device is a monolithic, high-speed, low-power, CMOS synchronous (clocked) FIFO memory which supports clock frequencies up to 67 MHz and has read-access times as fast as 10 ns. The 64 x 36 dualport SRAM FIFO buffers data from port A to port B. The FIFO operates in IDT Standard mode and has flags to indicate empty and full conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number of words is stored in memory. FIFO data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of Big- or Little-Endian configurations. Three modes of byte-order swapping are possible with any bussize selection. Communication between each port can bypass the FIFO via two R T O R F A P ED E D T S N E N E L G M O I S S M B E O D O EC R EW T N O N FUNCTIONAL BLOCK DIAGRAM RAM ARRAY 64 x 36 36 Write Pointer FF AF Output Register PGB Parity Generation ODD/ EVEN Device Control MBF1 PEFB Parity Gen/Check Mail 1 Register Input Register RST Port-A Control Logic Bus-Matching Outputand Byte Swapping Register CLKA CSA W/RA ENA MBA 36 Read Pointer B0 - B35 Status Flag Logic FIFO FS0 FS1 A0 - A35 Programmable Flag Offset Registers PGA PEFA MBF2 Parity Gen/Check Mail 2 Register 64 x 36 Port-B Port-B Control Control Logic Logic EF AE CLKB CSB W/RB ENB BE SIZ0 SIZ1 SW0 SW1 4661 drw 01 COMMERCIAL TEMPERATURE RANGE JANUARY 2014 1 DSC-4661/5 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous interfaces. The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage synchronized to the port clock (CLKA) that writes data into its array. The Empty Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized to the port clock (CLKB) that reads data from its array. The IDT72V3613 is characterized for operation from 0°C to 70°C. This device is fabricated using high speed, submicron CMOS technology. 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices may be used in parallel to create wider data paths. The IDT72V3613 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0 EF AE NC NOTES: 1. Pin 1 idenifier in corner. 2. NC = No internal connection AF FF CSA ENA CLKA W/RA VCC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND BE SW1 SW0 SIZ1 SIZ0 MBF1 PEFB PGB VCC W/RB CLKB ENB CSB NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 NC NC TQFP (PNG120, order code: PF) TOP VIEW 2 4661 drw 02 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol Name I/O I/O Description A0-A35 Port A Data AE Almost-Empty Flag O Port B Programmable Almost-Empty flag synchronized to CLKB. It is LOW when Port B the number of 36-bit words in the FIFO is less than or equal to the value in the offset register, X. AF Almost-Full Flag O Port A Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty empty locations in the FIFO is less than or equal to the value in the offset register, X. B0-B35 Port B Data BE Big-Endian Select I Selects the bytes on port B used during byte or word FIFO reads. A LOW on BE selects the most significant bytes on B0-B35 for use, and a HIGH selects the least significant bytes. CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the LOW-to-HIGH transition of CLKB. EF and AE are synchronized to the LOW-to-HIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0B35 outputs are in the high-impedance state when CSB is HIGH. EF Empty Flag ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. FF Full Flag I/O O Port B O Port A 36-bit bidirectional data port for side A. 36-bit bidirectional data port for side B EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty, and reads from its memory are disabled. Data can be read from the FIFO to its output register when EF is HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO memory. FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. FS1, FS0 Flag Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four preset values into the Almost-Full flag and Almost-Empty flag offsets. MBA Port A Mailbox Select I A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, mail2 register data is output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the device is reset. MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset. ODD/ EVEN Odd/Even Parity Select I Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. PEFA Port A Parity Error Flag O When any valid byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes (Port A) are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of the A0-A35 inputs. 3 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (CONTINUED) Symbol PEFB Name Port B Parity Error Flag I/O Description O When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as (Port B) B0-B8, B9-B17, B-18-B26, and B27-B35, with the most significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs. PGA Port A Parity Generation I Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized at A0-A8, A9-A17, A18A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. PGB Port B Parity Generation I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-Full flag and Almost-Empty flag offset. SIZ0, SIZ1 Port B Bus Size Selects I A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to(Port B) HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long word, word, or byte. A HIGH on both SIZ0 and SIZ1 chooses a mailbox register for a port B 36-bit write or read. SW0, SW1 Port B Byte Swap Selects I At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by (Port B) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection. W/RA Port A Write/Read Select I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. W/RB Port B Write/Read Select I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH. 4 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise noted)(1) Symbol Rating Commercial Unit –0.5 to +4.6 V V CC Supply Voltage Range VI Input Voltage Range –0.5 to VCC+0.5 V VO Output Voltage Range –0.5 to VCC+0.5 V IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA IOK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA I OUT Continuous Output Current, (VO = 0 to VCC) ±50 mA I CC Continuous Current Through VCC or GND ±500 mA T STG Storage Temperature Range –65 to 150 °C (2) (2) NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Min. Typ. Max. Unit 3.0 3.3 3.6 V V VIH HIGH Level Input Voltage 2 — VCC+0.5 VIL LOW-Level Input Voltage — — 0.8 V IOH HIGH-Level Output Current — — –4 mA IOL LOW-Level Output Current — — 8 mA TA Operating Free-air Temperature 0 — 70 °C ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise noted) Symbol VOH Test Conditions IOH = –4 mA IDT72V3613 Commercial tCLK = 15 ns Min. Typ.(1) Max. 2.4 — — Parameter Output Logic "1" Voltage VCC = 3.0V, VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V ILI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 µA ILO Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 µA ICC(2) Standby Current VCC = 3.6V, VI = VCC - 0.2V or 0 — — 500 µA CIN Input Capacitance VI = 0, f = 1 MHz — 4 — pF C OUT Output Capacitance VO = 0, f = 1 MHZ — 8 — pF NOTES: 1. All typical values are at VCC = 3.3V, TA = 25°C. 2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS). 5 Unit V IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3613 with CLKA and CLKB set to fS. All date inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3613 may be calculated by: PT = VCC x ICC(f) + Σ(CL x (VOH - VOL)2 x fo) N where: N CL fo VOH VOL = = = = = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus-size) output capacitance load switching frequency of an output output high-level voltage output high-level voltage When no reads or writes are occurring on the IDT72V3613, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated by: PT = VCC x fS x 0.025mA/MHz 175 150 fdata = 1/2 fS 125 mA TA = 25°C VCC = 3.6V Supply Current 100 ICC(f) CL = 0 pF 50 VCC = 3.3V VCC = 3.0V 75 25 0 0 10 20 30 40 50 60 70 fS ⎯ Clock Frequency ⎯ MHz Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS) 6 80 90 4661 drw 04 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial: Vcc=3.3V± 0.30V; TA = 0°C to +70°C; JEDEC JESD8-A compliant Symbol IDT72V3613L15 Min. Max. Parameter Unit fS Clock Frequency, CLKA or CLKB – 66.7 MHz tCLK Clock Cycle Time, CLKA or CLKB 15 – ns tCLKH Pulse Duration, CLKA and CLKB HIGH 6 – ns tCLKL Pulse Duration, CLKA and CLKB LOW 6 – ns tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 4 – ns tENS Setup Time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB, W/RB, and ENB before CLKB↑ 5 – ns tSZS Setup Time, SIZ0, SIZ1, and BE before CLKB↑ 4 – ns tSWS Setup Time, SW0 and SW1 before CLKB↑ tPGS Setup Time, ODD/EVEN and PGB before CLKB↑ tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑ tFSS 6 – ns (1) 4 – ns (2) 5 – ns Setup Time, FS0 and FS1 before RST HIGH 5 – ns tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 1 – ns tENH Hold Time, CSA W/RA, ENA and MBA after CLKA↑; CSB, W/RB, and ENB after CLKB↑ 1 – ns tSZH Hold Time, SIZ0, SIZ1, and BE after CLKB↑ 2 – ns tSWH Hold Time, SW0 and SW1 after CLKB↑ 2 – ns tPGH Hold Time, ODD/EVEN and PGB after CLKB↑ 0 – ns tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑ 5 – ns Hold Time, FS0 and FS1 after RST HIGH 4 – ns Skew Time, between CLKA↑ and CLKB↑ for EF and FF 8 – ns Skew Time, between CLKA↑ and CLKB↑ for AE and AF 14 – ns (1) (2) tFSH tSKEW1 (3) tSKEW2 (3,4) NOTES: 1. Only applies for a clock edge that does a FIFO read. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested. 7 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF Commercial: Vcc=3.3V± 0.30V; TA = 0°C to +70°C; JEDEC JESD8-A compliant Symbol IDT72V3613L15 Min. Max. Parameter Unit tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 10 ns tWFF Propagation Delay Time, CLKA↑ to FF 2 10 ns tREF Propagation Delay Time, CLKB↑ to EF 2 10 ns tPAE Propagation Delay Time, CLKB↑ to AE 2 10 ns tPAF Propagation Delay Time, CLKA↑ to AF 2 10 ns tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH 1 9 ns tPMR Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2) 2 10 ns tPPE Propagation delay time, CLKB↑ to PEFB 2 10 ns tMDV Propagation Delay Time, SIZ1, SIZ0 to B0-B35 valid 1 10 ns tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 2 10 ns Propagation Delay Time, ODD/EVEN to PEFA and PEFB 2 10 ns tPOPB Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) 2 10 ns tPEPE Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB 1 10 ns tPEPB(4) Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35); CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35) 2 10 ns tRSF Propagation Delay Time, RST to AE, EF LOW and AF, MBF1, MBF2 HIGH 1 15 ns tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to B0-B35 active 2 10 ns tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or W/RB LOW to B0-B35 at high-impedance 1 8 ns (3) tPOPE (4) NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1 and SIZ0 are HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active. 3. Only applies when a new port-B bus size is implemented by the rising CLKB edge. 4. Only applies when reading data from a mail register. 8 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE FUNCTIONAL DESCRIPTION Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FF is HIGH (see Table 2). The relevant FIFO write timing diagram can found in Figure 6. The state of the port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB) and the port B Write/Read select (W/RB). The B0-B35 outputs are in the high-impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are active when both CSB and W/RB are LOW. Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3). Relevant FIFO read timing diagrams together with Bus-Matching, Endian select and Byte-swapping operation can be found in Figures 7, 8 and 9. The setup and hold-time constraints to the port clocks for the port Chip Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select and Write/ Read select can change states during the setup and hold time window of the cycle. RESET (RST) The IDT72V3613 is reset by taking the Reset (RST) input LOW for at least four port A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH transitions. The Reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of the FIFO and forces the Full Flag (FF) LOW, the Empty Flag (EF) LOW, the Almost-Empty flag (AE) LOW, and the Almost-Full flag (AF) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FF is set HIGH after two LOW-to-HIGH transitions of CLKA. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the Almost-Full and Almost-Empty Offset register (X) with the value selected by the Flag Select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1. See Figure 5 for relevant FIFO Reset and preset value loading timing diagram. FIFO WRITE/READ OPERATION The state of the port A data (A0-A35) outputs is controlled by the port-A Chip Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0A35 outputs are active when both CSA and W/RA are LOW. SYNCHRONIZED FIFO FLAGS Each FIFO flag is synchronized to its port clock through two flip-flop stages. This is done to improve the flags’ reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB. Table 4 shows the relationship of each port flag to the level of FIFO fill. TABLE 1 – FLAG PROGRAMMING FS1 FS0 RST H H L L H L H L ↑ ↑ ↑ ↑ ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) 16 12 8 4 EMPTY FLAG (EF) The FIFO Empty Flag is synchronized to the port clock that reads data from its array (CLKB). When the EF is HIGH, new data can be read to the FIFO output register. When the EF is LOW, the FIFO is empty and attempted FIFO reads TABLE 2 – PORT A ENABLE FUNCTION TABLE CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O Port Function H X X X X Input None L L L L L L L H H H L L L L L H H L H L H X L H L L H H X Input Input Input Output Output Output Output None FIFO write Mail1 write None None None Mail2 read (set MBF2 HIGH) ↑ ↑ X ↑ X ↑ TABLE 3 – PORT B ENABLE FUNCTION TABLE CSB W/RB ENB SIZ1, SIZ0 CLKB Data B (B0-B35) I/O Port Function H X X X X Input None L L L L L L L H H H L L L L L H H L H L H X One, both LOW Both HIGH One, both LOW One, both LOW Both HIGH Both HIGH X ↑ ↑ X ↑ X ↑ Input Input Input Output Output Output Output None None Mail2 write None FIFO read None Mail1 read (set MBF1 HIGH) 9 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE are ignored. When reading the FIFO with a byte or word size on port B, EF is set LOW when the fourth byte or second word of the last long word is read. The FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls the EF monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. A word written to the FIFO can be read to the FIFO output register in a minimum of three port B clock (CLKB) cycles. Therefore, an EF is LOW if a word in memory is the next data to be sent to the FIFO output register and two CLKB cycles have not elapsed since the time the word was written. The EF of the FIFO is set HIGH by the second LOW-to-HIGH transition of CLKB, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 10). X or less long words in memory and is HIGH when the FIFO contains (X+1) or more long words. Two LOW-to-HIGH transitions on the port B Clock (CLKB) are required after a FIFO write for the AE flag to reflect the new level of fill. Therefore, the AE flag of a FIFO containing (X+1) or more long words remains LOW if two CLKB cycles have not elapsed since the write that filled the memory to the (X+1) level. The AE flag is set HIGH by the second CLKB LOW-to-HIGH transition after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of CLKB begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle (see Figure 12). ALMOST FULL FLAG (AF) The FIFO Almost-Full flag is synchronized to the port clock that writes data to its array (CLKA). The state machine that controls an AF flag monitors a writepointer and read-pointer comparator that indicates when the FIFO memory status is almost -full, almost- full-1, or almost-full-2. The almost-full state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset section). The AF flag is LOW when the FIFO contains (64-X) or more long words in memory and is HIGH when the FIFO contains [64-(X+1)] or less long words. Two LOW-to-HIGH transitions on the port A Clock (CLKA) are required after a FIFO read for the AF flag to reflect the new level of fill. Therefore, the AF flag of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA cycles have not elapsed since the read that reduced the number of long words in memory to [64-(X+1)]. The AF flag is set HIGH by the second CLKA LOW-toHIGH transition after the FIFO read that reduces the number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of long words in memory to [64-(X+1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see Figure 13). FULL FLAG (FF) The FIFO Full Flag is synchronized to the port clock that writes data to its array (CLKA). When the FF is HIGH, a FIFO memory location is free to receive new data. No memory locations are free when the FF is LOW and attempted writes to the FIFO are ignored. Each time a word is written to the FIFO, its write-pointer is incremented. The state machine that controls the FF monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is full, full-1, or full-2. From the time a word is read from the FIFO, its previous memory location is ready to be written in a minimum of three CLKA cycles. Therefore, a FF is LOW if less than two CLKA cycles have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the FF synchronizing clock after the read sets the FF HIGH and data can be written in the following clock cycle. A LOW-to-HIGH transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 11). MAILBOX REGISTERS Two 36-bit bypass registers (mail1, mail2) are on the IDT72V3613 to pass command and control information between port A and port B without putting it in queue. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A write is selected by CSA, W/RA, and ENA with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when a port B write is selected by CSB, W/RB and ENB, and both SIZ0 and SIZ1 are HIGH. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while its mail flag is LOW. When the port B data (B0-B35) outputs are active, the data on the bus comes from the FIFO output register when either one or both SIZ1 and SIZ0 are LOW and from the mail1 register when both SIZ1 and SIZ0 are HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a rising CLKB edge when a port B read is selected by CSB, W/RB, and ENB, and both SIZ1 and SIZ0 HIGH. The Mail2 Register Flag (MBF2) is set HIGH by a rising CLKA edge when a port A read is selected by CSA, W/RA, and ENA with MBA HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. See Figure 14 and 15 for relevant mail register and mail register flag timing diagrams. ALMOST-EMPTY FLAG (AE) The FIFO Almost-Empty flag is synchronized to the port clock that reads data from its array (CLKB). The state machine that controls the AE flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four preset values during a device reset (see reset above). The AE flag is LOW when the FIFO contains TABLE 4 – FIFO FLAG OPERATION NUMBER OF 36-BIT WORDS IN THE FIFO(1) 0 1 to X (X+ 1) to [64 - (X + 1)] (64 - X) to 63 64 SYNCHRONIZED TO CLKB SYNCHRONIZED TO CLKA EF AE AF FF L H H H H L L H H H H H H L L H H H H L DYNAMIC BUS SIZING The port B bus can be configured in a 36-bit long word, 18-bit word, or 9bit byte format for data read from the FIFO. Word- and byte-size bus selections can utilize the most significant bytes of the bus (Big-Endian) or least significant bytes of the bus (Little-Endian). Port B bus-size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths. NOTE: 1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register 10 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE The levels applied to the port B bus-size select (SIZ0, SIZ1) inputs and the Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH transition. The stored port B bus-size selection is implemented by the next rising edge on CLKB according to Figure 2. Only 36-bit long-word data is written to or read from the FIFO memory on the IDT72V3613. Bus-matching operations are done after data is read from the FIFO RAM. Port B bus sizing does not apply to mail register operations. port B data inputs that are valid for the bus-size implementation is reported by a low level on the port B Parity Error Flag (PEFB). Odd or Even parity checking can be selected, and the Parity Error Flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the Odd/ Even parity (ODD/EVEN) select input. A parity error on one or more valid bytes of a port is reported by a LOW level on the corresponding port Parity Error Flag (PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26, and A27-A35, and port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, and its valid bytes are those used in a port B bus size implementation. When Odd/Even parity is selected, a port Parity Error Flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to its bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is selected for port-A reads (PGA = HIGH). When a port A read from the mail2 register with parity generation is selected with CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port B reads (PGB = HIGH). When a port B read from the mail1 register with parity generation is selected with CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH, and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs. BUS-MATCHING FIFO READS Data is read from the FIFO RAM in 36-bit long-word increments. If a longword bus-size is implemented, the entire long word immediately shifts to the FIFO output register upon a read. If byte or word size is implemented on port B, only the first one or two bytes appear on the selected portion of the FIFO output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO reads with the same bus-size implementation output the rest of the long word to the FIFO output register in the order shown by Figure 2. Each FIFO read with a new bus-size implementation automatically unloads data from the FIFO RAM to its output register and auxiliary registers. Therefore, implementing a new port B bus-size and performing a FIFO read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread data in these registers. When reading data from FIFO in byte or word format, the unused B0-B35 outputs are indeterminate. BYTE SWAPPING The byte-order arrangement of data read from the FIFO can be changed synchronous to the rising edge of CLKB. Byte-order swapping is not available for mail register data. Four modes of byte-order swapping (including no swap) can be done with any data port size selection. The order of the bytes are rearranged within the long word, but the bit order within the bytes remains constant. Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs on a CLKB rising edge that reads a new long word from the FIFO. The byte order chosen on the first byte or first word of a new long word read from the FIFO is maintained until the entire long word is transferred, regardless of the SW0 and SW1 states during subsequent reads. Figure 4 is an example of the byte-order swapping available for long word reads. Performing a byte swap and bus-size simultaneously for a FIFO read first rearranges the bytes as shown in Figure 4, then outputs the bytes as shown in Figure 2. PARITY GENERATION A HIGH level on the port A Parity Generate select (PGA) or port B Parity Generate select (PGB) enables the IDT72V3613 to generate parity bits for port reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte regardless of the state of the Parity Generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/ EVEN select. The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from the FIFO memory and before the data is written to the output register. Therefore, the port A Parity Generate select (PGA) and Odd/Even parity select (ODD/EVEN) have setup and hold time constraints to the port A Clock (CLKA) and the port B Parity Generate select (PGB) and ODD/EVEN select have setup and hold time constraints to the port B Clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new long word to the FIFO output register (see Figure 16 and 17). The circuit used to generate parity for the mail1 data is shared by the port B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH, and Write/Read select (W/RA, W/RB) input is LOW, the mail register is selected (MBA HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity Generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents of the register. Parity Generation timing, when reading from a mail register, can be found in Figure 18 and 19. PORT-B MAIL REGISTER ACCESS In addition to selecting port B bus sizes for FIFO reads, the port B bus Size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are HIGH, the mail1 register is accessed for a port B long-word read and the mail2 register is accessed for a port B long-word write. The mail register is accessed immediately and any bus-sizing operation that can be underway is unaffected by the mail register access. After the mail register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic diagram in Figure 3 shows the previous bus-size selection is preserved when the mail registers are accessed from port B. A port B bus-size is implemented on each rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q. PARITY CHECKING The port A data inputs (A0-A35) and port B data inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the port A data bus is reported by a low level on the port A Parity Error Flag (PEFA). A parity failure on one or more bytes of the 11 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 BYTE ORDER ON PORT A: BYTE ORDER ON PORT B: BE X SIZ1 SIZ0 L L COMMERCIAL TEMPERATURE RANGE A35 ⎯ A27 A26 ⎯ A18 A17 ⎯ A9 A8 ⎯ A0 A B C D B35 ⎯ B27 B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 A B C D Write to FIFO Read from FIFO (a) LONG WORD SIZE BE SIZ1 SIZ0 L L H B35 ⎯ B27 B26 ⎯ B18 A B B35 ⎯ B27 B26 ⎯ B18 C D B17 ⎯ B9 B8 ⎯ B0 1st: Read from FIFO B17 ⎯ B9 B8 ⎯ B0 2nd: Read from FIFO (b) WORD SIZE ⎯ BIG-ENDIAN BE H B35 ⎯ B27 B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 C D B17 ⎯ B9 B8 ⎯ B0 A B SIZ1 SIZ0 L H B35 ⎯ B27 B26 ⎯ B18 1st: Read from FIFO 2nd: Read from FIFO (c) WORD SIZE ⎯ LITTLE-ENDIAN B35 ⎯ B27 BE SIZ1 SIZ0 L H L B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 A B35 ⎯ B27 1st: Read from FIFO B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 2nd: Read from FIFO B B35 ⎯ B27 B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 C B35 ⎯ B27 3rd: Read from FIFO B26 ⎯ B18 B17 ⎯ B9 D B8 ⎯ B0 4th: Read from FIFO (d) BYTE SIZE ⎯ BIG-ENDIAN Figure 2. Dynamic Bus Sizing 12 4661 fig 01 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 B35 ⎯ B27 BE SIZ1 SIZ0 H H L COMMERCIAL TEMPERATURE RANGE B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 D B35 ⎯ B27 B26 ⎯ B18 B17 ⎯ B9 1st: Read from FIFO B8 ⎯ B0 2nd: Read from FIFO C A35 ⎯ A27 A26 ⎯ A18 A17 ⎯ A9 A8 ⎯ A0 B B35 ⎯ B27 B26 ⎯ B18 B17 ⎯ B9 3rd: Read from FIFO B8 ⎯ B0 A 4th: Read from FIFO 4661 fig 01a (d) BYTE SIZE ⎯ LITTLE-ENDIAN Figure 2. Dynamic Bus Sizing (Continued) CLKB G1 MUX SIZ0 Q SIZ1 Q BE Q 1 SIZ0 SIZ1 BE D Q 1 4661 fig 02 Figure 3. Logic Diagram for SIZ0, SIZ1, and BE Register 13 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 SW1 L L SW0 L L COMMERCIAL TEMPERATURE RANGE A35 ⎯ A27 A26 ⎯ A18 A B C D A B C D B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 B35 ⎯ B27 A17 ⎯ A9 A8 ⎯ A0 (a) NO SWAP SW1 SW0 L H A35 ⎯ A27 A26 ⎯ A18 A17 ⎯ A9 A8 ⎯ A0 A B C D D C B A B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 B35 ⎯ B27 (b) BYTE SWAP SW1 SW0 H L A35 ⎯ A27 A26 ⎯ A18 A17 ⎯ A9 A8 ⎯ A0 A B C D C D A B B26 ⎯ B18 B17 ⎯ B9 B8 ⎯ B0 A17 ⎯ A9 A8 ⎯ A0 B35 ⎯ B27 (c) WORD SWAP A35 ⎯ A27 SW1 SW0 H H A26 ⎯ A18 A B C D B A D C B17 ⎯ B9 B8 ⎯ B0 B35 ⎯ B27 B26 ⎯ B18 (d) BYTE-WORD SWAP Figure 4. Byte Swapping for FIFO Reads (Long-Word Size Example) 14 4661 fig 03 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE CLKA tRSTH CLKB tRSTS tFSS tFSH RST 0,1 FS1,FS0 tWFF tWFF FF tREF EF tPAE AE tPAF AF tRSF MBF1, MBF2 4661 drw 05 Figure 5. FIFO Reset and Loading the X Register with the Value of Eight tCLKH tCLK tCLKL CLKA FF HIGH CSA tENS tENH tENS tENH W/RA MBA tENH tENS tENS tENH tDS W1 (1) tDH tENS tENH tENS tENH ENA A0 - A35 ODD/ EVEN PEFA W2 (1) tPDPE No Operation tPDPE Valid Valid 4661 drw 06 NOTE: 1. Written to the FIFO. Figure 6. Port A Write Cycle Timing 15 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE CLKB EF HIGH CSB W/RB tENS tENH tSWS tSWH tENS tENH ENB SW1, SW0 tSZS tSZH tSZS tSZH No Operation BE SIZ1, SIZ0 (0,0) (0,0) NOT (1,1) (1) tPGS PGB, ODD/ EVEN NOT (1,1) (1) tPGH tEN B0-B35 tDIS tA tA Previous Data W1(2) W2 (2) 4661 drw 07 NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Data read from FIFO1. DATA SWAP TABLE FOR FIFO LONG-WORD READS FIFO DATA WRITE SWAP MODE FIFO DATA READ A35-A27 A26-A18 A17-A9 A8-A0 SW1 SW0 B35-B27 B26-B18 B17-B9 B8-B0 A B C D L L A B C D A B C D L H D C B A A B C D H L C D A B A B C D H H B A D C Figure 7. Port B Long-Word Read Cycle Timing 16 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE CLKB EF HIGH CSB W/RB tENS tENH tSWS tSWH ENB SW1, SW0 BE SIZ1, SIZ0 tSZS tSZH tSZS (0,1) tSZH PGB, ODD/ EVEN NOT (1,1) (1) tPGS No Operation (0,1) NOT (1,1) (1) tPGH Little Endian (2) B0-B17 tA Previous Data Read 1 Big Endian (2) B18-B35 tA Previous Data Read 1 tEN tA tDIS Read 2 tA tDIS Read 2 4661 drw 08 NOTES; 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused word B0-B17 or B18-B35 are indeterminate. DATA SWAP TABLE FOR FIFO WORD READS FIFO DATA WRITE SWAP MODE FIFO DATA READ READ NO. A35-A27 A26-A18 A17-A9 A8-A0 SW1 SW0 A B C D L L 1 2 A B C D L H A B C D H A B C D H BIG-ENDIAN B35-B27 LITTLE-ENDIAN B26-B18 B17-B9 B8-B0 A C B D C A D B 1 2 D B C A B D A C L 1 2 C A D B A C B D H 1 2 B D A C D B C A Figure 8. Port B Word Read-Cycle Timing 17 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE CLKB EF HIGH CSB W/RB tENS tENH tSWS tSWH ENB No Operation SW1, SW0 tSZS tSZH BE tSZS SIZ1, SIZ0 tSZH (1,0) (1,0) Not (1,1) (1) tPGS PGB, ODD/ EVEN tEN (1,0) (1,0) Not (1,1) (1) tPGH Not (1,1) (1) Not (1,1) (1) B0-B8 tA Previous Data tA Read 1 tA Read 2 tA Read 3 B27-B35 tA Previous Data tA Read 1 tA Read 2 tA Read 3 tDIS Read 4 tDIS Read 4 4661 drw 09 NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused bytes B0-B26 or B9-B35 are indeterminate. DATA SWAP TABLE FOR FIFO BYTE READS FIFO DATA READ FIFO DATA WRITE A35-A27 A A A A A26-A18 B B B B A17-A9 C C C C SWAP MODE A8-A0 D D D D SW1 L L H H BIGENDIAN LITTLEENDIAN B35-B27 B8-B0 1 2 3 4 A B C D D C B A 1 2 3 4 D C B A A B C D 1 2 3 4 C D A B B A D C 1 2 3 4 B A D C C D A B SW0 L H L H Figure 9. Port B Byte Read-Cycle Timing 18 READ NO. IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE tCLKH tCLK tCLKL CLKA CSA LOW WRA HIGH tENS tENH tENS tENH tDS tDH MBA ENA FF HIGH A0 - A35 W1 (1) tSKEW1 CLKB EF tCLKH 1 tCLK tCLKL 2 tREF tREF FIFO Empty CSB LOW W/RB LOW SIZ1, LOW SIZ0 tENS tENH ENB tA W1 B0 -B35 4661 drw 10 NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown. 2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively. Figure 10. EF Flag Timing and First Data Read when the FIFO is Empty 19 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 tCLKH tCLK COMMERCIAL TEMPERATURE RANGE tCLKL CLKB CSB LOW W/RB LOW SIZ1, LOW SIZ0 tENH tENS ENB EF HIGH B0 -B35 tA Previous Word in FIFO Output Register Next Word From FIFO (1) tCLKH tSKEW1 tCLK tCLKL 1 CLKA 2 tWFF tWFF FF FIFO Full CSA LOW WRA HIGH tENS tENH tENS tENH tDS tDH MBA ENA A0 - A35 To FIFO 4661 drw 11 NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKA cycle later than shown. 2. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. Figure 11. FF Flag Timing and First Available Write when the FIFO is Full CLKA tENS tENH ENA tSKEW2 CLKB AE (1) 1 2 tPAE tPAE X Long Words in FIFO (X+1) Long Words in FIFO tENS tENH ENB 4661 drw 12 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown. 2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW). 3. Port B size of long word is selected for the FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced to the last word or byte of the long word, respectively. Figure 12. Timing for AE when the FIFO is Almost-Empty 20 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE (1) tSKEW2 1 CLKA tENS 2 tENH ENA tPAF tPAF AF (64-X) Long Words in FIFO [64-(X+1)] Long Words in FIFO CLKB tENS tENH ENB 4661 drw 13 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown. 2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW). 3. Port-B size of long word is selected for FIFO read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the long word, respectively. Figure 13. Timing for AF when the FIFO is Almost-Full CLKA CSA tENS tENH tENS tENH tENS tENH tENS tENH W/RA MBA ENA tDS W1 A0 - A35 tDH CLKB tPMF tPMF MBF1 CSB W/RB SIZ1, SIZ0 tENS tENH ENB tEN B0 - B35 tMDV FIFO Output Register tPMR tDIS W1 (Remains valid in Mail1 Register after read) 4661 drw 14 NOTE: 1. Port-B parity generation off (PGB = LOW). Figure 14. Timing for Mail1 Register and MBF1 Flag 21 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE CLKB tENS tENH tENS tENH CSB W/RB tSZS SIZ1, SIZ0 tSZH tENH tENS ENB tDS W1 B0 - B35 tDH CLKA tPMF tPMF MBF2 CSA W/RA MBA tENS tENH ENA tEN tPMR tDIS W1 (Remains valid in Mail2 Register after read) A0 - A35 4661 drw 15 NOTE: 1. Port-A parity generation off (PGA = LOW). Figure 15. Timing for Mail2 Register and MBF2 Flag ODD/ EVEN W/RA MBA PGA tPOPE PEFA Valid tPEPE tPOPE Valid Valid tPEPE Valid 4661 drw 16 NOTE: 1. CSA = LOW and ENA = HIGH. Figure 16. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing 22 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE ODD/ EVEN W/RB SIZ1, SIZ0 PGB tPOPE PEFB Valid tPEPE tPOPE Valid Valid tPEPE Valid 4661 drw 17 NOTE: 1. CSB = LOW and ENB = HIGH. Figure 17. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB Timing ODD/ EVEN CSA LOW W/RA MBA PGA A8, A17, A26, A35 tEN tPEPB Mail2 Data tPOPB Generated Parity tPEPB Generated Parity Mail2 Data 4661 drw 18 NOTE: 1. ENA = HIGH. Figure 18. Parity Generation Timing when Reading from the Mail2 Register ODD/ EVEN CSB LOW W/RB SIZ1, SIZ0 PGB tEN B8, B17, B26, B35 tPEPB tMDV tPOPB Generated Parity tPEPB Generated Parity Mail1 Data Mail1 Data 4661 drw 19 NOTE: 1. ENB = HIGH. Figure 19. Parity Generation Timing when Reading from the Mail1 Register 23 IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION 3.3V 330 Ω From Output Under Test 30 pF 510 Ω (1) PROPAGATION DELAY LOAD CIRCUIT 3V Timing Input 1.5 V GND tS 3V High-Level Input 1.5 V th 3V Data, Enable Input 3V Low-Level Input GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 V 1.5 V GND VOLTAGE WAVEFORMS PULSE DURATIONS 3V 1.5 V tPLZ 1.5 V tPZL GND 1.5 V Low-Level Output ≈ 3V Input VOL tPZH VOH High-Level Output GND tW 1.5 V 1.5 V 1.5 V 1.5 V tPHZ 3V 1.5 V 1.5 V tPD tPD GND VOH In-Phase Output 1.5 V 1.5 V ≈ OV VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTE: 1. Includes probe and jig capacitance. Figure 20. Load Circuit and Voltage Waveforms 24 VOL 4661 drw 20 ORDERING INFORMATION XXXXXX Device Type X XX X Power Speed Package X X Process/ Temperature Range X BLANK 8 Tube or Tray Tape and Reel BLANK Commercial (0°C to +70°C) G Green PF Thin Quad Flat Pack (TQFP, PNG120) 15 Commercial L Low Power 72V3613 64 x 36 ⎯ 3.3V SyncFIFO Clock Cycle Time (tCLK) Speed in Nanoseconds 4661 drw 21 DATASHEET DOCUMENT HISTORY 07/10/2000 05/27/2003 06/09/2005 02/12/2009 11/11/2013 01/09/2014 07/23/2019 pg. 1. pg. 6. pgs. 1, 2, 3 and 26. pg. 26. pgs. 1, 2, 5, 7, 8, 20, 21 and 25. pg. 2. Datasheet changed to Obsolete Status. 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