72V3614L15PF

3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 FEATURES: • • • • • • Selection of Big- or Little-Endian format for word and byte bus sizes Three modes of byte-order swapping on port B Programmable Almost-Full and Almost-Empty flags Microprocessor interface control logic EFA , FFA , AEA , and AFA flags synchronized by CLKA EFB , FFB , AEB , and AFB flags synchronized by CLKB Passive parity checking on each port Parity generation can be selected for each port Available in space saving 120-pin thin quad flat package (TQFP) Green parts available, see ordering information • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions Supports clock frequencies up to 67 MHz Fast access times of 10 ns Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Mailbox bypass Register for each FIFO Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word), and 9 bits (byte) IDT72V3614 OBSOLETE PART • • • • • • • • • FUNCTIONAL BLOCK DIAGRAM R T O R F A P ED E D T S N E N E L G M O I S S M B E O D O EC R EW T N O N Port-A Control Logic MBF1 Write Pointer FFA AFA Read Pointer EFB AEB FIFO1 Programmable Flag Offset Register FIFO2 FFB AFB Status Flag Logic Parity Generation Output Register Read Pointer Write Pointer RAM ARRAY 64 x 36 PGA PEFA B0-B35 36 Input Register EFA AEA 36 Status Flag Logic 36 FS0 FS1 A0 - A35 Output Register Device Control RAM ARRAY 64 x 36 Bus-Matching & Byte Swapping ODD/ EVEN PGB Parity Generation Input Register RST PEFB Parity Gen/Check Mail 1 Register Bus-Matching & Byte Swapping CLKA CSA W/RA ENA MBA Mail 2 Register Parity Gen/Check MBF2 Port-B Control Logic 4663 drw 01 COMMERCIAL TEMPERATURE RANGE CLKB CSB W/RB ENB BE SIZ0 SIZ1 SW0 SW1 JANUARY 2014 1 DSC-4663/4 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DESCRIPTION: for data read from each port. Two or more devices can be used in parallel to create wider data paths. This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOWto-HIGH transition of a continuous (free-running) port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses controlled by a synchronous interface. The Full Flag (FFA, FFB) and Almost-Full flag (AFA, AFB) of a FIFO are two-stage synchronized to the port clock that writes data to its array. The Empty Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT72V3614 is characterized for operation from 0°C to 70°C. This device is fabricated using high speed, submicron CMOS technology. The IDT72V3614 is designed to run off a 3.3V supply for exceptionally low power consumption. This device is monolithic, high-speed, low-power CMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. The FIFO operates in IDT Standard mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats with a choice of Big- or Little-Endian configurations. Three modes of byte-order swapping are possible with any bus size selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0 EFB AEB AFB AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND BE SW1 SW0 SIZ1 SIZ0 MBF1 PEFB PGB VCC W/RB CLKB ENB CSB FFB 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 EFA AEA NOTE: 1. Pin 1 identifier in corner. TQFP (PNG120, order code: PF) TOP VIEW 2 4663 drw 03 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION Symbol Name I/O I/O Description A0-A35 Port A Data AEA Port A AlmostEmpty Flag O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of 36-bit words in (Port A) FIFO2 is less than or equal to the value in the offset register, X. AEB Port B AlmostEmpty Flag O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of 36-bit words in (Port B) FIFO1 is less than or equal to the value in the offset register, X. AFA Port A Almost-Full Flag O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty (Port A) locations in FIFO1 is less than or equal to the value in the offset register, X. AFB Port B Almost-Full Flag O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of 36-bit empty (Port B) locations in FIFO2 is less than or equal to the value in the offset register, X. B0-B35 Port B Data BE Big-Endian Select I Selects the bytes on port B used during byte or word data transfer. A LOW on BE selects the most significant bytes on B0-B35 for use, and a HIGH selects the least significant bytes. CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port B byte swapping and data port sizing operations are also synchronous to the LOW-to-HIGH transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-HIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. EFA Port A Empty Flag O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA isLOW, FIFO2 is empty, and (Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory. EFB Port B Empty Flag O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is empty, and (Port B) and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. FFA Port A Full Flag O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full, and writes (Port A) to its memory are disabled. FFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. FFB Port B Full Flag O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full, and writes (Port B) writes to its memory are disabled. FFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after reset. I/O 36-bit bidirectional data port for side A. 36-bit bidirectional data port for side B. FS1, FS0 Flag-Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the Almost-Full flag and Almost-Empty flag offset. MBA Port A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level selects FIFO2 output register data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the device is reset. 3 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (Continued) Symbol Name I/O Description MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset. ODD/ EVEN Odd/Even Parity Select I Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. PEFA Port A Parity Error Flag O When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8, (Port A) A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs. PEFB Port B Parity Error Flag O When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as B0-B8, (Port B) B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for Port B. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/RB LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0B35 inputs. PGA Port A Parity Generation I Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. PGB Port B Parity Generation I Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. RST Reset I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offsets. SIZ0, SIZ1 Port B Bus Size Selects I A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to-HIGH (Port B) transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long word, word or byte. A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit write or read. SW0, SW1 Port B Byte Swap Select I At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by SW0 (Port B) and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection. W/RA Port A Write/ Read Select I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. W/RB Port B Write/ Read Select I A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH. 4 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)(1) Symbol Rating Commercial Unit –0.5 to +4.6 V V CC Supply Voltage Range VI Input Voltage Range –0.5 to VCC+0.5 V Output Voltage Range –0.5 to VCC+0.5 V (2) VO (2) IIK Input Clamp Current, (VI < 0 or VI > VCC) ±20 mA IOK Output Clamp Current, (VO < 0 or VO > VCC) ±50 mA I OUT Continuous Output Current, (VO = 0 to VCC) ±50 mA I CC Continuous Current Through VCC or GND ±500 mA T STG Storage Temperature Range –65 to 150 °C NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Supply Voltage Min. Typ. Max. Unit 3.0 3.3 3.6 V VIH HIGH Level Input Voltage 2 — VCC+0.5 V VIL LOW-Level Input Voltage – — 0.8 V IOH HIGH-Level Output Current – — –4 mA IOL LOW-Level Output Current – — 8 mA TA Operating Free-air Temperature 0 — 70 °C ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREEAIR TEMPERATURE RANGE (Unless otherwise noted) IDT72V3614 Commercial tCLK = 15 ns Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit VOH Output Logic "1" Voltage VCC = 3.0V, IOH = –4 mA 2.4 — — V VOL Output Logic "0" Voltage VCC = 3.0V, IOL = 8 mA — — 0.5 V ILI Input Leakage Current (Any Input) VCC = 3.6V, VI = VCC or 0 — — ±5 µA Output Leakage Current VCC = 3.6V, VO = VCC or 0 — — ±5 µA Standby Current VCC = 3.6V, VI = VCC - 0.2V or 0 — — 500 µA CIN Input Capacitance VI = 0, f = 1 MHz — 4 — pF C OUT Output Capacitance VO = 0, f = 1 MHZ — 8 — pF ILO I CC (2) NOTES: 1. All typical values are at VCC = 3.3V, TA = 25°C. 2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS). 5 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT72V3614 with CLKA and CLKB set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT72V3614 can be calculated by: PT = VCC x ICC(f) + Σ(CL x VOH2 x fo) N where: N CL fo VOH = = = = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus-size) output capacitance load switching frequency of an output output high level voltage When no reads or writes are occurring on this device, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is calculated by: PT=VCC x fS x 0.025 mA/MHz 175 150 ICC(f) Supply Current mA fdata = 1/2 fS TA = 25°C 125 CL = 0 pF VCC = 3.6V VCC = 3.3V 100 VCC = 3.0V 75 50 25 0 0 10 20 30 40 50 60 70 fS ⎯ Clock Frequency ⎯ MHz Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) 6 80 90 4663 drw 04 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial: Vcc=3.3V± 0.30V; TA = 0°C to +70°C; JEDEC JESD8-A compliant Symbol IDT72V3614L15 Min. Max. Parameter Unit fS Clock Frequency, CLKA or CLKB – 66.7 Mhz tCLK Clock Cycle Time, CLKA or CLKB 15 – ns tCLKH Pulse Duration, CLKA or CLKB HIGH 6 – ns tCLKL Pulse Duration, CLKA or CLKB LOW 6 – ns tDS Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑ 4 – ns tENS Setup Time, CSA, W/RA, ENA and MBA before CLKA↑; CSB,W/RB and ENB before CLKB↑ 5 – ns tSZS Setup Time, SIZ0, SIZ1,and BE before CLKB↑ 4 – ns tSWS Setup Time, SW0 and SW1 before CLKB↑ 6 – ns tPGS Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before CLKB↑ 4 – ns tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑ 5 – ns tFSS Setup Time, FS0 and FS1 before RST HIGH 5 – ns tDH Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑ 1 – ns tENH Hold Time, CSA, W/RA, ENA and MBA after CLKA↑; CSB, W/RB and ENB after CLKB↑ 1 – ns tSZH Hold Time, SIZ0, SIZ1, and BE after CLKB↑ 1 – ns tSWH Hold Time, SW0 and SW1 after CLKB↑ 1 – ns tPGH Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after CLKB↑ 0 – ns tRSTH Hold Time, RST LOW after CLKA↑ or CLKB↑ 5 – ns (2) (1) (2) tFSH (1) Hold Time, FS0 and FS1 after RST HIGH 4 – ns (3) Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, FFB 8 – ns (3,4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB 14 – ns tSKEW1 tSKEW2 NOTES: 1. Only applies for a clock edge that does a FIFO read. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested. 7 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF Commercial: Vcc=3.3V± 0.30V; TA = 0°C to +70°C; JEDEC JESD8-A compliant Symbol IDT72V3614L15 Min. Max. Parameter Unit tA Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35 2 10 ns tWFF Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB 2 10 ns tREF Propagation Delay Time, CLKA↑ to EFA and and CLKB↑ to EFB 2 10 ns tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB 2 10 ns tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB 2 10 ns tPMF Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH 1 9 ns tPMR Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2) 2 10 ns tPPE Propagation delay time, CLKB↑ to PEFB 2 10 ns tMDV Propagation Delay Time, MBA to A0-A35 valid and SIZ1, SIZ0 to B0-B35 valid 1 10 ns tPDPE Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid 2 10 ns Propagation Delay Time, ODD/EVEN to PEFA and PEFB 2 10 ns tPOPB Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35) 2 10 ns tPEPE Propagation Delay Time, CSA, ENA,W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to PEFB 1 10 ns tPEPB(4) Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17, A26, A35); CSB, ENB, W/RB,SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35) 2 10 ns tRSF Propagation Delay Time, RST to (MBF1, MBF2) HIGH 1 15 ns tEN Enable Time, CSA and W/RA LOW to A0-A35 active and CSB LOW and W/RB HIGH to B0-B35 active 2 10 ns tDIS Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or W/RB LOW to B0-B35 at high-impedance 1 8 ns (3) tPOPE (4) NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 3. Only applies when a new port B bus size is implemented by the rising CLKB edge. 4. Only applies when reading data from a mail register. 8 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE SIGNAL DESCRIPTIONS output register. When the Empty Flag is LOW, the FIFO is empty and attempted FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set LOW when the fourth byte or second word of the last long word is read. The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state machine that controls an Empty Flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output register in a minimum of three cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that reads data from the FIFO have not elapsed since the time the word was written. The Empty Flag of the FIFO is set HIGH by the second LOW-toHIGH transition of the synchronizing clock, and the new data word can be read to the FIFO output register in the following cycle. A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 14 and 15). RESET The IDT72V3614 is reset by taking the Reset (RST) input LOW for at least four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH transitions. The Reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW, the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA, AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH. After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The device must be reset after power up before data is written to its memory. A LOW-to-HIGH transition on the RST input loads the Almost-Full and Almost-Empty Offset register (X) with the values selected by the Flag Select (FS0, FS1) inputs. The values that can be loaded into the registers are shown in Table 1. For the relevant Reset and preset value loading timing diagram, see Figure 5. FIFO WRITE/READ OPERATION The state of port A data A0-A35 outputs is controlled by the port A Chip Select (CSA) and the port A Write/Read select (W/RA). The A0-A35 outputs are in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35 outputs are active when both CSA and W/RA are LOW. Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA is LOW, and EFA is HIGH (see Table 2). Port A read and write timing diagrams can be found in Figure 6 and 15. The port B control signals are identical to those of port A. The state of the port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB) and the port B Write/Read select (W/RB). The B0-B35 outputs are in the highimpedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are active when both CSB and W/RB are LOW. Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/ RB is HIGH, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW. Data is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW (see Table 3). Port B read and write timing diagrams together with Bus-Matching, byte-swapping and Endian select can be found in Figures 7 to 12. The setup and hold time constraints to the port clocks for the port Chip Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port Chip Select and Write/Read select can change states during the setup and hold time window of the cycle. FULL FLAG (FFA, FFB) The Full Flag of a FIFO is synchronized to the port clock that writes data to its array. When the Full Flag is HIGH, a memory location is free in the FIFO to receive new data. No memory locations are free when the full flag is LOW and attempted writes to the FIFO are ignored. Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a Full Flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is full, full-1, or full-2. From the time a word is read from a FIFO, the previous memory location is ready to be written in a minimum of three cycles of the Full Flag synchronizing clock. Therefore, a Full Flag is LOW if less than two cycles of the Full Flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full Flag synchronization clock after the read sets the Full Flag HIGH and the data can be written in the following clock cycle. A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle (see Figure 16 and 17). ALMOST-EMPTY FLAGS (AEA, AEB) The Almost-Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost-Empty flag monitors a write-pointer and a read-pointer comparator that indicates when the FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2. The almost-empty state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset section). An Almost-Empty flag is LOW when the FIFO contains X or less long words in memory and is HIGH when the FIFO contains (X+1) or more long words. Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock are required after a FIFO write for the Almost-Empty flag to reflect the new level of fill. Therefore, the Almost-Empty flag of a FIFO containing (X+1) or more long words remains LOW if two cycles of the synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing clock begins the first synchronization SYNCHRONIZED FIFO FLAGS Each FIFO is synchronized to its port clock through two flip-flop stages. This is done to improve flag reliability by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to the level of FIFO1 and FIFO2 fill. EMPTY FLAGS (EFA, EFB) The Empty Flag of a FIFO is synchronized to the port clock that reads data from its array. When the Empty Flag is HIGH, new data can be read to the FIFO 9 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE TABLE 1 – FLAG PROGRAMMING FS1 FS0 RST ALMOST-FULL AND ALMOST-EMPTY FLAG OFFSET REGISTER (X) H H ↑ 16 H L ↑ 12 L H ↑ 8 L L ↑ 4 TABLE 2 – PORT-A ENABLE FUNCTION TABLE CSA W/RA ENA MBA CLKA Data A (A0-A35) I/O Port Functions H X X X X Input None L H L X X Input None L H H L ↑ Input FIFO1 Write L H H H ↑ Input Mail1 Write L L L L X Output None L L H L ↑ Output FIFO2 Read L L L H X Output None L L H H ↑ Output Mail2 Read (Set MBF2 HIGH) TABLE 3 – PORT-B ENABLE FUNCTION TABLE CSB W/RB ENB SIZ1, SIZ0 CLKB Data B (B0-B35) I/O H X X X X Input None L H L X X Input None L H H One, both LOW ↑ Input FIFO2 Write L H H Both HIGH ↑ Input Mail2 Write L L L One, both LOW X Output None L L H One, both LOW ↑ Output FIFO1 read L L L Both HIGH X Output None L L H Both HIGH ↑ Output Mail1 Read (Set MBF1 HIGH) TABLE 4 – FIFO1 FLAG OPERATION Synchronized Synchronized to CLKB to CLKA Number of 36-Bit TABLE 5 – FIFO2 FLAG OPERATION Synchronized Synchronized to CLKA to CLKB Number of 36-Bit EFB AEB AFA FFA Words in the FIFO2 0 L L H H 1 to X H L H (X+1) to [64-(X+1)] H H (64-X) to 63 H 64 H Words in the FIFO1 (1) Port Functions EFA AEA AFB FFB 0 L L H H H 1 to X H L H H H H (X+1) to [64-(X+1)] H H H H H L H (64-X) to 63 H H L H H L L 64 H H L L (1) NOTE: 1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register. 10 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) long words. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 18 and 19). ALMOST FULL FLAGS (AFA, AFB) The Almost-Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost-Full flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO memory status is almost full, almost full-1, or almost full-2. The almost-full state is defined by the value of the Almost-Full and Almost-Empty Offset register (X). This register is loaded with one of four preset values during a device reset (see Reset section). An Almost-Full flag is LOW when the FIFO contains (64-X) or more long words in memory and is HIGH when the FIFO contains [64-(X+1)] or less long words. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for the Almost-Full flag to reflect the new level of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)] or less words remains LOW if two cycles of the synchronizing clock have not elapsed since the read that reduced the number of long words in memory to [64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of long words in memory to [64-(X+1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see Figure 20 and 21). MAILBOX REGISTERS Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B without putting it in queue. The Mailbox Select (MBA, SIZ0, SIZ1) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when a port A write is selected by CSA, W/ RA, and ENA with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0B35 data to the mail2 register when a port B write is selected by CSB, W/RB, and ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When the port A data outputs (A0-A35) are active, the data on the bus comes from the FIFO2 output register when MBA is LOW and from the mail2 register when MBA is HIGH. When the port B data outputs (B0-B35) are active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are LOW and from the mail2 register when both SIZ1 and SIZ0 are HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a rising CLKB edge when a port B read is selected by CSB, W/RB, and ENB with both SIZ1 and SIZ0 HIGH. The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when port A read is selected by CSA, W/RA, and ENA and MBA is HIGH. The data in the mail register remains intact after it is read and changes only when new data is written to the register. Relevant mail register and Mail Register Flag timing diagrams can be found in Figure 22 and Figure 23. DYNAMIC BUS SIZING The port B bus can be configured in a 36-bit long word, 18-bit word, or 9bit byte format for data read from FIFO1 or written to FIFO2. Word- and bytesize bus selections can utilize the most significant bytes of the bus (Big-Endian) or least significant bytes of the bus (Little-Endian). Port B bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths. 11 The levels applied to the port B bus Size select (SIZ0, SIZ1) inputs and the Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH transition. The stored port B bus size selection is implemented by the next rising edge on CLKB according to Figure 2. Only 36-bit long-word data is written to or read from the two FIFO memories on the IDT72V3614. Bus-matching operations are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. Port B bus sizing does not apply to mail register operations. BUS-MATCHING FIFO1 READS Data is read from the FIFO1 RAM in 36-bit long word increments. If a long word bus size is implemented, the entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B, only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 2. Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its output register and auxiliary registers. Therefore, implementing a new port B bus size and performing a FIFO1 read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread long word data. When reading data from FIFO1 in byte or word format, the unused B0-B35 outputs are indeterminate. BUS-MATCHING FIFO2 WRITES Data is written to the FIFO2 RAM in 36-bit long word increments. FIFO2 writes, with a long-word bus size, immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner shown in Figure 2. Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data. When writing data to FIFO2 in byte or word format, the unused B0-B35 inputs are don't care(1) inputs. PORT-B MAIL REGISTER ACCESS In addition to selecting port-B bus sizes for FIFO reads and writes, the port B bus Size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are HIGH, the mail1 register is accessed for a port B long word read and the mail2 register is accessed for a port B long word write. The mail register is accessed immediately and any bus-sizing operation that may be underway is unaffected by the mail register access. After the mail register access is complete, the previous FIFO access can resume in the next CLKB cycle. The logic diagram in Figure 3 shows the previous bus-size selection is preserved when the mail registers are accessed from port B. A port B bus size is implemented on each rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q. BYTE SWAPPING The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order swapping is not available for mail register data. Four modes of byte-order swapping (including no swap) can be done with any data port size selection. IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 The order of the bytes are rearranged within the long word, but the bit order within the bytes remains constant. Byte arrangement is chosen by the port B Swap select (SW0, SW1) inputs on a CLKB rising edge that reads a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first word of a new long word read from FIFO1 or written to FIFO2 is maintained until the entire long word is transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 4 is an example of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for a FIFO1 read first rearranges the bytes as shown in Figure 4, then outputs the bytes as shown in Figure 2. Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes, first loads the data according to Figure 2, then swaps the bytes as shown in Figure 4 when the long word is loaded to FIFO2 RAM. PARITY CHECKING The port A inputs (A0-A35) and port B inputs (B0-B35) each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the port A data bus is reported by a LOW level on the port Parity Error Flag (PEFA). A parity failure on one or more bytes of the port B data input that are valid for the bus-size implementation is reported by a LOW level on the port B Parity Error Flag (PEFB). Odd or Even parity checking can be selected, and the Parity Error Flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the Odd/ Even parity (ODD/EVEN) select input. A parity error on one or more valid bytes of a port is reported by a LOW level on the corresponding port Parity Error Flag (PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18-A26, and A27-A35. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, and its valid bytes are those used in a port B bus-size implementation. When Odd/Even parity is selected, a port Parity Error Flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to the bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is selected for port A reads (PGA = HIGH). When a port A read from the mail2 register with parity generation is selected with CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA HIGH, the port A Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the COMMERCIAL TEMPERATURE RANGE A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port B reads (PGB = HIGH). When a port B read from the mail1 register with parity generation is selected with CSB LOW, ENB HIGH, W/RB LOW, both SIZ0 and SIZ1 HIGH, and PGB HIGH, the port B Parity Error Flag (PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs (see Figure 24 and 25). PARITY GENERATION A HIGH level on the port A Parity Generate select (PGA) or port B Parity Generate select (PGB) enables the IDT72V3614 to generate parity bits for port reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8, A9-A17, A18-26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte regardless of the state of the Parity Generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/ EVEN select. The generated parity bits are substituted for the levels originally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port A Parity Generate select (PGA) and Odd/Even parity select (ODD/EVEN) have setup and hold time constraints to the port A Clock (CLKA) and the port B Parity Generate select (PGB) and ODD/EVEN have setup and hold-time constraints to the port B Clock (CLKB). These timing constraints only apply for a rising clock edge used to read a new long word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port Chip Select (CSA, CSB) is LOW, Enable (ENA, ENB) is HIGH, Write/Read select (W/RA, W/RB) input is LOW, the Mail register is selected (MBA is HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity Generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents of the register (see Figure 26 and 27). 12 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE A35⎯A27 A26⎯A18 A1⎯A9 A8⎯A0 BYTE ORDER ON PORT A: A B C D BYTE ORDER ON PORT B: B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 A B C D BE SIZ1 SIZ0 X L L Write to FIFO1/ Read From FIFO2 Read from FIFO1/ Write to FIFO2 (a) LONG WORD SIZE BE SIZ1 SIZ0 L L H B35⎯B27 B26⎯B18 A B B35⎯B27 B26⎯B18 C D B17⎯B9 B8⎯B0 1st: Read from FIFO1/ Write to FIFO2 B17⎯B9 B8⎯B0 2nd: Read from FIFO1/ Write to FIFO2 (b) WORD SIZE ⎯ BIG-ENDIAN B35⎯B27 BE SIZ1 SIZ0 H L H B35⎯B27 B26⎯B18 B26⎯B18 B17⎯B9 B8⎯B0 C D B17⎯B9 B8⎯B0 A B 1st: Read from FIFO1/ Write to FIFO2 2nd: Read from FIFO1/ Write to FIFO2 (c) WORD SIZE ⎯ LITTLE-ENDIAN B35⎯B27 BE SIZ1 SIZ0 L H L B26⎯B18 B17⎯B9 B8⎯B0 1st: Read from FIFO1/ Write to FIFO2 A B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 2nd: Read from FIFO1/ Write to FIFO2 B B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 3rd: Read from FIFO1/ Write to FIFO2 C B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 4th: Read from FIFO1/ Write to FIFO2 D (d) BYTE SIZE ⎯ BIG-ENDIAN Figure 2. Dynamic Bus Sizing 13 4663 drw fig 01 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 B35⎯B27 BE SIZ1 SIZ0 H H L COMMERCIAL TEMPERATURE RANGE B26⎯B18 B17⎯B9 B8⎯B0 1st: Read from FIFO1/ Write to FIFO2 D B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 2nd: Read from FIFO1/ Write to FIFO2 C B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 B B35⎯B27 B26⎯B18 B17⎯B9 3rd: Read from FIFO1/ Write to FIFO2 B8⎯B0 4th: Read from FIFO1/ Write to FIFO2 A (d) BYTE SIZE ⎯ LITTLE-ENDIAN 4663 drw fig 01a Figure 2. Dynamic Bus Sizing (Continued) CLKB G1 MUX SIZ0 Q SIZ1 Q BE Q 1 SIZ0 SIZ1 BE D Q 1 4663 drw fig 02 Figure 3. Logic Diagrams for SIZ0, SIZ1, and BE Register (1) Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with unused inputs) must not be left open, rather they must be either HIGH or LOW. 14 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 SW1 L L SW0 L L COMMERCIAL TEMPERATURE RANGE A35⎯A27 A26⎯A18 A17⎯A9 A8⎯A0 A B C D A B C D B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 (a) NO SWAP SW1 SW0 L H A35⎯A27 A26⎯A18 A17⎯A9 A8⎯A0 A B C D D C B A B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 (b) BYTE SWAP SW1 SW0 H L A35⎯A27 A26⎯A18 A17⎯A9 A8⎯A0 A B C D C D A B B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 (c) WORD SWAP SW1 SW0 H H A35⎯A27 A26⎯A18 A17⎯A9 A8⎯A0 A B C D B A D C B35⎯B27 B26⎯B18 B17⎯B9 B8⎯B0 (d) BYTE-WORD SWAP Figure 4. Byte Swapping (Long Word Size Example) 15 4663 drw fig 03 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKA tRSTH CLKB tRSTS tFSS tFSH RST 0,1 FS1,FS0 tWFF tWFF FFA tREF EFA tWFF tWFF FFB tREF EFB tRSF MBF1, MBF2 tPAE AEA tPAF AFA tPAE AEB tPAF AFB 4663 drw 05 Figure 5. Device Reset and Loading the X Register with the Value of Eight 16 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 tCLKH tCLK COMMERCIAL TEMPERATURE RANGE tCLKL CLKA FFA HIGH CSA tENS tENH tENS tENH tENS tENH tENS tENH W/RA MBA tENS tENH tENS tENH ENA tDS tDH W1(1) A0 - A35 ODD/ EVEN W2(1) tPDPE PEFA No Operation tPDPE Valid Valid 4663 drw 06 NOTE: 1. Written to FIFO1. Figure 6. Port-A Write Cycle Timing for FIFO1 CLKB FFB HIGH t ENS CSB t ENS W/RB t ENS tENH tSWS tSWH tENS tENH ENB SW1, SW0 BE SIZ1, SIZ0 tSZS tSZH tSZS (0,0) tSZH (0,0) tDS NOT (1,1) (1) tDH B0-B35 ODD/ EVEN tPPE tPDPE PEFB VALID VALID 4663 drw 07 NOTE: 1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2 SWAP MODE DATA WRITTEN TO FIFO2 DATA READ FROM FIFO2 SW1 SW0 B35-27 B26-18 B17-B9 B8-B0 A35-27 L L A B C D A L H D C B A H L C D A H H B A D A17-A9 A8-A0 B C D A B C D B A B C D C A B C D Figure 7. Port-B Long-Word Write Cycle Timing for FIFO2 17 A26-A18 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB FFB HIGH tENH tENS CSB tENS W/RB tENH tENS tENH tENS ENB tSWS tSWH SW1, SW0 tSZS tSZH tSZS tSZH tSZS tSZH tSZS tSZH BE SIZ1, SIZ0 LittleEndian BigEndian (0, 1) NOT (1,1) (1) (0, 1) tDS tDH tDS tDH B0-B17 B18-B35 ODD/EVEN tPDPE VALID tPPE PEFB VALID 4663 drw 08 NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register. 2. PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for Big-Endian bus, and B17-B9 and B-8-B0 for Little-Endian bus. DATA SWAP TABLE FOR WORD WRITES TO FIFO2 DATA WRITTEN TO FIFO2 SWAP WRITE MODE NO. BIG-ENDIAN LITTLE-ENDIAN SW1 L L H H SW0 L H L H DATA READ FROM FIFO2 B35-27 B26-18 B17-B9 B8-B0 A35-27 A26-A18 A17-A9 A8-A0 1 A B C D A B C D 2 C D A B 1 D C B A A B C D 2 B A D C 1 C D A B A B C D 2 A B C D 1 B A D C A B C D 2 D C B A Figure 8. Port-B Word Write Cycle Timing for FIFO2 18 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB FFB HIGH tENS tENH CSB tENS W/RB tENS tENH tSWS tENH tSZH tSZS tSZH tENS tENH ENB SW1, SW0 tSZS BE tSZH tSZS tSZS SIZ1, SIZ0 LittleEndian B0B8 BigEndian B27B35 (1,0) tSZH (1,0) (1,0) tDS tDH tDS tDH (1,0) Not (1,1) (1) ODD/EVEN tPPE tPDPE tPDPE tPDPE PEFB Valid Valid Valid 4663 drw 09 Valid NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register. 2. PEFB indicates parity error for the following bytes: B35—B27 for Big-Endian bus and B8—B0 for Little-Endian bus. DATA SWAP TABLE FOR BYTE WRITES TO FIFO2 DATA WRITTEN TO FIFO2 SWAP WRITE MODE NO. BIG-ENDIAN LITTLE-ENDIAN SW1 SW0 B35-B27 B8-80 L L L H H L H H 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 A B C D D C B A C D A B B A D C D C B A A B C D B A D C C D A B DATA READ FROM FIFO2 A35-A27 A26-A18 A17-A9 A8-A0 A B C D A B C D A B C D A B C D Figure 9. Port-B Byte Write Cycle Timing for FIFO2 19 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB EFB HIGH CSB W/RB tENS tENH tSWS tSWH tENH tENS ENB No Operation SW1, SW0 tSZS tSZH tSZS (0,0) tSZH BE SIZ1, SIZ0 PGB, ODD/ EVEN NOT (1,1) (1) tPGS tEN (0,0) NOT (1,1) (1) tPGH B0-B35 tDIS tA tA Previous Data W1(2) W2 (2) 4663 drw 10 NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Data read from FIFO1. DATA SWAP TABLE FOR FIFO LONG-WORD READS FROM FIFO1 DATA WRITTEN TO FIFO1 SWAP MODE DATA READ FROM FIFO1 A35-A27 A26-A18 A17-A9 A8-A0 SW1 SW0 B35-B27 B26-B18 B17-B9 B8-B0 A B C D L L A B C D A B C D L H D C B A A B C D H L C D A B A B C D H H B A D C Figure 10. Port-B Long-Word Read Cycle Timing for FIFO1 20 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB EFB HIGH CSB W/RB tENS tENH tSWS tSWH ENB No Operation SW1, SW0 tSZS tSZH tSZS (0,1) tSZH BE SIZ1, SIZ0 PGB, ODD/ EVEN NOT (1,1) (1) tPGS NOT (1,1) (1) (0,1) tEN tPGH tA LittleEndian(2) B0-B17 tA Previous Data Read 1 BigEndian(2) B18-B35 tA Previous Data Read 1 tDIS Read 2 tDIS tA Read 2 4663 drw 11 NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused word B0-B17 or B18-B35 are indeterminate. DATA SWAP TABLE FOR WORD READS FROM FIFO1 DATA READ FROM FIFO1 DATA WRITTEN TO FIFO1 SWAP MODE READ NO. A35-A27 A26-A18 A17-A9 A8-A0 SW1 SW0 A B C D L L 1 2 A B C D L H A B C D H A B C D H BIG-ENDIAN B35-B27 LITTLE-ENDIAN B26-B18 B17-B9 B8-B0 A C B D C A D B 1 2 D B C A B D A C L 1 2 C A D B A C B D H 1 2 B D A C D B C A Figure 11. Port-B Word Read Cycle Timing for FIFO1 21 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB EFB HIGH CSB W/RB tENS tENH tSWS tSWH ENB No Operation SW1, SW0 tSZS tSZH BE tSZS SIZ1, SIZ0 BigEndian(2) (1,0) (1,0) Not (1,1)(1) tPGS PGB, ODD/ EVEN LittleEndian(2) tSZH (1,0) tEN Not (1,1) (1) tPGH Not (1,1)(1) (1,0) Not (1,1)(1) B0-B8 tA Previous Data tA Read 1 tA Read 2 tA Read 3 B27-B35 tA Previous Data tA Read 1 tA Read 2 tA Read 3 tDIS Read 4 tDIS Read 4 4663 drw 12 NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. 2. Unused bytes B9-B35 or B0-B26 are indeterminate. DATA SWAP TABLE FOR BYTE READS FROM FIFO1 DATA READ FROM FIFO 1 DATA WRITTEN TO FIFO 1 A35-A27 A A A A A26-A18 B B B B A17-A9 C C C C SWAP MODE A8-A0 D D D D SW1 L L H H READ NO. LITTLEENDIAN B35-B27 B8-B0 1 2 3 4 A B C D D C B A 1 2 3 4 D C B A A B C D 1 2 3 4 C D A B B A D C 1 2 3 4 B A D C C D A B SW0 L H L H Figure 12. Port-B Byte Read Cycle Timing for FIFO1 22 BIGENDIAN IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 tCLK tCLKH COMMERCIAL TEMPERATURE RANGE tCLKL CLKA EFA HIGH CSA W/RA MBA tENH tENS tENS tENH tENH tENS ENA tEN tMDV A0 - A35 tA Previous Data Word 1(1) tPGH tPGS PGA, ODD/ EVEN No Operation tA tPGS tDIS Word 2 (1) tPGH 4663 drw 13 NOTE: 1. Read from FIFO2. Figure 13. Port-A Read Cycle Timing for FIFO2 tCLK tCLKH tCLKL CLKA CSA LOW WRA HIGH tENS tENH tENS tENH tDS tDH MBA ENA FFA HIGH W1 A0 - A35 (1) tSKEW1 CLKB EFB tCLK tCLKH tCLKL 1 2 tREF tREF FIFO1 Empty CSB LOW W/RB LOW SIZ1, SIZ0 LOW tENS tENH ENB tA W1 B0 -B35 4663 drw 14 NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown. 2. Port-B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1, respectively. Figure14. EFB Flag Timing and First Data Read when FIFO1 is Empty 23 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB CSB LOW WRB HIGH tENS tENH tENS tENH SIZ1, SIZ0 ENB FFB HIGH tDS tDH W1 B0 - B35 (1) tSKEW1 CLKA tCLK tCLKH tCLKL 1 2 tREF EFA tREF FIFO2 Empty CSA LOW W/RA LOW MBA LOW tENS tENH ENA tA W1 A0 - A35 4663 drw 15 NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown. 2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. Figure 15. EFA Flag Timing and First Data Read when FIFO2 is Empty 24 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE tCLK tCLKH tCLKL CLKB CSB LOW W/RB LOW SIZ1, LOW SIZ0 tENS tENH ENB EFB B0 - B35 HIGH tA Previous Word in FIFO1 Output Register tSKEW1 Next Word From FIFO1 (1) tCLKH tCLK 1 CLKA tCLKL 2 tWFF tWFF FFA FIFO1 Full CSA LOW WRA HIGH tENS tENH tENS tENH MBA ENA tDS tDH A0 - A35 To FIFO1 4663 drw 16 NOTES: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown. 2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. Figure 16. FFA Flag Timing and First Available Write when FIFO1 is Full. 25 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 tCLKH tCLK COMMERCIAL TEMPERATURE RANGE tCLKL CLKA CSA LOW W/RA LOW MBA LOW tENS tENH ENA EFA A0 - A35 HIGH tA Previous Word in FIFO2 Output Register tSKEW1 Next Word From FIFO2 (1) tCLKH 1 CLKB tCLK tCLKL 2 tWFF tWFF FFB FIFO2 Full CSB LOW WRB HIGH SIZ1, SIZ0 tENS tENH tENS tENH ENB tDS tDH B0 - B35 4663 drw 17 To FIFO2 NOTES: 1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown. 2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively. Figure 17. FFB Flag Timing and First Available Write when FIFO2 is Full CLKA tENS tENH ENA tSKEW2 CLKB (1) 1 2 tPAE tPAE AEB X Long Word in FIFO1 (X+1) Long Words in FIFO1 tENS tENH ENB 4663 drw 18 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, either SIZ1 = LOW or SIZ0 = LOW). 3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AEB is set LOW by the last word or byte read of the long word, respectively. Figure 18. Timing for AEB when FIFO1 is Almost-Empty 26 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB tENS tENH ENB tSKEW2 (1) 1 CLKA 2 tPAE tPAE AEA (X+1) Long Words in FIFO2 tENH tENS X Long Words in FIFO2 ENA 4663 drw 19 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = HIGH, either SIZ0 = LOW or SIZ1 = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). 3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that writes the last word or byte of the long word, respectively. Figure 19. Timing for AEA when FIFO2 is Almost-Empty tSKEW2 (1) 1 CLKA tENS 2 tENH ENA AFA tPAF tPAF [64-(X+1)] Long Words in FIFO1 (64-X) Long Words in FIFO1 CLKB tENS tENH ENB 4663 drw 20 NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown. 2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, either SIZ0 = LOW or SIZ1 = LOW). 3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of the long word, respectively. Figure 20. Timing for AFA when FIFO1 is Almost-Full (1) tSKEW2 1 CLKB tENS 2 tENH ENB AFB tPAF tPAF [64-(X+1)] Long Words in FIFO2 (64-X) Long Words in FIFO2 CLKA tENS tENH ENA 4663 drw 21 NOTES: 1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown. 2. FIFO2 Write (CSB = LOW, W/RB = HIGH, either SIZ0 = LOW or SIZ1 = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). 3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AFB is set LOW by the last word or byte read of the long word, respectively. Figure 21. Timing for AFB when FIFO2 is Almost-Full 27 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKA tENS tENH CSA W/RA MBA ENA tDS W1 A0 - A35 tDH CLKB tPMF tPMF MBF1 CSB W/RB SIZ1, SIZ0 tENS tENH ENB tEN B0 - B35 tPMR tMDV FIFO1 Output Register tDIS W1 (Remains valid in Mail1 Register after read) 4663 drw 22 NOTE: 1. Port B Parity Generation off (PGB = LOW). Figure 22. Timing for Mail1 Register and MBF1 Flag 28 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE CLKB tENS tENH tSZS tSZH tDS W1 tDH CSB W/RB SIZ1, SIZ0 ENB B0 - B35 CLKA tPMF tPMF MBF2 CSA W/RA MBA tENH tENS ENA tPMR tMDV FIFO2 Output Register tEN A0 - A35 tDIS W1 (Remains valid in Mail2 Register after read) 4663 drw 23 NOTE: 1. Port-A Parity Generation off (PGA = LOW). Figure 23. Timing for Mail2 Register and MBF2 Flag ODD/ EVEN W/RA MBA PGA tPOPE PEFA Valid tPEPE tPOPE Valid Valid tPEPE Valid 4663 drw 24 Figure 24. ODD/EVEN. W/RA, MBA, and PGA to PEFA Timing 29 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE ODD/ EVEN W/RB SIZ1, SIZ0 PGB tPOPE PEFB Valid tPEPE tPOPE Valid Valid tPEPE Valid 4663 drw 25 Figure 25. ODD/EVEN. W/RB, SIZ1, SIZ0, and PGB to PEFB Timing ODD/ EVEN CSA LOW W/RA MBA PGA tEN tPEPB tMDV A8, A17, A26, A35 tPOPB Generated Parity tPEPB Generated Parity Mail2 Data Mail2 Data 4663 drw 26 NOTE: 1. ENA is HIGH. Figure 26. Parity Generation Timing when Reading from the Mail2 Register ODD/ EVEN CSB LOW W/RB SIZ1, SIZ0 PGB B8, B17, B26, B35 tEN tPEPB tMDV tPOPB Generated Parity tPEPB Generated Parity Mail1 Data Mail1 Data 4663 drw 27 NOTE: 1. ENB is HIGH. Figure 27. Parity Generation Timing when Reading from the Mail1 Register 30 IDT72V3614 3.3V, CMOS SyncBiFIFOTM WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE PARAMETER MEASUREMENT INFORMATION 3.3V 330Ω From Output Under Test 30 pF 510Ω (1) LOAD CIRCUIT 3V Timing Input 1.5 V High-Level Input GND tS th 3V 1.5 V 1.5 V Low-Level Input GND VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V GND VOLTAGE WAVEFORMS PULSE DURATIONS 3V Output Enable 1.5 V tPLZ 1.5 V tPZL GND 1.5 V Low-Level Output ≈ 3V Input VOL tPZH VOH High-Level Output GND tW 3V Data, Enable Input 1.5 V 1.5 V 1.5 V tPHZ 3V 1.5 V 1.5 V tPD tPD GND VOH In-Phase Output 1.5 V 1.5 V ≈ OV VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE: 1. Includes probe and jig capacitance. Figure 28. Load Circuit and Voltage Waveforms 31 VOL 4663 drw 28 ORDERING INFORMATION XXXXXX Device Type X XX X Power Speed Package X X Process/ Temperature Range X BLANK 8 Tube or Tray Tape and Reel BLANK Commercial (0°C to +70°C) G Green PF Thin Quad Flat Pack (TQFP, PNG120) 15 Commercial L Low Power 72V3614 64 x 36 x 2 ⎯ 3.3V SyncBiFIFO Clock Cycle Time (tCLK) Speed in Nanoseconds 4663 drw 29 DATASHEET DOCUMENT HISTORY 07/10/2000 05/27/2003 06/14/2005 02/12/2009 01/09/2014 07/23/2019 pg. 1. pg. 6. pgs. 1, 2, 3 and 33. pg. 33. pg. 1, 2, 3, 5, 7, 8, 9 and 32. Datasheet changed to Obsolete Status. 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