72V71643BCG8

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 4,096 x 4,096 IDT72V71643 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JULY 31, 2015 • Internal Loopback for testing FEATURES: • Available in 144-pin Thin Quad Flatpack (TQFP) and • Up to 32 serial input and output streams 144-pin Ball Grid Array (BGA) packages • Maximum 4,096 x 4,096 channel non-blocking switching • Operating Temperature Range -40°°C to +85°°C • Accepts data streams at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or • 3.3V I/O with 5V tolerant inputs and TTL compatible outputs 16.384 Mb/s • • • • • • • • • • • • Rate matching capability: Mux/Demux mode and Split mode Output Enable Indication Pins Per-channel Variable Delay mode for low-latency applications Per-channel Constant Delay mode for frame integrity applications Automatic identification of ST-BUS® and GCI serial streams Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high-impedance output control Per-channel Processor mode to allow microprocessor writes to TX streams Direct microprocessor access to all internal memories Memory block programming for quick setup IEEE-1149.1 (JTAG) Test Port DESCRIPTION: The IDT72V71643 has a maximum non-blocking switch capacity of 4,096 x 4,096 channels with data rates at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s. With 32 inputs and 32 outputs, a variety of rate combinations is supported, under either Mux/Demux mode or Split mode, to allow for switching between streams of different data rates. Output enable indications are provided through optional pins (one pin per output stream, only 16 output streams can be used in this mode) to facilitate external data bus control. For applications requiring 32 streams and 32 per-stream Output Enable indicators, there is also an All Output Enable Feature. FUNCTIONAL BLOCK DIAGRAM Vcc GND RESET TMS TDI TDO TCK ODE TRST Test Port RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 Loopback Output MUX Data Memory Transmit Serial Data Streams Receive Serial Data Streams Connection Memory Internal Registers Timing Unit TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TX10 TX11 TX12 TX13 TX14 TX15 TX16/OEI0 TX17/OEI1 TX18/OEI2 TX19/OEI3 TX20/OEI4 TX21/OEI5 TX22/OEI6 TX23/OEI7 TX24/OEI8 TX25/OEI9 TX26/OEI10 TX27/OEI11 TX28/OEI12 TX29/OEI13 TX30/OEI14 TX31/OEI15 Microprocessor Interface 5902 drw01 CLK F0i FE/ WFPS HCLK DS CS R/W A0-A14 DTA D0-D15 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS® is a trademark of Mitel Corp. JANUARY 2002 1 © 2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5902/5 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS A1 BALL PAD CORNER A RX0 RX1 RX3 RX6 TX1 TX4 TX7 RX10 RX12 RX15 TX10 TX11 CLK ODE RX2 RX5 TX0 TX3 TX6 RX9 RX13 RX14 TX9 TX12 F0i FE/HCLK RESET RX4 RX7 TX2 TX5 RX8 RX11 TX8 TX13 TX14 TMS WFPS TDI VCC VCC VCC VCC VCC VCC TX15 RX16 RX17 TD0 TCK TRST VCC GND GND GND GND VCC RX19 RX20 RX21 DS CS R/W VCC GND GND GND GND VCC RX22 RX23 RX18 A0 A1 A2 VCC GND GND GND GND VCC TX16/ OEI10 TX17/ OEI1 TX18/ OEI2 A3 A4 A5 A14 GND GND GND GND VCC TX19/ OEI3 TX20/ OEI4 TX21/ OEI5 A6 A7 A8 D15 VCC VCC VCC VCC GND TX22/ OEI6 RX24 TX23/ OEI7 A9 A10 DTA D9 D6 D3 D0 TX29/ OEI13 TX26/ OEI10 RX27 RX25 RX26 A11 A12 D12 D11 D7 D4 D1 TX30/ OEI14 TX27/ OEI11 TX24/ OEI8 RX28 RX29 A13 D14 D13 D10 D8 D5 D2 TX31/ OEI15 TX28/ OEI12 TX25/ OEI9 RX31 RX30 1 2 5 6 7 8 9 10 11 B C D E F G H J K L M 3 4 12 5902 drw02 BGA: 1mm pitch, 13mm x 13mm (BC144-1, order code: BC) TOP VIEW NOTES: 1. IC - Internal Connection, tie to Ground for normal operation. 2. All I/O pins are 5V tolerant except for TMS, TDI and TRST. 2 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VCC TX12 TX13 GND TX14 TX15 VCC RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 GND TX16/OEI0 TX17/OEI1 VCC TX18/OEI2 TX19/OEI3 GND TX20/OEI4 TX21/OEI5 VCC TX22/OEI6 TX23/OEI7 GND RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 PIN CONFIGURATIONS (CONTINUED) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 ODE RESET GND CLK F0i FE/HCLK WFPS VCC TMS TDI TDO TCK TRST GND DS CS R/W VCC A0 A1 A2 A3 A4 A5 GND A6 A7 A8 A9 A10 A11 A12 A13 A14 DTA VCC TX11 TX10 GND TX9 TX8 VCC RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 GND TX7 TX6 VCC TX5 TX4 GND TX3 TX2 VCC TX1 TX0 GND RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 VCC TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA) TOP VIEW NOTES: 1. IC - Internal Connection, tie to Ground for normal operation. 2. All I/O pins are 5V tolerant except for TMS, TDI and TRST. 3 VCC TX24/OEI8 TX25/OEI9 GND TX26/OEI10 TX27/OEI11 VCC TX28/OEI12 TX29/OEI13 GND TX30/OEI14 TX31/OEI15 VCC D0 D1 GND D2 D3 VCC D4 D5 GND D6 D7 VCC D08 D09 GND D10 D11 VCC D12 D13 GND D14 D15 5902 drw03 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION SYMBOL NAME GND Vcc TX0-15 Ground. Vcc TX Output 0 to 15 (Three-state Outputs) TX16-31/ TX Output 16 to 31/ OEI0-15 Output Enable Indication 0 to 15 (Three-state Outputs) RX0-31 RX Input 0 to 31 F0i Frame Pulse I/O O O I I FE/HCLK Frame Evaluation/ HCLK Clock CLK Clock TMS Test Mode Select I TDI Test Serial Data In I TDO Test Serial Data Out O TCK TRST Test Clock Test Reset I I RESET Device Reset I WFPS Wide Frame Pulse Select I DS R/W CS A0-14 D0-15 DTA Data Strobe Read/Write Chip Select Address Bus 0 to 14 Data Bus 0-15 Data Transfer Acknowledgment I I I I I/O O ODE Output Drive Enable I I I DESCRIPTION Ground Rail. +3.3 Volt Power Supply. Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s, or 16.384 Mb/s. When all 32 output streams are selected via control register, these pins (TX16-31) are output streams 16 to 31 and may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or 16.384 Mb/s. When output enable indication function is selected, these pins (OEI 0-15) reflect the active or three-state status for the corresponding, (TX0-15) output streams. Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s, or 16.384 Mb/s. This input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS® and GCI specifications. When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK (4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode. Serial clock for shifting data in/out on the serial streams (RX/TX 0-31). JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-up when not driven. JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when JTAG scan is not enabled. Provides the clock to the JTAG test logic. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V71643 is in the normal functional mode. This input (active LOW) puts the IDT72V71643 in its reset state that clears the device internal counters, registers and brings TX0-31 and microport data outputs to a high-impedance state. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device. When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS® /GCI mode. This active LOW input works in conjunction with CS to enable the read and write operations. This input controls the direction of the data bus lines during a microprocessor access. Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V71643. These pins allow direct access to Connection Memory, Data Memory and internal control registers. These pins are the data bits of the microprocessor port. This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance. This is the output enable control for the TX0-31 serial outputs. When ODE input is LOW and the OSB bit of the IMS register is LOW, TX0-31 are in a high-impedance state. If this input is HIGH, the TX0-31 output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per channel control bit in the Connection Memory. 4 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE DESCRIPTION (CONTINUED) OPERATING MODES In addition to Regular mode where input and output streams are operating at the same rate, the IDT72V71643 incorporates a rate matching function in two different modes: Split mode and Mux/Demux mode. In Split mode some of the input streams are set at one rate, while others are set to another rate. Both input and output streams are symmetrical. In Mux/Demux mode, all input streams are operating at the same rate, while output streams are operating at a different rate. All configurations are non-blocking. These two modes can be entered by setting the DR3-0 bits in the Control Register, see Table 5. The IDT72V71643 is capable of switching up to 4,096 x 4,096 channels without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per channel basis. The serial input streams (RX) and serial output streams (TX) of the IDT72V71643 can be run up to 16.384 Mb/s allowing 256 channels per 125μs frame. Depending on the input and output data rates the device can support up to 32 serial streams. With two main operating modes, Processor mode and Connection Mode, the IDT72V71643 can easily switch data from incoming serial streams (Data Memory) or from the controlling microprocessor (Connection Memory). As control and status information is critical in data transmission, the Processor mode is especially useful when there are multiple devices sharing the input and output streams. With three main configuration modes, Regular, Mux/Demux, and Split mode the IDT72V71643 is designed to work in a mixed data-rate environment. In Mux/Demux mode, all of the input streams work at one data rate and the output streams at another. Depending on the configuration, more or less serial streams will be available on the inputs or outputs to maintain a non-blocking switch. In Split Mode, half of the input streams are set at one rate, while the other half are set to another rate. In this mode, both input and output streams are symmetrical. With data coming from multiple sources and through different paths, data entering the device is often delayed. To handle this problem, the IDT72V71643 has a frame evaluation feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +4.5 clock cycles for speeds up to 8 Mb/s or +2.5 clock cycles for 16 Mb/s. (See Table 8 for maximum allowable skew). The IDT72V71643 also provides a JTAG test access port, an internal loopback feature, memory block programming, a simple microprocessor interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities. OUTPUT IMPEDANCE CONTROL In order to put all streams in three-state, all per-channel three-state control bits in the Connection Memory are set (MOD0 and MOD1 = 1) or both the ODE pin and the OSB bit of the Control Register must be zero. If any combination other than 0-0, for the ODE pin and the OSB bit, is used, the three-state control of the streams will be left to the state of the MOD1 and MOD0 bits of the Connection Memory. The IDT72V71643 incorporates a memory block programming feature to facilitate three-state control after reset. See Table 1 for Output HighImpedance Control. SERIAL DATA INTERFACE TIMING When a 16Mb/s serial data rate is required, the master clock frequency will be running at 16.384MHz resulting in a single-bit per clock. For all other cases, 2Mb/s, 4Mb/s, and 8Mb/s, the master clock frequency will be twice the fastest data rate on the serial streams. Use Table 5 to determine clock speed and DR3-0 bits in the Control Register to setup the device. The IDT72V71643 provides two different interface timing modes, ST-BUS® or GCI. The IDT72V71643 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS® or GCI. In ST-BUS®, when running at 16.384MHz, data is clocked out on the falling edge and is clocked in on the subsquent rising-edge. At all other data rates, there are two clock cycles per bit and every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell. See Figure 17 for timing. In GCI format, when running at 16.384MHz, data is clocked out on the rising edge and is clocked in on the subsquent falling edge. At all other data rates, there are two clock cycles per bit and every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell. See Figure 18 for timing. FUNCTIONAL DESCRIPTION DATA AND CONNECTION MEMORY All data that comes in through the RX inputs go through a serial-to-parallel conversion before being stored into internal Data Memory. The 8 KHz frame pulse (F0i) is used to mark the 125μs frame boundaries and to sequentially address the input channels in Data Memory. The Data Memory is only written by the device from the RX streams and can be read from either the TX streams or the microprocessor. Data output on the TX streams may come from either the Serial Input Streams (Data Memory) or from the microprocessor (Connection Memory). In the case that RX input data is to be output, the addresses in Connection Memory are used to specify a stream and channel of the input. The Connection Memory is setup in such a way that each location corresponds to an output channel for each particular stream. In that way, more than one channel can output the same data. In Processor mode, the microprocessor writes data to the Connection Memory locations corresponding to the stream and channel that is to be output. The lower byte (8 least significant bits) of the Connection Memory is output every frame until the microprocessor changes the data or mode of the channel. By using this Processor mode capability, the microprocessor can access input and output time-slots on a per channel basis. The most significant bits of the Connection Memory are used to control per channel functions such as Processor mode, Constant or Variable Delay mode, three-state of output drivers, and the Loopback function. INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). Although input data is synchronous, delays can be caused by variable path serial backplanes and variable path lengths, which may be implemented in large centralized and distributed switching systems. Because data is often delayed this feature is useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 7). The frame offset shown is a function of the data rate, and can be as large as +4.5 master clock (CLK) periods forward with a resolution of ½ clock period. To determine the maximum offset allowed see Table 8. SERIAL INPUT FRAME ALIGNMENT EVALUATION The IDT72V71643 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. Setting the start frame evaluation (SFE) bit low for at least one frame starts a measurement cycle. 5 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE delay equates to 12 output channel time slots. See Figure 2 for this example and other examples of minimum delay to guarantee transmission in the same frame. When the SFE bit in the Control Register is changed from low to high, the evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before a new measurement cycle is started. In ST-BUS ® mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS ® frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 6 and Figure 6 for the description of the frame alignment register. CONSTANT DELAY MODE (MOD1-0 = 0x1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple Data Memory buffer. Input channel data is written into the Data Memory buffers during frame n will be read out during frame n+2. Figure 1 shows examples of Constant Delay mode. MICROPROCESSOR INTERFACE MEMORY BLOCK PROGRAMMING The IDT72V71643 provides users with the capability of initializing the entire Connection Memory block in two frames. To set bits 15 to 13 of every Connection Memory location, first program the desired pattern in bits 9 to 7 of the Control Register. Setting the memory block program (MBP) bit of the control register high enables the block programming mode. When the block programming enable (BPE) bit of the Control Register is set to high, the block programming data will be loaded into the bits 15 to 13 of every Connection Memory location. The other Connection Memory bits (bit 12 to bit 0) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. The IDT72V71643’s microprocessor interface looks like a standard RAM interface to improve integration into a system. With a 15-bit address bus and a 16-bit data bus, read and writes are mapped directly into Data and Connection memories and require only one Master Clock cycle to access. By allowing the internal memories to be randomly accessed in one cycle, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. Table 2 shows the mapping of the addresses into internal memory blocks, Table 3 shows the Control Register information and Figure 13 and Figure 14 shows asynchronous and synchronous microprocessor accesses. LOOPBACK CONTROL The loopback control (LPBK) bit of each Connection Memory location allows the TX output data to be looped backed internally to the RX input for diagnostic purposes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., data from TXn channel m routes to the RXn channel m internally); if the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero and the device must be in regular switch mode (DR3-0 = 0x0, 0x1 or 0x2). MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V71643. The two most significant bits of the address select between the registers, Data Memory, and Connection Memory. If A14 and A13 are HIGH, A12-A0 are used to address the Data Memory (Read Only). If A14 is HIGH and A13 is LOW, A12-A0 are used to address Connection Memory (Read/Write). If A14 is LOW and A13 is HIGH A12-A9 are used to select the Control Register, Frame Alignment Register, and Frame Offset Registers. See Table 2 for mappings. CONTROL REGISTER As explained in the Serial Data Interface Timing and Switching Configurations sections, after system power-up, the Control Register should be programmed immediately to establish the desired switching configuration. The data in the Control Register consists of the Memory Block Programming bit (MBP), the Block Programming Data (BPD) bits, the Begin Block Programming Enable (BPE), the Output Stand By (OSB), Start Frame Evaluation (SFE), and Data Rate Select bits (DR 3-0). As explained in the Memory Block Programming section, the BPE begins the programming if the MBP bit is enabled. This allows the entire Connection Memory block to be programmed with the Block Programming Data bits. DELAY THROUGH THE IDT72V71643 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, Variable throughput delay is best as it ensures minimum delay between input and output data. In wideband data applications, Constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the MOD1 and MOD0 bits of the Connection Memory. CONNECTION MEMORY CONTROL If the ODE pin or the OSB bit is high, the MOD1-0 bits of each Connection Memory location controls the output drivers. See Table 1 for detail. The Processor Channel (PC) mode is entered by a 1-0 of the MOD1-0 of the Connection Memory. In Processor Channel Mode, this allows the microprocessor to access TX output channels. Once the MOD1-0 bits are set, the lower 8 bits of the Connection Memory will be output on the TX serial streams. Also controlled in the Connection Memory is the Variable Delay mode or Constant Delay mode. Each Connection Memory location allows the per-channel selection between Variable and Constant throughput Delay modes and Processor mode. VARIABLE DELAY MODE (MOD1-0 = 0x0) In this mode, the delay is dependent only on the combination of source and destination serial stream speed. Although the minimum delay achievable is dependent on the input and output serial stream speed, if data is switched out +3 channels of the slowest data rate, the data will be switched out in the same frame except if the input and output data rates are both 16 Mb/s (DR3-0 = 0x3). (See Figure 2 for example). For example, given the input data rate is 2 Mb/s and the output data rate is 8 Mb/s, input channel CH0 can be switch out by output channel CH12. In the above example the input streams are slower than the output streams. Also, for every 2 Mb/s time slot there are four 8 Mb/s time slots, thus a three 2 Mb/s channel 6 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., RXn channel m data comes from the TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero and the device must be in regular switch mode (DR3-0 = 0x0, 0x1 or 0x2). acts as the switch and the other as a three-state control device. See Figure 8. It is important to note if the TSI device is programmed for AOE and the OEI is also set, the device will be in the AOE mode not OEI. INITIALIZATION OF THE IDT72V71643 After power up, the IDT72V71643 should be reset. During reset, the internal registers are put into their default state and all TX outputs are put into three-state. After reset however, the state of Connection Memory is unknown. As such, the outputs should be put in high-impedance by holding the ODE low. While the ODE is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the OE bit in Connection Memory. Once the device is configured, the ODE pin (or OSB bit depending on initialization) can be switched. OUTPUT ENABLE INDICATION The IDT72V71643 has the capability to indicate the state of the outputs (active or three-state) by enabling the Output Enable Indication (OEI) in the control register. In the OEI mode however, only half of the output streams are available. If this same capability is desired with all 32 streams, this can be accomplished by using two IDT72V71643 devices. In one device, the All Output Enable (AOE) bit is set to a one while in the other the AOE is set to zero. In this way, one device 7 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 1 — OUTPUT HIGH-IMPEDANCE CONTROL MOD1-0 BITS IN CONNECTION MEMORY 1 and 1 Any, other than 1 and 1 ODE PIN Don’t Care OSB BIT IN CONTROL REGISTER Don’t Care OUTPUT DRIVER STATUS Per Channel High-Impedance 0 0 High-Impedance Any, other than 1 and 1 0 1 Enable Any, other than 1 and 1 1 0 Enable Any, other than 1 and 1 1 1 Enable TABLE 2 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING A14 A13 A12 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R/W Location 1 1 STA4 STA3 STA2 A10 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R Data Memory 1 0 STA4 STA3 STA2 0 1 0 0 1 0 1 0 1 0 1 0 0 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R/W Connection Memory 0 0 0 x x x x x x x x x R/W Control Register 0 0 0 1 x x x x x x x x x R Frame Align Register 0 0 1 0 x x x x x x x x x R/W FOR0 0 0 1 1 x x x x x x x x x R/W FOR1 0 1 0 0 x x x x x x x x x R/W FOR2 1 0 1 0 1 x x x x x x x x x R/W FOR3 1 0 1 1 0 x x x x x x x x x R/W FOR4 0 1 0 1 1 1 x x x x x x x x x R/W FOR5 0 1 1 0 0 0 x x x x x x x x x R/W FOR6 0 1 1 0 0 1 x x x x x x x x x R/W FOR7 8 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 DR3-0 = DH COMMERCIAL TEMPERATURE RANGE 2 Mb/s → 4 Mb/s 1 Frame (125μsec) RX 2 Mb/s A Q(1) • • • • DR3-0 = 9H A(2) • • • • 2 Mb/s → 16 Mb/s 1 Frame (125μsec) RX 2 Mb/s 1 Frame (125μsec) Q •••• TX 4 Mb/s 1 Frame (125μsec) A 1 Frame (125μsec) Q • • • • TX 16 Mb/s 1 Frame (125μsec) Q(1) •••• A(2) • • • • NOTES: 1. Timeslot Q ⎯ 2 Frames ⎯ minimum delay. 2. Timeslot A ⎯ 3 Frames - 1 output channel period ⎯ maximum delay. Figure 1. Constant Delay Mode Examples DR3-0 = 4H(3) 2 Mb/s → 8 Mb/s DR3-0 = CH 2 Mb/s → 8 Mb/s 1 Channel @ 2 Mb/s A RX 2 Mb/s B C D E F 1 Channel @ 8 Mb/s TX 8 Mb/s A(1,2) DR3-0 = AH(3) 16 Mb/s → 8 Mb/s DR3-0 = FH 16 Mb/s → 8 Mb/s 1 Channel @ 16 Mb/s RX 16 Mb/s A B C D E F G H I J 1 Channel @ 8 Mb/s A or B(1,2) TX 8 Mb/s C or D DR3-0 = 3H(3,4) 16 Mb/s → 16 Mb/s RX 16 Mb/s TX 16 Mb/s A B C D E F G H I J K A B B B A L M N O P Q R NOTES: 1. If data is switched at least +3 channel periods of the slower data rate, the data will transmit out in the same frame except if the input and output data rates are both 16 Mb/s (DR3-0 = 0x3). 2. Delay is a function of input channel and output channel combinations, and input and output stream data rate. 3. See switching mode table for input and output speed combinations. 4. When the input and output data rates are both 16 Mb/s, the minimum delay achievable is 6 time slots. Figure 2. Variable Delay Mode Examples 9 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 3 — CONTROL REGISTER (CR) BITS Reset Value: 4000H. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRS OEI OEP AOE MBP 0 BPD2 BPD1 BPD0 BPE OSB SFE DR3 DR2 DR1 DR0 Bit Name 15 Reset (Software Reset) Description A one will reset the device and have the same effect as of the RESET pin. Must be zero for normal operation. 14 OEI (Output Enable Indication) When 1, TX16-31/OEI0-15 will behave as OEI0-15. These outputs will reflect the active or high-impedance state of the corresponding output data streams TX0-15. When 0, TX16-31/OEI0-15 will behave as TX16-31 and react in the same way as TX0-15. 13 OEPOL (Output Enable Polarity) When 1, a one on OEI pin denotes an active state on the output data stream; zero on OEI pin denotes high-impedance state. When 0, a one denotes high-impedance and a zero denotes an active state. 12 AOE When 1, TX0-31 will behave as OEI0-31 accordingly. These outputs will reflect the active or high-impedance state of the corresponding output data streams (TX0-31) in another IDT72V71643 if programmed identically. 11 MBP (Memory Block Program) When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory high bits, bit 13 to bit 15. When 0, this feature is disabled. 10 Unused Must be zero for normal operation. 9-7 BPD2-0 (Block Programming Data) These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD2-0 are loaded into bit 15 and 13 of the Connection Memory. Bit 12 to bit 0 of the Connection Memory are set to 0. 6 BPE A zero to one transition of this bit enables the memory block programming function. The BPE and BPD2-0 bits in the CR register (Begin Block Programming have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the Enable) block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE=1, the other bit in the control register must not be changed for two frames to ensure proper operation. 5 OSB (Output Stand By) When ODE=0 and OSB=0, the output drivers of transmit serial streams are in high-impedance mode. When ODE=1 or OSB=1, the output serial stream drivers function normally. 4 SFE (Start Frame Evaluation) A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero for at least one frame. DR3-0 Input/Output data rate selection. See Table 5 for detailed programming. 3-0 TABLE 4 — CONNECTION MEMORY BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LPBK MOD1 MOD0 SAB4 SAB3 SAB2 SAB1 SAB0 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0 Bit Name Description 15 LPBK (Per Channel Loopback) When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. This feature is offered only when DR3-0 = 0000, 0001 or 0010 is selected via the control register. 14,13 MOD1-0 (Switching Mode Selection) MOD1 MOD0 0 0 0 1 1 0 1 1 12-8 SAB4-0 The binary value is the number of the data stream for the source of the connection. Unused SAB bits must be zero for proper (Source Stream Address Bits) operation. 7-0 MODE Variable Delay mode Constant Delay mode Processor mode Output High-Impedance CAB7-0 The binary value is the number of the channel for the source of the connection. Unused CAB bits must be zero for proper (Source Channel Address Bits) operation. 10 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 5 — SWITCH MODES Switching Mode Regular Mux/Demux DR3 Control Bits DR2 DR1 DR0 Data Rate bits/s Receive Streams Transmit Streams Clock Rate MHz 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 2 M on RX0-31 4 M on RX0-31 8 M on RX0-31 16 M on RX0-15 2 M on TX0-31 4 M on TX0-31 8 M on TX0-31 16 M on TX0-15 4 8 16 16 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 M on RX0-31 8 M on RX0-7 4 M on RX0-31 8 M on RX0-15 16 M on RX0-3 2 M on RX0-31 16 M on RX0-15 8 M on RX0-31 8 M on TX0-7 2 M on TX0-31 8 M on TX0-15 4 M on TX0-31 2 M on TX0-31 16 M on TX0-3 8 M on TX0-31 16 M on TX0-15 16 16 16 16 16 16 16 16 1 1 0 0 2 M on RX0-15; 8 M on RX16-31 2 M on TX0-15; 8 M on TX16-31 16 1 1 0 1 2 M on RX0-15; 4 M on RX16-31 2 M on TX0-15; 4 M on TX16-31 8 1 1 1 0 4 M on RX0-15; 8 M on RX16-31 4 M on TX0-15; 8 M on TX16-31 16 1 1 1 1 8 M on RX0-15; 16 M on RX16-23 8 M on TX0-15; 16 M on TX16-23 16 Split 11 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE DR3-0 = 0H, 1H, 2H 2 Mb/s → 2 Mb/s, 4 Mb/s → 4 Mb/s, 8 Mb/s → 8 Mb/s DR3-0 = 3H 16 Mb/s → 16 Mb/s RX0 TX0 RX0 TX0 16 Mb/s 2, 4, 8 Mb/s 2, 4, 8 Mb/s 16 Mb/s RX15 TX15 RX16 TX16 OPEN RX31 TX31 RX31 TX31 5902 drw04 Figure 3. Regular Switch Mode DR3-0 = 8H 16 Mb/s → 2 Mb/s DR3-0 = 4H 2 Mb/s → 8 Mb/s RX0 RX0 TX0 TX0 16 Mb/s 8 Mb/s RX3 TX7 RX4 TX8 2 Mb/s 2 Mb/s OPEN RX31 RX31 TX31 TX31 5902 drw05 Figure 4. Mux/Demux Mode DR3-0 = FH 8 Mb/s → 8 Mb/s & 16 Mb/s → 16 Mb/s DR3-0 = CH 2 Mb/s → 8 Mb/s & 8 Mb/s → 8 Mb/s RX0 RX0 TX0 TX0 8 Mb/s 2 Mb/s 8 Mb/s 2 Mb/s RX15 TX15 RX16 TX16 8 Mb/s RX15 TX15 RX16 TX16 16 Mb/s 8 Mb/s 16 Mb/s RX23 TX23 RX24 TX24 RX31 TX31 OPEN RX31 TX31 5902 drw06 Figure 5. Split Mode 12 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 6 — FRAME ALIGNMENT REGISTER (FAR) BITS 0000H. Reset Value: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 Bit Name Description 15-13 Unused Will be zero when read. 12 CFE (Complete Frame Evaluation) When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the CR register is changed from 1 to 0. 11 FD11 The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase (Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle. 10-0 FD10-0 (Frame Delay Bits) The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the CR register changes from 1 to 0. (FD10 – MSB, FD0 – LSB) ST-BUS® Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 13 14 15 FE Input (FD[10:0] = 06H) (FD11 = 0, sample at CLK LOW phase) GCI Frame CLK Offset Value 0 1 2 3 4 5 6 7 8 9 10 11 12 FE Input (FD[10:0] = 09H) (FD11 = 1, sample at CLK HIGH phase) 5902 drw07 Figure 6. Example for Frame Alignment Measurement 13 16 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 7 — FRAME INPUT OFFSET REGISTER (FOR) BITS Reset Value: 0000H for all FOR registers. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0 FOR0 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF312 OF311 OF310 DLE31 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 DLE17 OF162 OF161 OF160 DLE16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 DLE21 OF202 OF201 OF200 DLE20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 DLE25 OF242 OF241 OF240 DLE24 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290 DLE29 OF282 OF281 OF280 DLE28 FOR1 Register FOR2 Register FOR3 Register FOR4 Register FOR5 Register FOR6 Register FOR7 Register Name(1) OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) DLEn Description These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 7. ST-BUS® mode: (Data Latch Edge) DLEn = 0, if clock rising edge is at the ¾ point of the bit cell. DLEn = 1, if when clock falling edge is at the ¾ of the bit cell. GCI mode: DLEn = 0, if clock falling edge is at the ¾ point of the bit cell. DLEn = 1, if when clock rising edge is at the ¾ of the bit cell. NOTE: 1. n denotes an input stream number from 0 to 31. 14 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 8 — MAXIMUM ALLOWABLE SKEW Switching Mode Regular Mux/Demux DR3 Control Bits DR2 DR1 DR0 Receive Streams Data Rate bits/s Transmit Streams Maximum allowable skew 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 2 M on RX0-31 4 M on RX0-31 8 M on RX0-31 16 M on RX0-15 2 M on TX0-31 4 M on TX0-31 8 M on TX0-31 16 M on TX0-15 +4.5 +4.5 +4.5 +2.5 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 M on RX0-31 8 M on RX0-7 4 M on RX0-31 8 M on RX0-15 16 M on RX0-3 2 M on RX0-31 16 M on RX0-15 8 M on RX0-31 8 M on TX0-7 2 M on TX0-31 8 M on TX0-15 4 M on TX0-31 2 M on TX0-31 16 M on TX0-3 8 M on TX0-31 16 M on TX0-15 +1.5 +4.5 +1.5 +4.5 +2.5 +1.5 +4.5 +4.5 1 1 0 0 2 M on RX0-15; 8 M on RX16-31 2 M on TX0-15; 8 M on TX16-31 +1.5 +4.5 1 1 0 1 2 M on RX0-15; 4 M on RX16-31 2 M on TX0-15; 4 M on TX16-31 +1.5 +4.5 1 1 1 0 4 M on RX0-15; 8 M on RX16-31 4 M on TX0-15; 8 M on TX16-31 +1.5 +4.5 1 1 1 1 8 M on RX0-15; 16 M on RX16-23 8 M on TX0-15; 16 M on TX16-23 +4.5 +2.5 Split 15 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 9 — OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELAY BITS (FD11, FD2-0) Input Stream Measurement Result from Corresponding Frame Delay Bits Offset Bits Offset FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn No clock period shift (Default) 1 0 0 0 0 0 0 0 + 0.5 clock period shift 0 0 0 0 0 0 0 1 + 1.0 clock period shift 1 0 0 1 0 0 1 0 + 1.5 clock period shift 0 0 0 1 0 0 1 1 + 2.0 clock period shift 1 0 1 0 0 1 0 0 + 2.5 clock period shift 0 0 1 0 0 1 0 1 + 3.0 clock period shift 1 0 1 1 0 1 1 0 + 3.5 clock period shift 0 0 1 1 0 1 1 1 + 4.0 clock period shift 1 1 0 0 1 0 0 0 + 4.5 clock period shift 0 1 0 0 1 0 0 1 NOTE: 1. See Table 8 for maximum allowable offsets. ST-BUS® F0i 16.384 MHz CLK RX Stream (16.384 Mb/s) Bit 7 RX Stream (16.384 Mb/s) RX Stream (16.384 Mb/s) Bit 6 Bit 5 Bit 4 offset = 0, DLE = 0 Bit 7 Bit 6 Bit 5 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 Bit 7 Bit 6 Bit 4 Bit 5 GCI F0i 16.384 MHz CLK RX Stream (16.384 Mb/s) Bit 0 RX Stream (16.384 Mb/s) RX Stream (16.384 Mb/s) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 2 Bit 1 5902 drw08 Figure 7. Examples for Input Offset Delay Timing in 16 Mb/s mode 16 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE ST-BUS® F0i CLK RX Stream Bit 7 RX Stream Bit 7 Bit 7 RX Stream DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 Bit 7 RX Stream offset = 0, denotes the 3/4 point of the bit cell GCI F0i CLK RX Stream Bit 0 Bit 0 RX Stream RX Stream RX Stream Bit 0 offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 Bit 0 denotes the 3/4 point of the bit cell Figure 7. Examples for Input Offset Delay Timing in 8 Mb/s, 4 Mb/s and 2 Mb/s mode (Continued) 17 5902 drw09 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE JTAG SUPPORT INSTRUCTION REGISTER In accordance with the IEEE-1149.1 standard, the IDT72V71643 uses public instructions. The IDT72V71643 JTAG Interface contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. The IDT72V71643 JTAG interface conforms to the Boundary-Scan standard IEEE-1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. TEST ACCESS PORT (TAP) The Test Access Port (TAP) provides access to the test functions of the IDT72V71643. It consists of three input pins and one output pin. •Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. •Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not driven from an external source. •Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VCC when it is not driven from an external source. •Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high-impedance state. •Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VCC. Value 00 11 01 or 10 Instruction EXTEST BYPASS SAMPLE/PRELOAD JTAG Instruction Register Decoding TEST DATA REGISTER As specified in IEEE-1149.1, the IDT72V71643 JTAG Interface contains two test data registers: •The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V71643 core logic. •The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The IDT72V71643 boundary scan register bits are shown in Table 10. Bit 0 is the first bit clocked out. All three-state enable bits are active high. 18 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE TABLE 10 — BOUNDARY SCAN REGISTER BITS Device Pin ODE RESET CLK F0i FE/HCLK WFPS DS CS R/W A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DTA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TX31/OEI15 TX30/OEI14 TX29/OEI13 TX28/OEI12 TX27/OEI11 TX26/OEI10 TX25/OEI9 TX24/OEI8 RX31 RX30 RX29 RX28 Boundary Scan Bit 0 to bit 168 Three-State Output Input Control Scan Cell Scan Cell 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Device Pin RX27 RX26 RX25 RX24 TX23/OEI7 TX22/OEI6 TX21/OEI5 TX20/OEI4 TX19/OEI3 TX18/OEI2 TX17/OEI1 TX16/OEI0 RX23 RX22 RX21 RX20 RX19 RX18 RX17 RX16 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 19 Boundary Scan Bit 0 to bit 168 Three-State Output Input Control Scan Cell Scan Cell 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE Using OEI AOE=0 RX0-15 RX0-15 TX0-15 RX16-31 TX0-15 OEI0-15 OEI0-15 AOE=0 RX0-15 TX0-15 RX16-31 TX16-31 RX16-31 AOE=0 RX0-15 RX16-31 TX0-15 RX16-31 OEI16-31 OEI0-15 AOE=0 RX0-15 TX0-15 RX16-31 RX16-31 AOE=0 Using AOE RX0 RX0 TX0 RX31 RX31 TX31 RX0 RX0 OEI0 RX31 RX31 OEI31 AOE=1 5902 drw10 Figure 8. Using All Output Enable (AOE) 20 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE RECOMMENDED OPERATING CONDITIONS(1) ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Min. Max. Unit Supply Voltage 3.0 3.6 V VCC Vi Voltage on Digital Inputs GND -0.3 5.3 V IO Current at Digital Outputs -50 50 mA TS Storage Temperature -55 +125 °C PD Package Power Dissapation ⎯ 2 W Symbol NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Parameter Min. Typ. Max. Unit VCC Positive Supply 3.0 3.3 3.6 V VIH Input HIGH Voltage 2.0 ⎯ 5.3 V VIL Input LOW Voltage ⎯ ⎯ 0.8 V TOP Operating Temperature Commercial -40 25 +85 °C NOTE: 1. Voltages are with respect to Ground unless otherwise stated. DC ELECTRICAL CHARACTERISTICS Symbol Parameter ICC (2) IIL (3,4) IOZ(3,4) (5) Min. Typ. Max. Units Supply Current - - 75 mA Input Leakage (input pins) - - 60 μA High-impedance Leakage - - 60 μA VOH Output HIGH Voltage 2.4 - - V VOL(6) Output LOW Voltage - - 0.4 V NOTES: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Outputs unloaded. 3. 0 ≤ V ≤ VCC. 4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V). 5. IOH = 10 mA. 6. IOL = 10 mA. AC ELECTRICAL CHARACTERISTICS - TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS Symbol Rating Level Unit 1.5 V V TT TTL Threshold VHM TTL Rise/Fall Threshold Voltage HIGH 2.0 V VLM TTL Rise/Fall Threshold Voltage LOW 0.8 V Test Point VCC RL Output Pin S1 S1 is open circuit except when testing output levels or high-impedance states. S2 CL GND S2 is switched to VCC or GND when testing output levels or high-impedance states. GND 5902 drw11 Figure 9. Output Load 21 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK Symbol Parameter tFPW(1) Frame Pulse Width (ST-BUS®, GCI) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s or 16.384 Mb/s Min. Typ. Max. Units 26 26 26 ⎯ ⎯ ⎯ 295 145 65 ns ns ns tFPS(1) Frame Pulse Setup time before CLK falling (ST-BUS® or GCI) 5 ⎯ ⎯ ns tFPH(1) Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI) 10 ⎯ ⎯ ns tCP(1) CLK Period Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s or 16.384 Mb/s 190 110 58 ⎯ ⎯ ⎯ 300 150 70 ns ns ns CLK Pulse Width HIGH Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s or 16.384 Mb/s 85 50 20 ⎯ ⎯ ⎯ 150 75 40 ns ns ns CLK Pulse Width LOW Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s or 16.384 Mb/s 85 50 20 ⎯ ⎯ ⎯ 150 75 40 ns ns ns tr, tf Clock Rise/Fall Time ⎯ ⎯ 10 ns tHFPW(2) Wide Frame Pulse Width HCLK = 4.096 MHz HCLK = 8.192 MHz tCH(1) tCL(1) 244 122 ns ns tHFPS(2) Frame Pulse Setup Time before HCLK 4 MHz falling 50 ⎯ 150 ns tHFPH(2) Frame Pulse Hold Time from HCLK 4 MHz falling 50 ⎯ 150 ns tHFPS Frame Pulse Setup Time before HCLK 8 MHz rising 45 ⎯ 90 ns tHFPH(2) Frame Pulse Hold Time from HCLK 8 MHz rising 45 ⎯ 90 ns t HCLK Period @ 4.096 MHz @ 8.192 MHz (2) HCP(2) 244 122 ns ns tHr, tHf HCLK Rise/Fall Time ⎯ ⎯ 10 ns tDIF(2) Delay between falling edge of HCLK and falling edge of CLK -10 ⎯ 10 ns NOTES: 1. WFPS Pin = 0. 2. WFPS Pin = 1. 22 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE RESET tZR tRZ tRZ tRS TX tODE ODE 5902 drw12 Figure 10. Reset and ODE Timing CLK (ST-BUS® or WFPS mode) CLK (GCI mode) tDZ TX ODE VALID DATA tODE tODE tZD TX TX VALID DATA VALID DATA 5902 drw14 5902 drw13 Figure 11. Serial Output and External Control Figure 12. Output Driver Enable (ODE) 23 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS - MICROPROCESSOR INTERFACE TIMING Symbol Parameter Min. Typ. Max. Units tCSS tRWS CS Setup from DS falling 0 ⎯ ⎯ ns R/W Setup from DS falling 3 ⎯ ⎯ ns tADS Address Setup from DS falling 2 ⎯ ⎯ ns tCSH CS Hold after DS rising 0 ⎯ ⎯ ns tRWH R/W Hold after DS Rising 3 ⎯ ⎯ ns tADH Address Hold after DS Rising 2 ⎯ ⎯ ns tDDR(1) Data Setup from DTA LOW on Read 2 ⎯ ⎯ ns tDHR(1,2,3) Data Hold on Read 10 15 25 ns tDSW Data Setup on Write (Fast Write) 10 ⎯ ⎯ ns tSWD Valid Data Delay on Write (Slow Write) - ⎯ 0 ns tDHW Data Hold on Write 5 ⎯ ⎯ ns tDSPW DS Pulse Width 5 ⎯ ⎯ ns tCKAK Clock to ACK ⎯ ⎯ 35 ns tAKD (1) Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory 30 345 200 120 ns ns ns ns @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s or 16.384 Mb/s tAKH (1,2,3) tDSS (4) Acknowledgment Hold Time Data Strobe Setup Time ⎯ ⎯ 15 ns 2 ⎯ ⎯ ns NOTES: 1. CL= 150pF 2. RL = 1K 3. High-Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. To achieve one clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst case memory access operation is determined by tAKD. 24 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE DS tCSS tCSH tCSS tCSH CS tRWS tRWH tRWS tRWH R/W tADS A0-A14 tADH tADH tADS VALID READ ADDRESS VALID WRITE ADDRESS tDSW tDHR tDHW VALID WRITE DATA D0-D15 VALID READ DATA tDDR tAKD tAKH tAKD tAKH DTA 5902 drw15 Figure 13. Asyncronous Bus Timing CLK GCI CLK ST-BUS® tDSS tDSPW tDSS DS tCSS tCSH tCSS tCSH tRWS tRWH tRWS tRWH tADS tADH tADS tADH CS R/W A0-A14 tSWD D0-D15 VALID READ ADDRESS VALID WRITE ADDRESS tDHW tDHR VALID WRITE DATA tCKAK VALID READ DATA tDDR tAKH tCKAK DTA tAKH 5902 drw16 Figure 14. Syncronous Bus Timing 25 tFPS tOEIE tOEIE tZD tFPW tSOD tFPH Bit 7 tCP Bit 6 tCH Bit 5 tCL tr Bit 4 tf Bit 3 Figure 15. Output Enable Indicator Timing (8 Mb/s ST-BUS® ) NOTES: 1. When OEPOL = 1, OEI is HIGH when TX is active and LOW when TX is in three-state. 2. When OEPOL = 0, OEI is LOW when TX is active and HIGH when TX is in three-state. OEI(2) OEI(1) TX 8 Mb/s CLK 16.384 MHz F0i Bit 2 Bit 1 Bit 0 tOEID tOEID tDZ 5902 drw17 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE 26 27 Bit 1 Bit 1 RX 16 Mb/s Bit 2 Bit 0 Bit 0 Bit 1 RX 8 Mb/s TX 16 Mb/s Bit 0 Bit 1 Bit 2 tDIF tDIF tHFPS TX 8 Mb/s HCLK4.096 MHz HCLK8.192 MHz CLK16.384 MHz F0i Bit 0 tSIS Bit 7 tSOD tSIS tSOD tSIH Bit 5 tSIH Bit 6 Bit 7 Bit 7 Bit 6 tHFPH Bit 7 tHFPW Bit 5 Bit 4 Bit 4 Bit 6 Bit 6 Bit 2 Bit 2 Bit 1 Bit 1 Bit 0 tCP Figure 16. WFPS Timing Bit 3 Bit 3 Bit 5 Bit 5 tr tCH Bit 0 Bit 7 Bit 4 Bit 4 tf tCL Bit 7 Bit 6 Bit 6 Bit 5 Bit 3 Bit 3 tHr tHCL Bit 5 Bit 4 tHf Bit 3 Bit 2 Bit 2 Bit 4 tHCP tHCH Bit 3 Bit 2 tHCL Bit 2 Bit 1 Bit 0 tHCH Bit 1 tHr Bit 1 Bit 1 tHCP Bit 7 Bit 0 Bit 0 5902 drw18 Bit 0 tHf IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS(1) ⎯ SERIAL STREAM (ST-BUS® and GCI) Symbol Parameter tSIS RX Setup Time Min. Typ. Max. Units 5 ⎯ ⎯ ns tSIH RX Hold Time tSOD TX Delay – Active to Active 10 ⎯ ⎯ ns ⎯ ⎯ 30 ns tDZ(1) TX Delay – Active to High-Z tZD(1) TX Delay – High-Z to Active ⎯ ⎯ 30 ns ⎯ ⎯ 30 ODE(1) ns t tOEIE Output Driver Enable (ODE) Delay ⎯ ⎯ 30 ns Output Enable Indicator (OEI) Enable ⎯ ⎯ 40 ns tOEID Output Enable Indicator (OEI) Disable ⎯ ⎯ 25 ns tRZ Active to High-Z on Master Reset ⎯ ⎯ 30 ns tZR High-Z to Active on Master Reset ⎯ ⎯ 30 ns tRs Reset pulse width 100 ⎯ ⎯ ns NOTE: 1. High-Impedance is measured by pulling to the appropriate rail with RL (1KΩ), with timing corrected to cancel time taken to discharge CL (150 pF). 28 29 RX 2 Mb/s TX 2 Mb/s RX 4 Mb/s TX 4 Mb/s RX 8 Mb/s TX 8 Mb/s RX 16 Mb/s TX 16 Mb/s CLK16.384 MHz F0i RX 2 Mb/s TX 2 Mb/s Bit 7 Bit 7 Bit 6 Bit 6 Bit 7 Bit 6 Bit 6 Bit 5 tr Bit 7 tf Bit 7 tSOD tSOD tSOD tFPH tSIH Bit 0 Bit 0 tSIS tSOD tFPS tFPW tSOD tSOD tSOD Bit 6 Bit 6 Bit 0 Bit 1 Bit 1 Bit 7 Bit 7 Bit 0 tSIS tSIS tSIH Bit 7 Bit 7 tSIS tSOD tFPH tFPW tFPS Bit 0 Bit 0 Bit 0 Bit 7 Bit 0 tf Bit 7 Bit 7 Bit 0 Bit 0 RX 4 Mb/s Bit 0 Bit 1 Bit 1 Bit 0 tr TX 4 Mb/s Bit 1 Bit 1 TX 8 Mb/s RX 8 Mb/s Bit 2 Bit 2 RX 16 Mb/s TX 16 Mb/s CLK16.384 MHz F0i Bit 7 tSIS Bit 2 tSIS Bit 2 Bit 7 Bit 0 tSIH tSIH Bit 5 Bit 5 Bit 1 Bit 3 tSIH Bit 0 Bit 1 Bit 3 tSIH Bit 6 Bit 6 Bit 4 Bit 4 Bit 0 Bit 2 tSIS Bit 5 Bit 5 Bit 2 tCL Bit 7 tSIH Bit 6 Bit 1 Bit 1 Bit 6 Bit 4 Bit 4 Bit 0 Bit 0 tSIS Bit 2 Bit 0 tSIH Bit 1 Bit 6 Bit 6 Bit 1 Bit 3 Bit 7 Bit 3 Bit 7 Figure 18. GCI Timing Bit 2 Bit 5 Bit 5 Bit 0 Bit 7 Bit 7 Figure 17. ST-BUS® Timing tCP tCL Bit 4 tCP Bit 4 tCH Bit 7 Bit 3 Bit 3 tCH Bit 0 Bit 5 Bit 4 Bit 5 Bit 5 Bit 1 Bit 4 Bit 1 Bit 3 Bit 3 Bit 6 Bit 6 Bit 2 Bit 2 Bit 2 Bit 5 Bit 3 Bit 3 Bit 2 Bit 5 Bit 6 Bit 3 Bit 5 Bit 3 Bit 2 Bit 2 Bit 4 Bit 4 Bit 1 Bit 4 Bit 4 Bit 2 Bit 1 Bit 1 Bit 2 Bit 5 Bit 6 Bit 6 Bit 1 Bit 3 Bit 6 Bit 0 Bit 0 Bit 0 Bit 0 Bit 4 Bit 6 Bit 4 Bit 6 Bit 5 Bit 1 Bit 1 Bit 7 Bit 3 Bit 5 Bit 3 Bit 7 5902 drw20 Bit 7 5902 drw19 Bit 7 Bit 7 Bit 7 Bit 7 IDT72V71643 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 4,096 x 4,096 COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XXXXX XX XX Device Type Package Process/ Temp. Range Blank Commercial (-40ºC to +85ºC) BCG DAG BGA - Green (BGA, BC144-1) TQFP – Green (TQFP, DA144-1) 72V71643 4096 x 4096 – 3.3V Time Slot Interchange Digital Switch DATASHEET DOCUMENT HISTORY 5/01/2000 6/07/2000 10/10/2000 11/20/2000 03/09/2001 08/20/2001 10/22/2001 1/04/2002 12/03/2012 8/12/2014 pg. 1 pgs. 3 and 4. pgs. 1 through 30. pgs.10. pg. 21 pg. 24. pg. 1. pgs. 1 and 21. pg. 30 pg 1 Product Discontinuation Notice, CQ-14-06 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 30 for Tech Support: 408-330-1753 email: TELECOMhelp@idt.com IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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