72V8985J8

3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256 and write access to individual channels. As an important function of a digital switch is to maintain sequence integrity and minimize throughput delay, the IDT72V8985 is an ideal solution for most switching needs. FEATURES: • • • • • • • • • • • IDT72V8985 256 x 256 channel non-blocking switch Automatic signal identification (ST-BUS®, GCI) 8 RX inputs—32 channels at 64 Kbit/s per serial line 8 TX outputs—32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) Frame Integrity for data applications 3.3V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC) Operating Temperature Range -40°° C to +85°°C 3.3V I/O with 5V Tolerant Inputs FUNCTIONAL DESCRIPTION Frame sequence, constant throughput delay, and guaranteed minimum delay are high priority requirements in today’s integrated data and multimedia networks. The IDT72V8985 provides these functions on a per-channel basis using a standard microprocessor control interface. Each of the eight serial lines is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data. In Processor Mode, the microprocessor can access the input and output time slots to control other devices such as ISDN transceivers and trunk interfaces. Supporting both GCI and ST-BUS® formats, IDT72V8985 has incorporated an internal circuit to automatically identify the polarity and format of the frame synchronization. A functional block diagram of the IDT72V8985 device is shown on page 1. The serial streams operate continuously at 2.048 Mb/s and are arranged in 125µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and eight output (TX0-7) serial streams are provided in the IDT72V8985 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz. DESCRIPTION: The IDT72V8985 is a ST-BUS®/GCI compatible digital switch controlled by a microprocessor. The IDT72V8985 can handle as many as 256, 64 Kbit/s input and output channels. Those 256 channels are divided into 8 serial inputs and outputs, each of which consists of 32 channels. The IDT72V8985 provides perchannel variable or constant throughput delay modes and microprocessor read FUNCTIONAL BLOCK DIAGRAM C4i F0i VCC GND Timing Unit RX0 RESET(1) ODE TX0 Output MUX RX1 TX1 TX2 RX2 RX3 RX4 Receive Serial Data Streams Transmit Serial Data Streams Data Memory RX5 Control Register RX6 RX7 Connection Memory TX3 TX4 TX5 TX6 Microprocessor Interface TX7 5707 drw01 DS CS R/W A0/ DTA D0/ A5 D7 CCO NOTE: 1. The RESET Input is only provided on the SSOP package. IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp. AUGUST 2003 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5707/5 IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 Commercial Temperature Range 39 TX3 8 38 TX4 RX5 9 37 TX5 RX6 10 36 RX7 11 VCC TX1 TX2 DNC(1) 36 35 34 ODE TX0 38 37 39 RX0 DTA CCO 40 RX1 41 RX2 42 DNC(1) 40 7 RX4 DNC(1) TX2 41 RX3 43 TX1 42 INDEX 44 ODE TX0 43 RX0 DTA 2 CCO RX1 3 44 RX2 4 1 DNC(1) 5 INDEX 6 PIN CONFIGURATION 30 TX6 35 TX7 RX7 5 29 TX7 12 34 GND VCC 6 28 GND F0i 13 33 D0 F0i 7 27 C4i 14 32 D1 8 26 D0 D1 A0 15 31 D2 C4i A0 9 25 D2 A1 10 24 D3 A2 11 23 D4 26 27 D6 D5 12 25 D7 28 24 23 R/W CS 21 A5 22 20 A4 D4 19 D3 29 18 30 17 A3 16 A2 DNC(1) A1 22 4 21 RX6 20 TX5 TX6 19 31 18 3 17 TX4 RX5 16 TX3 32 15 33 2 14 1 RX4 13 RX3 PLCC: 0.05in. pitch, 0.65in. x 0.65in (J44-1, order code: J) TOP VIEW DNC(1) D5 D6 CS D7 DS R/W A5 A4 A3 DNC(1) DNC (1) DS 5707 drw03 5707 drw02 PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW GND 1 48 CCO DTA 2 47 ODE RX0 3 46 TX0 RX1 4 45 TX1 RX2 5 44 TX2 DNC(1) 6 43 DNC(1) RX3 7 42 TX3 RX4 8 41 TX4 RX5 9 40 TX5 RX6 10 39 TX6 RX7 11 38 TX7 VCC 12 37 GND RESET(2) 13 36 VCC F0i 14 35 D0 C4i 15 34 D1 A0 16 33 D2 A1 17 32 D3 A2 18 31 D4 DNC(1) 19 30 DNC(1) A3 20 29 D5 A4 21 28 D6 A5 22 27 D7 DS 23 26 CS R/W 2 4 25 GND 5707 drw04 TOP VIEW Package Type SSOP: 0.025in. pitch, 0.625in. x 0.295in. Reference Identifier SO48-1 NOTES: 1. DNC - Do Not Connect 2. The RESET Input is only provided on the SSOP package. 2 Order Code PV IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 Commercial Temperature Range PIN DESCRIPTIONS SYMBOL GND VCC DTA RX0-7 F0i C4i NAME Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 7 Frame Pulse I/O O I I Clock Address 0 to 5 Data Strobe I I I Read/Write Chip Select Data Bus 0 to 7 I I I/O O ODE TX Outputs 0 to 7 (Three-state Outputs) Output Drive Enable CCO Control Channel Output O RESET Device Reset (Schmitt Trigger Input) I A0-A5 DS R/W CS D0-D7 TX0-7 I DESCRIPTION Ground Rail. +3.3 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input accepts and automatically identifies frame synchronization signals formatted according to different backplane specifications such as ST-BUS® and GCI. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT72V8985 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations. This input (active LOW) puts the IDT72V8985 in its reset state that clears the device internal counters, registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device. 3 IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 Commercial Temperature Range OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master output three-state control pin. If the ODE input is held LOW all TDM (Time Division Multiplexed) outputs will be placed in high impedance regardless Connection Memory High programming. However, if ODE is HIGH, the contents of Connection Memory High control the output state on a per-channel basis. FUNCTIONAL DESCRIPTION (Cont'd) The received serial data is internally converted to parallel by the on chip serial-to-parallel converters and stored sequentially in a 256-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed. Depending on the type of information to be switched, the IDT72V8985 device can be programmed to perform time slot interchange functions with different throughput delay capabilities on a per-channel basis. The Variable Delay mode, most commonly used for voice applications, can be selected ensuring minimum throughput delay between input and output data. In Constant Delay mode, used in multiple or grouped channel data applications, the integrity of the information through the switch is maintained. SERIAL INTERFACE TIMING The IDT72V8985 master clock (C4i) is 4.096 MHz signal allowing serial data link configuration at 2.048 Mb/s to be implemented. The IDT72V8985 can automatically detect the presence of an input frame pulse, identify the type of backplane present on the serial interface, and format the synchronization pulse according to ST-BUS® or GCI interface specifications (active HIGH in GCI or active LOW in ST-BUS®). Upon determining the correct interface Connected to the serial port, the internal timing unit establishes the appropriate serial data bit transmit and sampling edges. In ST-BUS® mode, every second falling edge of the 4.096 MHz clock marks a boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI mode every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries. CONNECTION MEMORY Data to be output on the serial streams may come from two sources: Data Memory or Connection Memory. The Connection Memory is split into HIGH and LOW parts and is associated with particular TX output streams. In Processor Mode, data output on the TX streams is taken from the Connection Memory Low and originates from the microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is read from Data Memory and originated from the incoming RX streams. Data destined for a particular channel on the serial output stream is read internally during the previous channel time slot to allow time for memory access and internal parallel-to-serial conversion. DELAY THROUGH THE IDT72V8985 The transfer of information from the input serial streams to the output serial streams results in a delay through the device. The delay through the IDT72V8985 device varies according to the mode selected in the V/C bit of the Connection Memory High. CONNECTION MODE In Connection Mode, the addresses of input source for all output channels are stored in the Connection Memory Low. The Connection Memory Low locations are mapped to corresponding 8-bit x 32-channel output. The contents of the Data Memory at the selected address are then transferred to the parallelto-serial converters before being output. By having the output channel to specify the input channel through the Connection Memory, input channels can be broadcast to several output channels. VARIABLE DELAY MODE The delay in Variable Delay Mode is dependent only on the combination of source and destination on the input and output streams. The minimum delay achievable in the IDT72V8985 device is three time slots. In the IDT72V8985 device, the information that is to be output in the same channel position as the information is input (position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if the input channels succeeding (n+1, n+2) the channel position as the information is input. The information switched to the third time slot after the input has entered the device (for instance, input channel 0 to output channel 3 or input channel 30 to output channel 1), is always output three channels later. Any switching configuration that provides three or more time slots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the IDT72V8985 device in Variable Delay Mode. An example is shown in Figure 3. PROCESSOR MODE In Processor Mode the CPU writes data to the Connection Memory Low locations which correspond to the output link and channel number. The contents of the Connection Memory Low are transferred to the parallel-to-serial converter one channel before it is to be output and are transmitted each frame to the output until it is changed by the CPU. CONTROL The Connection Memory High bits (Table 4) control the per-channel functions available in the IDT72V8985. Output channels are selected into specific modes such as: Processor Mode or Connection mode, Variable or Constant throughput delay modes, Output Drivers Enabled or in three-state condition. There is also one bit to control the state of the CCO output pin. RX Receive Serial Data Streams Data Memory Connection Memory Transmit Serial Data Streams CONSTANT DELAY MODE In this mode frame integrity is maintained in all switching configurations by Receive Serial Data Streams TX Data Memory Connection Memory Transmit Serial Data Streams TX 5707 drw06 5707 drw05 Microprocessor Figure 2. Processor Mode Figure 1. Connection Mode 4 IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 Commercial Temperature Range The Processor Enable bit (bit 6) places every output channel on every output stream in Processor Mode; i.e., the contents of the Connection Memory LOW (CML, see Table 5) are output on the output streams once every frame unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8985 behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory High (CMH, see Table 4) locations were set to HIGH, regardless of the actual value. If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output. If the ODE input pin is LOW, then all the serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) for that particular channel. The contents of bit 1 (CCO) of each Connection Memory High Location (see Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/ s output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the CCO output is transmitted LOW. The contents of the 256 CCO bits of the CMH are transmitted sequentially on to the CCO output pin and are synchronous to the TX streams. To allow for delay in any external control circuitry the contents of the CCO bit is output one channel before the corresponding channel on the TX streams. For example, the contents of CCO bit in position 0 (corresponding to TX0, CH0), is transmitted synchronously with the TX channel 31, bit 7. Bit 1's of CMH for channel 1 of streams 0-7 are output synchronously with TX channel 0 bits 7-0. making use of a multiple Data Memory buffer technique where input channels written in any of the buffers during frame N will be read out during frame N+2. In the IDT72V8985, the minimum throughput delay achievable in Constant Delay mode will be 32 time slots; for example, when input time slot 32 (channel 31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay is achieved when the first time slot in a frame (channel 0) is switched to the last time slot in the frame (channel 31), resulting in 94 time slots of delay (see Figure 4). To summarize, any input time slot from input frame N will be always switched to the destination time slot on output frame N+2. In Constant Delay mode the device throughput delay is calculated according to the following formula: DELAY=[32+(32-IN)+(OUT-1)] IN =the number of the input time slot (from 1 to 32) OUT = the number of the output time slot (from 1 to 32). MICROPROCESSOR PORT The IDT72V8985 microprocessor port is a non-multiplexed bus architecture. The parallel port consists of an 8-bit parallel data bus (D0-D7), six address input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control Registers, Connection Memory Low, Connection Memory High, and the Data Memory. All locations are read/written except for the Data Memory, which can be read only. Accesses from the microport to the Connection Memory and the Data Memory are multiplexed with accesses from the input and output TDM ports. This can cause variable Data Acknowledge delays (DTA). In the IDT72V8985 device, the DTA output provides a maximum acknowledgment delay of 800ns for read/write operations in the Connection Memory. However, for operations in the Data Memory (Processor Mode), the maximum acknowledgment delay can be 1220ns. INITIALIZATION During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two Connected TX outputs drive the bus simultaneously. With the CMH setup, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the Connection Memory High bits outputs. The reset pin is designed to be used with board reset circuitry. During reset the TX serial streams will be put into high-impedance and the state of internal registers and counters will be reset. As the connection memory can be in any state after a power up, the ODE pin should be used to hold the TX streams in high-impedance until the per-channel output enable control in the connection memory high is appropriately programmed. The main difference between ODE and reset is, reset alters the state of the registers and counters where as ODE controls only the high-impedance state of the TX streams. RESET input is only provided on the SSOP packages. SOFTWARE CONTROL If the A5, A1, A0 address line inputs are LOW then the IDT72V8985 Internal Control Register is addressed (see Table 2). If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. As explained in the Control Register description, the address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of IDT72V8985 Data and Connect memories. See Figure 5 for accessing internal memories. The data in the control register consists of Memory Select and Stream Address bits, Split Memory and Processor Enable bits (Table 3). In Split Memory mode (Bit 7 of the Control register) reads are from the Data Memory and writes are to the Connection Memory LOW. The Memory Select bits allow the Connection Memory High or LOW or the Data Memory to be chosen, and the Stream Address bits define internal memory subsections corresponding to input or output streams. TABLE 2  ADDRESS MAPPING TABLE 1  VARIABLE DELAY MODE Input Channel n Output Channel m=n, n+1 or n+2 Throughput Delay m-n+32 time slot n m>n+2 m-n time slot n m