IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS 16-BIT
IDT54/74FCT162511AT/CT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
FEATURES:
DESCRIPTION:
•
•
•
•
The FCT162511T 16-bit registered/latched transceiver with parity is built
using advanced dual metal CMOS technology. This high-speed, low-power
transceiver combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched, or clocked modes. The device has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A direction. Error
checking is done at the byte level with separate parity bits for each byte. Separate
error flags exits for each direction with a single error flag indicating an error for
either byte in the A-to-B direction and a second error flag indicating an error for
either byte in the B-to-A direction. The parity error flags are open drain outputs
which can be tied together and/or tied with flags from other devices to form a single
error flag or interrupt. The parity error flags are enabled by the OExx control
pins allowing the designer to disable the error flag during combinational
transitions.
The control pins LEAB, CLKAB, and OEAB control operation in the A-to-B
direction while LEBA, CLKBA, and OEBA control the B-to-A direction. GEN/
CHK is only for the selection of A-to-B operation. The B-to-A direction is always
in checking mode. The ODD/EVEN select is common between the two directions.
Except for the ODD/EVEN control, independent operation can be achieved
between the two directions by using the corresponding control lines.
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Typical tsk(o) (Output Skew) < 250ps, clocked mode
Low input and output leakage ≤1µA (max)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 5V ±10%
Balanced Output Drivers:
– ±24mA (industrial)
– ±16mA (military)
Series current limiting resistors
Generate/Check, Check/Check modes
Open drain parity error allows wire-OR
Available in the following packages:
– Industrial: SSOP, TSSOP
– Military: CERPACK
FUNCTIONAL BLOCK DIAGRAM
LEAB
CLKAB
OEAB
Data
Parity, data
16
Parity
GEN/CHK
A0-15
Byte
Parity
Generator/
Checker
2
18
Latch/
Register
B0-15
PB1,2
PERB
(Open Drain)
PA1,2
ODD/EVEN
LEBA
CLKBA
Parity, Data
Parity, data
18
18
OEBA
Latch/
Register
Byte
Parity
Checking
PERA
(Open Drain)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2009
1
© 2009 Integrated Device Technology, Inc.
DSC-2916/4
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
BLOCK DIAGRAM
ODD/EVEN
OEAB
LEBA
CLKBA
CLKAB
LEAB
A0 - A7
C
C
D
D
C
B0 - B7
C
D
D
OEBA
P
O
PA1
C
C
D
D
PB1
I
P
C
C
D
D
A8 - A15
C
C
D
D
C
C
D
P
O
PA2
B8 - B15
D
C
C
D
D
PB2
I
C
C
D
GEN/CHK
D
C
C
D
D
C
PERA
(Open Drain)
PERB
(Open Drain)
C
D
D
2
P
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
OEAB
1
56
GEN/CHK
LEAB
2
55
CLKAB
PA1
3
54
PB1
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to 7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
GND
4
53
GND
A0
5
52
B0
A1
6
51
B1
VCC
7
50
VCC
A2
8
49
B2
A3
9
48
B3
A4
10
47
B4
A5
11
46
B5
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
A6
12
45
B6
CI/O
I/O Capacitance
VOUT = 0V
3.5
8
pF
A7
13
44
B7
CO
Open Drain
Capacitance
VOUT = 0V
3.5
6
pF
GND
14
43
PERB
PERA
15
42
GND
A8
16
41
B8
A9
17
40
B9
Pin Names
OEAB
Description
A-to-B Output Enable Input (Active LOW)
A10
18
39
B10
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
PIN DESCRIPTION
A11
19
38
B11
A12
20
37
B12
A13
21
36
B13
CLKBA
B-to-A Clock Input
VCC
22
35
VCC
Ax
A-to-B Data Inputs or B-to-A 3-State Outputs
Bx
B-to-A Data Inputs or A-to-B 3-State Outputs
PERA
Parity Error (Open Drain) on A Outputs
PERB
Parity Error (Open Drain) on B Outputs
A14
23
34
B14
A15
24
33
B15
GND
25
32
GND
PAx
B-to-A Parity Input, A-to-B Parity Output
(1)
A-to-B Parity Input, B-to-A Parity Output
PA2
26
31
PB2
PBx
27
30
CLKBA
ODD/EVEN
Parity Mode Selection Input
OEBA
GEN/CHK
A to B Port Generate or Check Mode Input
LEBA
28
29
ODD/EVEN
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
SSOP/ TSSOP/ CERPACK
TOP VIEW
3
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1, 4)
Inputs
FUNCTION TABLE
(PARITY CHECKING) (1, 2, 3, 4)
Outputs
OEAB
H
L
L
L
L
LEAB
X
H
H
L
L
CLKAB
X
X
X
↑
↑
Ax
X
L
H
L
H
Bx
Z
L
H
L
H
L
L
L
X
B(2)
L
L
H
X
B(3)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is
and CLKBA.
2. Output level before the indicated steady-state
3. Output level before the indicated steady-state
provided that CLKAB was HIGH before LEAB
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
A0 – A7 and PA1(5)
Number of inputs that are high
1, 3, 5, 7 or 9
ODD/EVEN
L
PERB
L
1, 3, 5, 7 or 9
H
H(6)
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
L
H
H(6)
L
NOTES:
1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses OEBA = L, OEAB
= H and errors will be indicated on PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along with the
corresponding data regardless of parity errors (PB1 = PA1).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered
clock.
5. Conditions shown are for the byte A0–A7 and PA1. The byte A8–A15 and PA2 is similiar.
6. The parity error flag PERB is a combined flag for both bytes A0–A7 and A8–A15. If a parity
error occurs on either byte PERB will go low. PERB is an open drain output which must
be externally pulled up to achieve a logic HIGH.
similar but uses OEBA, LEBA,
input conditions were established.
input conditions were established,
went LOW.
FUNCTION TABLE
(PARITY GENERATION) (1, 2, 3, 4, 5)
A0 – A7
Number of inputs that are high
1, 3, 5 or 7
1, 3, 5 or 7
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
ODD/EVEN
L
H
L
H
PB1
H
L
L
H
NOTES:
1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B
is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge
triggered clock.
4. Conditions shown are for the byte A–A7. The byte A8–A15 is similiar but will output
the parity on PB2.
5. The error flag PERB will remain in a high state during parity generation.
4
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current (Input pins)(5)
VCC = Max.
—
—
±1
µA
—
—
±1
—
—
±1
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
—
–0.7
–1.2
V
–80
–140
–250
mA
—
100
—
mV
—
5
500
µA
VI = VCC
Input HIGH Current (I/O pins)(5)
IIL
Input LOW Current (Input pins)(5)
VI = GND
Input LOW Current (I/O pins)(5)
IOZH
High Impedance Output Current
IOZL
(3-State Output pins)(5)
VIK
Clamp Diode Voltage
VCC = Max.
VCC = Min., IIN = –18mA
IOS
Short Circuit Current
VCC = Max., VO =
VH
Input Hysteresis
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
GND(3)
—
VCC = Max.
VIN = GND or VCC
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
IODL
Test Conditions(1)
Parameter
Output LOW
(I/O pins)
Current
(Open Drain)
VCC = 5V, VIN = VIH or VIL, VO =
IODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VO =
IOFF
Output Power Off Leakage Current
VCC = 0, VO ≤ 5.5V
1.5V(3)
1.5V(3)
Min.
Typ.(2)
Max.
Unit
60
115
200
mA
—
250
—
mA
–60
–115
–200
mA
—
—
±1
µA
2.4
3.3
—
V
—
0.3
0.55
V
—
0.3
0.55
V
(Open Drain)(5)
VOH
Output HIGH Voltage (I/O pins)
VCC = Min.
IOH = –16mA MIL
VIN = VIH or VIL
IOH = –24mA IND
VOL
Output LOW
VCC = Min.
IOL = 16mA MIL
VIN = VIH or VIL
IOL = 24mA IND
(I/O pins)
Voltage
(Open Drain)
IOL = 48mA MIL
IOL = 64mA IND
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at TA = –55°C.
5
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Min.
Typ.(2)
All other Input Pins
—
Parity Input Pins (PAx, PBx)
—
VIN = VCC
VIN = GND
VCC = Max.
Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = GND, OEBA = VCC
Symbol
Parameter
ΔICC
Quiescent Power Supply Current
VCC = Max.
TTL Inputs HIGH
VIN = 3.4V(3)
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OEAB = GND, OEBA = VCC
One Input Togging
50% Duty Cycle
Total Power Supply Current(6)
ICCD
IC
Max.
Unit
0.5
1.5
mA
1
2.5
—
75
120
µA/
MHz
VIN = VCC
VIN = GND
—
0.8
1.7
mA
LEAB = GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VIN = 3.4V
VIN = GND
—
1.3
3.2
VCC = Max.
Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = GND, OEBA = VCC
VIN = VCC
VIN = GND
—
3.8
6.5(5)
LEAB = GND
Eighteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
VIN = 3.4V
VIN = GND
—
9
21.8(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
6
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(PROPAGATION DELAYS)
FCT162511AT
Ind.
Symbol
Parameter
FCT162511CT
Mil.
Ind.
Mil.
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
1.5
5
1.5
5.3
1.5
4.2
1.5
4.5
ns
1.5
7.5
1.5
8
1.5
6.5
1.5
6.8
ns
tPLH
Propagation Delay, PAx to PBx
CL = 50pF
tPHL
Ax to Bx or Bx to Ax, PBx to PAx
RL = 500Ω
GEN/CHK LOW
tPLH
Propagation Delay
tPHL
Ax to PBx
tPLH(3)
Propagation Delay
1.5
9
1.5
9
1.5
7.5
1.5
7.8
ns
tPHL
Ax to PERB, PAx to PERB
1.5
8
1.5
8
1.5
6.5
1.5
6.8
ns
tPLH(3)
Propagation Delay
1.5
9
1.5
9
1.5
7.5
1.5
7.8
ns
tPHL
Bx to PERA, PBx to PERA
1.5
8
1.5
8
1.5
6.5
1.5
6.8
ns
tPLH
Propagation Delay
tPHL
LEBA to Ax and PAx
1.5
5.6
1.5
6
1.5
5.3
1.5
5.5
ns
LEAB to Bx and PBx
tPLH(3)
Propagation Delay
1.5
7
1.5
7
1.5
6
1.5
6.3
ns
tPHL
LEBA to PERA, LEAB to PERB
1.5
6
1.5
6
1.5
5
1.5
5.3
ns
tPLH
Propagation Delay
tPHL
CLKBA to Ax and PAx
1.5
5.6
1.5
6
1.5
5.3
1.5
5.5
ns
1.5
7
1.5
7
1.5
6
1.5
6.3
ns
1.5
6
1.5
6
1.5
5
1.5
5.3
ns
1.5
6
1.5
6.5
1.5
5.6
1.5
5.8
ns
1.5
5.6
1.5
6
1.5
5.2
1.5
5.5
ns
6
1.5
6.3
1.5
6
1.5
6.3
ns
CLKAB to Bx and PBx
tPLH(3)
Propagation Delay
tPHL
CLKBA to PERA
CLKAB to PERB
tPZH
Output Enable Time
tPZL
OEBA to Ax and PAx
OEAB to Bx and PBx
tPHZ
Output Disable Time
tPLZ
OEBA to Ax and PAx
OEAB to Bx and PBx
tPLZ(3)
Parity ERROR Enable
1.5
tPZL
OEBA to PERA, OEAB to PERB
1.5
6
1.5
6.3
1.5
6
1.5
6.3
ns
tPLH(3)
ODD/EVEN to PERx
1.5
10
1.5
10
1.5
10
1.5
10
ns
1.5
10
1.5
10
1.5
10
1.5
10
ns
1.5
10
1.5
10
1.5
10
1.5
10
ns
tPHL
tPLH
tPHL
ODD/EVEN to PBx
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. On Open Drain Outputs tPLH is measured at VOUT = VOL + 0.3V.
7
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES)
FCT162511AT
Ind.
Symbol
tSU
Test Conditions(1, 3)
Parameter
Set-up Time
GEN/CHK LOW
HIGH or LOW
Ax to CLKAB
tSU
tSU
GEN/CHK HIGH
Mil.
Ind.
Mil.
Min. Max. Min. Max. Min. Max. Min. Max. Unit
PBx valid
CL = 50pF
4
—
4
—
3
—
3.5
—
ns
PBx not valid
RL = 500Ω
3
—
3
—
3
—
3
—
ns
PERB valid
4
—
4
—
3
—
3
—
ns
PERB not valid
3
—
3
—
3
—
3
—
ns
PERB valid
4
—
4
—
3
—
3
—
ns
PAx to CLKAB
PERB not valid
3
—
3
—
3
—
3
—
ns
Set-up Time
PERA valid
4
—
4
—
3
—
3
—
ns
Bx to CLKBA,
PERA not valid
3
—
4
—
3
—
3
—
ns
3.5
—
3.5
—
3
—
3
—
ns
Set-up Time
GEN/CHK HIGH
FCT162511CT
PBx to CLKBA
tSU
tSU
tSU
Set-up Time
CLKAB LOW
PBx valid
Ax to LEAB
GEN/CHK LOW
PBx not valid
3
—
3
—
3
—
3
—
ns
CLKAB LOW
PERB valid
3.5
—
3.5
—
3
—
3
—
ns
GEN/CHK HIGH
PERB not valid
CLKAB HIGH
PBx valid
GEN/CHK LOW
3
—
3
—
3
—
3
—
ns
3.5
—
3.5
—
3
—
3
—
ns
PBx not valid
3
—
3
—
3
—
3
—
ns
CLKAB HIGH
PERB valid
3.5
—
3.5
—
3
—
3
—
ns
GEN/CHK HIGH
PERB not valid
3
—
3
—
3
—
3
—
ns
Set-up Time
CLKAB LOW
PERB valid
3.5
—
3.5
—
3
—
3
—
ns
PAx to LEAB
GEN/CHK HIGH
PERB not valid
3
—
3
—
3
—
3
—
ns
CLKAB HIGH
PERB valid
3.5
—
3.5
—
3
—
3
—
ns
GEN/CHK HIGH
PERB not valid
3
—
3
—
3
—
3
—
ns
CLKBA LOW
PERA valid
3.5
—
3.5
—
3
—
3
—
ns
3
—
3
—
3
—
3
—
ns
3.5
—
3.5
—
3
—
3
—
ns
3
—
3
—
3
—
3
—
ns
—
0.5
—
0.5
—
0.5
—
0.5
ns
Set-up Time
PERA not valid
Bx to LEBA
PBx to LEBA
CLKBA HIGH
PERA valid
PERA not valid
tSK(O)
Output Skew(4)
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (HOLD TIMES)
Symbol
tH
tH
tH
tH
tH
tW
tW
Condition(1)
CL= 50pF
RL = 500Ω
Parameter
Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA
Hold Time HIGH or LOW PAx to LEAB
Hold Time HIGH or LOW PBx to LEBA
Hold Time Ax to CLKAB, PAx to CLKAB
Hold Time Bx to CLKBA, PBx to CLKBA
LEAB or LEBA Pulse Width HIGH(2)
CLKAB or CLKBA Pulse Width HIGH or LOW(2)
FCT162511AT
FCT162511CT
Ind.
Mil.
Ind.
Mil.
Min. Max. Min. Max. Min. Max. Min. Max. Unit
1
—
1
—
1
—
1
—
ns
1
—
1
—
1
—
1
—
ns
1
—
1
—
1
—
1
—
ns
1
—
1
—
0
—
0
—
ns
1
—
1
—
0
—
0
—
ns
3
—
3
—
3
—
3
—
ns
3
—
3
—
3
—
3
—
ns
NOTES:
1. See test circuits and waveforms.
2. This parameter is guaranteed but not tested.
3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the
A to B or B to A port respective to the indicated direction.
4. Skew between any two outputs of the same package, switching in the same direction, excluding PERx in clocked mode, and Pxx (parity bits) and PERx in transparent/
latched mode. This parameter is guaranteed by design.
8
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCH POSITION
TEST CIRCUITS AND WAVEFORMS
V CC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
50pF
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
D.U.T.
RT
Test
500Ω
CL
Test Circuits for All Outputs
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
tH
1.5V
1.5V
Pulse Width
Set-up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
1.5V
0V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
Propagation Delay
SWITCH
OPEN
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
9
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
XX
FCT
Temp. Range
XXX
Family
XXXX
Device Type
XX
Package
X
Process
Blank
B
Industrial
MIL-STD-883, Class B
PVG
PAG
Industrial Options
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
E
Military Options
CERPACK
511AT
511CT
18-Bit Registered/Latched Transceiver
162
Double-Density, 5 Volt, Balanced Drive
54
74
55 C to +125 C
40 C to +85 C
Datasheet Document History
09/06/09 Pg.6
Updated the ordering information by removing the "IDT" notation and non RoHS part.
10
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