IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 18-BIT
REGISTER
IDT74FCT162823AT/CT
FEATURES:
DESCRIPTION:
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•
•
•
•
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The FCT162823T 18-bit bus interface register is built using advanced, dual
metal CMOS technology. These high-speed, low-power registers with clock
enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing
in high-performance synchronous systems. The control inputs are organized
to operate the device as two 9-bit registers or one 18-bit register. Flow-through
organization of signal pins simplifies layout. All inputs are designed with
hysteresis for improved noise margin.
The FCT162823T has balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times – reducing the need for external series terminating resistors. The
FCT162823T is a plug-in replacement for the FCT16823T and ABT16823 for
on-board interface applications.
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤1µA (max.)
VCC = 5V ±10%
Balanced Output Drivers of ±24mA
Reduced system switching noise
Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,
TA = 25°C
• Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
27
2
1OE
1CLR
2OE
1
2CLR
56
1CLK
2CLK
55
28
29
30
1CLKEN
2CLKEN
R
C
D
3
R
C
D
1Q1
54
15
2Q1
42
1D1
2D1
TO EIGHT OTHER CHANNELS
TO EIGHT OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2009
1
© 2009 Integrated Device Technology, Inc.
DSC-5437/7
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
VTERM(2)
Terminal Voltage with Respect to GND
Max
Unit
–0.5 to 7
V
–0.5 to VCC+0.5
V
1CLR
1
56
1CLK
1OE
2
55
1CLKEN
TSTG
Storage Temperature
–65 to +150
°C
1Q1
3
54
1D1
IOUT
DC Output Current
–60 to +120
mA
GND
4
53
GND
1Q2
5
52
1D2
1Q3
6
51
1D3
VCC
7
50
VCC
1Q4
8
49
1D4
1Q5
9
48
1D5
1Q6
10
47
1D6
GND
11
46
GND
1Q7
12
45
1D7
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
COUT
Output Capacitance
VOUT = 0V
3.5
8
pF
1Q8
13
44
1D8
1Q9
14
43
1D9
2Q1
15
42
2D1
2Q2
16
41
2D2
2Q3
17
40
2D3
GND
18
39
GND
2Q4
19
38
2D4
2Q5
20
37
2D5
2Q6
21
36
2D6
VCC
22
35
VCC
2Q7
23
34
2D7
2Q8
24
33
2D8
GND
25
32
GND
2Q9
26
31
2D9
2OE
27
30
2CLKEN
2CLR
28
29
VTERM(3) Terminal Voltage with Respect to GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Outputs and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
Description
xDx
Data Inputs
xCLK
Clock Inputs
xCLKEN
Clock Enable Inputs (Active LOW)
xCLR
Asynchronous clear Inputs (Active LOW)
xOE
Output Enable Inputs (ActiveLOW)
xOx
3-State Outputs
FUNCTION TABLE(1)
xOE
H
L
L
H
H
L
L
2CLK
SSOP/ TSSOP
TOP VIEW
xCLR
X
L
H
H
H
H
H
Inputs
xCLKEN
X
X
H
L
L
L
L
xCLK
X
X
X
↑
↑
↑
↑
xDx
X
X
X
L
H
L
H
Outputs
xQx
Z
L
Q(2)
Z
Z
L
H
Function
High Z
Clear
Hold
Load
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. Output level before indicated steady-state input conditions were established.
2
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current (Input pins)(4)
VCC = Max.
—
—
±1
µA
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(4)
IIL
Input LOW Current (Input pins)(4)
VI = GND
—
—
±1
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
—
–0.7
–1.2
V
–80
–140
–250
mA
—
100
—
mV
—
5
500
µA
Input LOW Current (I/O pins)(4)
IOZH
High Impedance Output Current
IOZL
(3-State Output pins)(4)
VIK
Clamp Diode Voltage
IOS
Short Circuit Current
VH
Input Hysteresis
ICCL
Quiescent Power Supply Current
VCC = Max.
VCC = Min., IIN = –18mA
VCC = Max., VO =
GND(3)
—
VCC = Max
µA
VIN = GND or VCC
ICCH
ICCZ
OUTPUT DRIVE CHARACTERISTICS
Symbol
IODL
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3)
60
115
200
mA
1.5V(3)
Parameter
Output LOW Current
IODH
Output HIGH Current
VCC = 5V, VIN = VIH or VIL, VO =
VOH
Output HIGH Voltage
VCC = Min.
–60
–115
–200
mA
IOH = –24mA
2.4
3.3
—
V
IOL = 24mA
—
0.3
0.55
V
VIN = VIH or VIL
VOL
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This test limit for this parameter is ±5µA at TA = –55°C.
3
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Test Conditions(1)
Symbol
ΔICC
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
ICCD
Dynamic Power Supply Current(4)
VCC = Max.
Outputs Open
xOE = xCLKEN = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
xOE = xCLKEN = GND
at fi = 5MHz
50% Duty Cycle
One Bit Toggling
VCC = Max.
Outputs Open
fCP = 10MHz
50% Duty Cycle
xOE = xCLKEN = GND
at fi = 2.5MHz
50% Duty Cycle
Eighteen Bits Toggling
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
VIN = VCC
VIN = GND
—
75
120
µA/
MHz
VIN = VCC
VIN = GND
—
0.8
1.7
mA
VIN = 3.4V
VIN = GND
—
1.3
3.2
VIN = VCC
VIN = GND
—
4.2
7.1(5)
VIN = 3.4V
VIN = GND
—
9.2
22.1(5)
VCC = Max.
VIN = 3.4V(3)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
tPLH
Propagation Delay
tPHL
xCLKx to xOx
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
xCLR to xQx
Output Enable Time
xOE to xOx
Output Disable Time
xOE to xOx
tSU
Set-up Time HIGH or LOW xDx to xCLK
tH
tSU
tH
tW
tW
Hold Time HIGH or LOW, xDx to xCLK
Set-up Time HIGH or LOW, xCLKEN to xCLK
Hold Time HIGH or LOW, xCLKEN to xCLK
xCLK Pulse Width HIGH or LOW
xCLR Pulse Width LOW
Recovery Time, xCLR to xCLK
Output Skew(3)
tREM
tSK(o)
Condition(1)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL= 500Ω
FCT162823AT
Min.(2)
Max.
1.5
10
Unit
ns
1.5
20
1.5
8
1.5
14
1.5
4.7
ns
1.5
12
1.5
4.4
ns
1.5
23
1.5
9
1.5
7
1.5
3.6
1.5
8
1.5
3.6
3
—
1.5
—
ns
1.5
3
0
6
6
6
—
—
—
—
—
—
—
0.5
0
2.5
0
3
3
3
—
—
—
—
—
—
—
0.5
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
4. This condition is guaranteed but not tested.
5
FCT162823CT
Min.(2)
Max.
1.5
4.7
ns
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
SWITCH POSITION
7.0V
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
CL
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
Propagation Delay
SWITCH
OPEN
1.5V
0V
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT162823AT/CT
FAST CMOS 18-BIT REGISTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX
FCT
Temp. Range
XXX
Family
XXXX
Device Type
XX
Package
PVG
PAG
Shrink Small Outline Package - Green
Thin Shrink Small Outline Package - Green
823AT
823CT
18-Bit Register
162
Double-Density, 5 Volt, Balanced Drive
74
40 C to +85 C
Datasheet Document History
09/06/09 Pg. 7
Updated the ordering information by removing the "IDT" notation and non RoHS part.
7
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