74FCT163244APAG

IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT BUFFER/LINE DRIVER IDT74FCT163244A/C FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range μ W typ. static) • CMOS power levels (0.4μ • Rail-to-rail output swing for increased noise margin • Low Ground Bounce (0.3V typ.) • Inputs (except I/O) can be driven by 3.3V or 5V components • Available in SSOP, TSSOP, and TVSOP packages The FCT163244 16-bit buffer/line drivers are built using advanced dual metal CMOS technology. These high-speed, low-power devices offer bus/ backplane interface capability with improved packing density. These devices have a flow-through organization for simplifying board layout. The three-state controls operate these devices in a Quad-Nibble, Dual-Byte or single 16-bit word mode. All inputs are designed with hysteresis for improved noise margin. The inputs of the FCT163244 can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V supply system. Thus, the FCT163244 can be used as buffers to connect 5V components to a 3.3V bus. FUNCTIONAL BLOCK DIAGRAM 25 1 1OE 1A1 1A2 1A3 1A4 2OE 3OE 47 2 46 3 44 5 43 6 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 48 4OE 41 8 2A2 40 9 2A3 38 2A4 37 2A1 1Y1 2Y1 4A1 2Y2 4A2 11 2Y3 4A3 12 2Y4 4A4 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2009 1 © 2009 Integrated Device Technology, Inc. DSC-2532/12 IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION 48 Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to 7 V VTERM(4) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V 1A1 TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +60 mA 1OE 1 1Y1 2 47 1Y2 3 46 1A2 GND 4 45 GND 1Y3 5 44 1A3 1Y4 6 43 1A4 VCC 7 42 VCC 2Y1 8 41 2A1 2Y2 9 40 2A2 GND 10 39 GND 2Y3 11 38 2A3 2Y4 12 37 2A4 3Y1 13 36 3A1 3Y2 14 35 3A2 GND 15 34 GND 3Y3 16 33 3A3 3Y4 17 32 3A4 VCC 18 31 VCC 4Y1 19 30 4A1 2OE 4Y2 20 29 4A2 GND 21 28 GND 4Y3 22 27 4A3 4Y4 23 26 4A4 4OE 24 25 3OE NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 3.5 6 pF COUT Output Capacitance VOUT = 0V 3.5 8 pF NOTE: 1. This parameter is measured at characterization but not tested. PIN DESCRIPTION Pin Names Description xOE 3-State Output Enable Inputs (Active LOW) xAx Data Inputs xYx 3-State Outputs FUNCTION TABLE(1) Inputs SSOP/ TSSOP/ TVSOP TOP VIEW xOE xAx xYx L L L L H H H X Z NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High-Impedance 2 Outputs IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V Symbol VIH Test Conditions(1) Min. Typ.(2) Max. Unit 2 — 5.5 V 2 — VCC+0.5 –0.5 — 0.8 VI = 5.5V — — ±1 Input HIGH Current (I/O pins) VI = VCC — — ±1 Input LOW Current (Input pins) VI = GND — — ±1 Input LOW Current (I/O pins) VI = GND — — ±1 VO = VCC — — ±1 VO = GND — — ±1 — –0.7 –1.2 V –36 –60 –110 mA mA Parameter Input HIGH Level (Input pins) Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level IIH Input HIGH Current (Input pins) IIL IOZH High Impedance Output Current IOZL (3-State Output pins) VIK Clamp Diode Voltage IODH Output HIGH Current VCC = Max. VCC = Max. VCC = Min., IIN = –18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V (3) (3) IODL Output LOW Current VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V VOH Output HIGH Voltage VCC = Min. IOH = –0.1mA VIN = VIH or VIL IOH = –3mA VCC = 3V IOH = –8mA 50 90 200 VCC-0.2 — — 2.4 3 — 3 — (5) 2.4 V µA µA V VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. IOL = 0.1mA — — 0.2 VIN = VIH or VIL IOL = 16mA — 0.2 0.4 IOL = 24mA — 0.3 0.55 IOL = 24mA — 0.3 0.5 –60 –135 –240 mA — 150 — mV — 0.1 10 µA VCC = 3V V VIN = VIH or VIL (4) IOS Short Circuit Current VH Input Hysteresis ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max., VO = GND(3) — VCC = Max. VIN = GND or VCC NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC–0.6V at rated current. 3 IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. Typ.(2) Max. Unit — 2 30 µA VIN = VCC VIN = GND — 50 75 µA/ MHz VCC = Max. Outputs Open fi = 10MHz VIN = VCC VIN = GND — 0.5 0.8 mA 50% Duty Cycle xOE = GND One Bit Toggling VIN = VCC - 0.6V VIN = GND — 0.5 0.8 VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND — 2 3(5) xOE = GND Sixteen BitsTogging VIN = VCC - 0.6V VIN = GND — 2 3.3(5) Symbol Parameter ΔICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = VCC - 0.6V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open xOE = GND One Input Togging 50% Duty Cycle Total Power Supply Current(6) IC NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input. All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ΔICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay xAx to xYx Output Enable Time FCT163244A Min.(3) Max. 1.5 4.8 Condition(2) CL = 50pF RL = 500Ω FCT163224C Min.(3) Max. 1.5 4.1 Unit ns 1.5 6.2 1.5 5.8 ns Output Disable Time 1.5 5.6 1.5 5.2 ns Output Skew(4) — 0.5 — 0.5 ns NOTES: 1. Propagation Delays and Enable/Disable times are with VCC = 3.3V±0.3V (normal range). For VCC = 2.7 to 3.6V (extended range), all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4 IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS 6v Open V CC 500 Ω V OUT VIN Pulse Generator SWITCH POSITION D.U.T . 50pF RT CL GND Test Switch Open Drain Disable Low Enable Low 6V Disable High Enable High GND All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500 Ω Test Circuits for All Outputs DATA INPUT tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR tSU CLOCK ENABLE ETC. tH tREM 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 3V 1.5V 0V tH 1.5V 1.5V Pulse Width Set-up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V 1.5V CONTROL INPUT tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH 6V 3V 1.5V tPZH OUTPUT NORMALLY HIGH Propagation Delay SWITCH GND 0V tPLZ 3V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC. 5 IDT74FCT163244A/C 3.3V CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XX FCT XXX Temp. Range Family XXXX Device Type X Package PVG PAG PFG Shrink Small Outline Package - Green Thin Shrink Small Outline Package - Green Thin Very Small Outline Package - Green 244A 244C Non-Inverting 16-Bit Buffer/Line Driver 163 Double-Density 3.3Volt 74 − 40°C to +85°C Datasheet Document History 09/10/09 Pg.6 Updated the ordering information by removing the "IDT" notation and non RoHS part. 6 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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