IDT74FCT16501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
18-BIT REGISTERED
TRANSCEIVER
IDT74FCT16501AT/CT
FEATURES:
DESCRIPTION:
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The FCT16501T 18-bit registered transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power 18-bit registered
bus transceivers combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA)
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is high. When LEAB is low, the A data
is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus
data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB
is the output enable for the B port. Data flow from the B port to the A port is similar
but requires using OEBA, LEBA and CLKBA. Flow-through organization of
signal pins simplifies layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT16501T are ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used as backplane
drivers.
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0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤ 1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
High drive outputs (–32mA IOH, 64mA IOL)
Power off disable outputs permit “live insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKBA
LEBA
1
30
28
27
OEBA
CLKAB
LEAB
A1
55
2
3
C
C
D
D
54
C
C
D
D
B1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2009
1
© 2009 Integrated Device Technology, Inc.
DSC-5435/5
IDT74FCT16501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
OEAB
1
56
VTERM(2) Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Max
Unit
–0.5 to 7
V
LEAB
2
55
CLKAB
VTERM(3)
–0.5 to VCC+0.5
V
A1
3
54
B1
TSTG
Storage Temperature
–65 to +150
°C
GND
4
53
GND
IOUT
DC Output Current
–60 to +120
mA
A2
5
52
B2
A3
6
51
B3
VCC
7
50
VCC
A4
8
49
B4
A5
9
48
B5
A6
10
47
B6
GND
11
46
GND
A7
12
45
B7
A8
13
44
B8
A9
14
43
B9
Symbol
A10
15
42
B10
A11
16
41
B11
A12
17
40
B12
GND
18
39
GND
A13
19
38
B13
A14
20
37
B14
A15
21
36
B15
VCC
22
35
VCC
A16
23
34
B16
A17
24
33
B17
GND
25
32
GND
A18
26
31
B18
OEBA
27
30
CLKBA
LEBA
28
29
GND
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
COUT
Output Capacitance
VOUT = 0V
3.5
8
pF
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(1, 4)
OEAB
L
H
H
H
H
H
H
TSSOP
LEAB
X
H
H
L
L
L
L
Inputs
CLKAB
X
X
X
↑
↑
L
H
Ax
X
L
H
L
H
X
X
Outputs
Bx
Z
L
H
L
H
B(2)
B(3)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and
CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
TOP VIEW
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
Description
GND
Description
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
2
IDT74FCT16501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current (Input pins)(5)
VCC = Max.
—
—
±1
µA
—
—
±1
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
IIL
Input LOW Current (Input pins)(5)
VI = GND
Input LOW Current (I/O pins)(5)
IOZH
High Impedance Output Current
IOZL
(3-State Output pins)(5)
VIK
Clamp Diode Voltage
IOS
Short Circuit Current
VH
Input Hysteresis
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
—
–0.7
–1.2
–80
–140
–250
mA
—
100
—
mV
—
5
500
µA
VCC = Min., IIN = –18mA
VCC = Max., VO =
GND(3)
—
VCC = Max.
VIN = GND or VCC
µA
V
OUTPUT DRIVE CHARACTERISTICS
Symbol
IO
VOH
Parameter
Output Drive Current
Output HIGH Voltage
VOL
Output LOW Voltage
IOFF
Input/Output Power Off Leakage(5)
Test Conditions(1)
VCC = Max., VO = 2.5V(3)
VCC = Min.
IOH = –3mA
VIN = VIH or VIL
IOH = –15mA
IOH = –32mA(4)
VCC = Min.
IOL = 64mA
VIN = VIH or VIL
VCC = 0V, VIN or VO ≤ 4.5V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at TA = –55°C.
3
Min.
–50
2.5
2.4
2
—
Typ.(2)
—
3.5
3.5
3
0.2
Max.
–180
—
—
—
0.55
Unit
mA
—
—
±1
μA
V
V
IDT74FCT16501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔICC
ICCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current(4)
IC
Total Power Supply Current(6)
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.,
Outputs Open
OEAB = OEBA = VCC or GND
One Input Toggling
50% Duty Cycle
VCC = Max.,
Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
One Bit Toggling
fi = 5MHz
50% Duty Cycle
VCC = Max.,
Outputs Open
fCP = 10MHz (CLKAB)
50% Duty Cycle
OEAB = OEBA = VCC
LEAB = GND
Eighteen Bits Toggling
fi = 2.5MHz
50% Duty Cycle
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
VIN = VCC
VIN = GND
—
75
120
µA/
MHz
VIN = VCC
VIN = GND
—
0.8
1.7
mA
VIN = 3.4V
VIN = GND
—
1.3
3.2
VIN = VCC
VIN = GND
—
3.8
6.5(5)
VIN = 3.4V
VIN = GND
—
8.5
20.8(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT16501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
tH
tSU
tH
tW
tW
tSK(o)
Parameter
Condition(1)
CLKAB or CLKBA frequency(3)
CL = 50pF
RL = 500Ω
Propagation Delay
Ax to Bx or Bx to Ax
Propagation Delay
LEBA to Ax, LEAB to Bx
Propagation Delay
CLKBA to Ax, CLKAB to Bx
Output Enable Time
OEBA to Ax, OEAB to Bx
Output Disable Time
OEBA to Ax, OEAB to Bx
Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Set-up Time HIGH or LOW
Clock LOW
Ax to LEAB, Bx to LEBA
Clock HIGH
Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
LEAB or LEBA Pulse Width HIGH(3)
CLKAB or CLKBA Pulse Width HIGH or LOW(3)
Output Skew(4)
FCT16501AT
Min.(2)
Max.
Unit
—
1.5
150
5.1
—
1.5
150
4.3
MHz
ns
1.5
5.6
1.5
4.4
ns
1.5
5.6
1.5
4.4
ns
1.5
6
1.5
4.8
ns
1.5
5.6
1.5
5.2
ns
3
—
2.4
—
ns
0
—
0
—
ns
3
1.5
1.5
—
—
—
2
1.5
0.5
—
—
—
ns
ns
3
3
—
—
3
3
—
—
ns
ns
—
0.5
—
0.5
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
5
FCT16501CT
Min.(2)
Max.
IDT74FCT16501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
SWITCH POSITION
7.0V
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
CL
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
1.5V
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
Propagation Delay
SWITCH
OPEN
1.5V
0V
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT16501AT/CT
FAST CMOS 18-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX
FCT
Temp. Range
XXX
Family
XXXX
Device Type
XX
Package
PAG
Thin Shrink Small Outline Package - Green
501AT
501CT
18-Bit Registered Transceiver
16
Double-Density, 5 Volt, High Drive
74
40 C to +85 C
Datasheet Document History
09/28/09 Pg. 7
Updated the ordering information by removing the "IDT" notation and non RoHS part.
7
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