IDT74FCT16952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
IDT74FCT16952AT/CT/ET
FAST CMOS
16-BIT REGISTERED
TRANSCEIVER
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage ≤1µA (max.)
High drive outputs (-32mA IOH, 64mA IOL)
Power off disable outputs permit “live insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
• Available in SSOP and TSSOP packages
The FCT16952T 16-bit registered transceiver is built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type registered transceivers with
separate input and output control for independent control of data flow in either
direction. For example, the A-to-B Enable (xCEAB) must be low to enter
data from the A port. xCLKAB controls the clocking function. When xCLKAB
toggles from low-to-high, the data present on the A port will be clocked into
the register. xOEAB performs the output enable function on the B port. Data
flow from the B port to A port is similar but requires using xCEBA, xCLKBA,
and xOEBA inputs. Full 16-bit operation is achieved by tying the control pins
of the independent transceivers together.
The FCT16952T is ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability allowing "live insertion" of boards when used as backplane
drivers.
FUNCTIONAL BLOCK DIAGRAM
54
31
2CEBA
1CEBA
1CLKBA
1OEAB
1CEAB
55
2CLKBA
28
1
2OEAB
3
2CEAB
2
2CLKAB
1CLKAB
1OEBA
1A1
56
5
30
2OEBA
C
CE
D
52
2A1
26
27
29
C
CE
D
15
1B1
42
2B1
C
CE
D
C
CE
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2018
1
© 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5442/7
IDT74FCT16952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
PIN CONFIGURATION
Pin Names
1OEAB
1
56
1OEBA
Description
xOEAB
A-to-B Output Enable Input (Active LOW)
xOEBA
B-to-A Output Enable Input (Active LOW)
xCEAB
A-to-B Clock Enable Input (Active LOW)
1CLKAB
2
55
1CLKBA
1CEAB
3
54
1CEBA
xCEBA
B-to-A Clock Enable Input (Active LOW)
GND
4
53
GND
xCLKAB
A-to-B Clock Input
1A1
5
52
1B1
xCLKBA
B-to-A Clock Input
1A2
6
51
1B2
xAx
A-to-B Data Inputs or B-to-A 3-State Outputs
VCC
7
50
VCC
xBx
B-to-A Data Inputs or A-to-B 3-State Outputs
1A3
8
49
1B3
1A4
9
48
1B4
1A5
10
47
1B5
Symbol
GND
VTERM(2) Terminal Voltage with Respect to GND
GND
11
46
ABSOLUTE MAXIMUM RATINGS(1)
–0.5 to VCC+0.5
V
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–60 to +120
mA
1B6
1A7
13
44
1B7
1A8
14
43
1B8
2A1
15
42
2B1
2A2
16
41
2B2
2A3
17
40
2B3
GND
18
39
GND
2A4
19
38
2B4
2A5
20
37
2B5
2A6
21
36
2B6
VCC
22
35
VCC
CIN
2A7
23
34
2B7
COUT
2A8
24
33
2B8
GND
25
32
GND
2CEAB
26
31
2CEBA
2CLKAB
27
30
2CLKBA
2OEAB
28
29
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
PAG
PVG56
PVG
Conditions
Typ.
Max.
Unit
Input Capacitance
VIN = 0V
3.5
6
pF
Output Capacitance
VOUT = 0V
3.5
8
pF
FUNCTION TABLE(1,3)
Inputs
TOP VIEW
PAG56
Parameter(1)
NOTE:
1. This parameter is measured at characterization but not tested.
2OEBA
SSOP
V
Terminal Voltage with Respect to GND
45
TSSOP
Unit
TSTG
12
Package Code
Max
–0.5 to +7
VTERM(3)
1A6
Package Type
Description
Order Code
Outputs
xCEAB
xCLKAB
xOEAB
xAx
xBx
H
X
L
X
B(2)
X
L
L
X
B(2)
L
↑
L
L
L
L
↑
L
H
H
X
X
H
X
Z
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA, and
xOEBA.
2. Level of B before the indicated steady-state input conditions were established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
Z = High-impedance
2
IDT74FCT16952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
Symbol
Test Conditions(1)
Parameter
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current (Input pins)(5)
VCC = Max.
—
—
±1
µA
—
—
±1
VI = VCC
Input HIGH Current (I/O pins)(5)
IIL
Input LOW Current (Input pins)(5)
VI = GND
—
—
±1
—
—
±1
VO = 2.7V
—
—
±1
VO = 0.5V
—
—
±1
Input LOW Current (I/O pins)(5)
IOZH
High Impedance Output Current
IOZL
(3-State Output pins)(5)
VCC = Max.
VIK
Clamp Diode Voltage
VCC = Min., IIN = –18mA
—
–0.7
–1.2
V
IOS
Short Circuit Current
VCC = Max., VO = GND(3)
–80
–140
–250
mA
VH
Input Hysteresis
—
100
—
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
—
5
500
µA
—
VCC = Max.
VIN = GND or VCC
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
IO
VOH
Test Conditions(1)
Parameter
Output Drive Current
Output HIGH Voltage
VCC = Max., VO =
VCC = Min.
VIN = VIH or VIL
2.5V(3)
IOH = –3mA
IOH = –15mA
IOH = –32mA(4)
IOL = 64mA
VOH
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOFF
Input/Output Power Off Leakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5μA at TA = -55°C.
3
Min.
Typ.(2)
Max.
Unit
–50
2.5
2.4
2
—
—
3.5
3.5
3
0.2
–180
—
—
—
0.55
mA
—
—
±1
μA
V
V
IDT74FCT16952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔICC
ICCD
IC
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current(4)
Total Power Supply Current(6)
Test Conditions(1)
VCC = Max.
VIN = 3.4V(3)
VCC = Max.,
Outputs Open
xOEAB = xOEBA = GND
One Input Toggling
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = VCC
fi = 5MHz
50% Duty Cycle
One Bit Toggling
VCC = Max., Outputs Open
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = VCC
fi = 2.5MHz
50% Duty Cycle
Sixteen Bits Toggling
Min.
—
Typ.(2)
0.5
Max.
1.5
Unit
mA
VIN = VCC
VIN = GND
—
75
120
µA/
MHz
VIN = VCC
VIN = GND
—
0.8
1.7
mA
VIN = 3.4V
VIN = GND
—
1.3
3.2
VIN = VCC
VIN = GND
—
3.8
6.5(5)
VIN = 3.4V
VIN = GND
—
8.3
20(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT16952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
FCT16952AT FCT16952CT
Symbol
Parameter
FCT16952ET
Condition(1)
Min.(2)
Max.
Min.(2)
Max. Min.(2)
Max.
Unit
CL = 50pF
RL = 500Ω
2
10
2
6.3
1.5
3.7
ns
tPLH
tPHL
Propagation Delay
xCLKAB, xCLKBA to xBx, xAx
tPZH
tPZL
Output EnableTime
xOEBA, xOEAB to xAx, xBx
1.5
10.5
1.5
7
1.5
4.4
ns
tPHZ
tPLZ
Output Disable Time
xOEBA, xOEAB to xAx, xBx
1.5
10
1.5
6.5
1.5
3.6
ns
tSU
Set-up Time, HIGH or LOW
2.5
—
2.5
—
1.5
—
ns
2
—
1.5
—
0
—
ns
3
—
3
—
2
—
ns
2
—
2
—
0
—
ns
Pulse Width HIGH or LOW, xCLKAB or xCLKBA (3)
3
—
3
—
3
—
ns
Output Skew(4)
—
0.5
—
0.5
—
0.5
ns
xAx, xBx to xCLKAB, xCLKBA
tH
Hold Time, HIGH or LOW
xAx, xBx to xCLKAB, xCLKBA
tSU
Set-up Time, HIGH or LOW
xCEBA, xCEAB, to xCLKAB, xCLKBA
tH
Hold Time, HIGH or LOW
xCEBA, xCEAB, to xCLKAB, xCLKBA
tW
tSK(o)
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. This limit is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT16952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
SWITCH POSITION
7.0V
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
CL
Test Circuits for All Outputs
DATA
INPUT
tH
tSU
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tREM
tSU
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
tW
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
3V
1.5V
0V
tH
1.5V
1.5V
Pulse Width
Set-up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPHL
3V
1.5V
0V
VOH
1.5V
VOL
DISABLE
3V
CONTROL
INPUT
tPZL
OUTPUT
NORMALLY
LOW
3V
1.5V
0V
SWITCH
CLOSED
tPLZ
3.5V
1.5V
tPZH
OUTPUT
NORMALLY
HIGH
Propagation Delay
SWITCH
OPEN
1.5V
0V
3.5V
0.3V
VOL
tPHZ
0.3V
1.5V
0V
VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT16952AT/CT/ET
FAST CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX
FCT XXX
Temp. Range
Family
XXXX
Device Type
X
X
Package
X
Blank
8
Tube
Tape and Reel
G
Green
PV
PA
Shrink Small Outline Package (PVG48)
Thin Shrink Small Outline Package (PAG48)
952AT
952CT
952ET
16-Bit Registered Transceiver
16
Double-Density, 5 Volt, High Drive
74
− 40°C to +85°C
Orderable Part Information
Speed
(ns)
A
C
E
Pkg.
Code
Pkg.
Type
Temp.
Grade
74FCT16952ATPAG
PAG56
TSSOP
I
74FCT16952ATPAG8
PAG56
TSSOP
I
74FCT16952ATPVG
PVG56
SSOP
I
74FCT16952ATPVG8
PVG56
SSOP
I
74FCT16952CTPAG
PAG56
TSSOP
I
74FCT16952CTPAG8
PAG56
TSSOP
I
74FCT16952CTPVG
PVG56
SSOP
I
Orderable Part ID
74FCT16952CTPVG8
PVG56
SSOP
I
74FCT16952ETPAG
PAG56
TSSOP
I
74FCT16952ETPAG8
PAG56
TSSOP
I
74FCT16952ETPVG
PVG56
SSOP
I
74FCT16952ETPVG8
PVG56
SSOP
I
Datasheet Document History
09/28/2009
09/25/2017
Pg. 7
Pg. 1, 2, 5, 7
05/07/2018
Pg. 2-7
Updated the ordering information by removing the "IDT" notation and non RoHS part.
Added table under pin configuration diagram with detailed package information. Updated the ordering information
diagram by adding Tube, Tape and Reel. Added orderable part information table.
Corrected typo in device name header.
7
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.