74FCT377ATSOG8

IDT74FCT377AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE INDUSTRIAL TEMPERATURE RANGE FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE IDT74FCT377AT/CT/DT FEATURES: DESCRIPTION: • • • • The IDT74FCT377T is an octal D flip-flop built using an advanced dual metal CMOS technology. The IDT74FCT377T has eight edge-triggered, D-type flip-flops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is low. The register is fully edge-triggered. The state of each D input, one set-up time before the low-to-high clock transition, is transferred to the corresponding flip-flop’s O output. The CE input must be stable only one set-up time prior to the low-to-high transition for predictable operation. • • • • A, C, and D grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permit "live insertion" Available in SOIC and QSOP packages FUNCTIONAL BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 CE D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP CP O0 O1 O2 O3 O4 O5 O6 O7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE OCTOBER 2009 1 © 2009 Integrated Device Technology, Inc. DSC-2630/14 IDT74FCT377AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION CE 20 1 VCC O0 2 19 O7 D0 3 18 D7 D1 4 17 D6 O1 5 16 O6 O2 6 15 O5 D2 7 14 D5 D3 8 13 D4 Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol O3 GND 9 12 O4 10 11 CP Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF NOTE: 1. This parameter is measured at characterization but not tested. SOIC/ QSOP TOP VIEW PIN DESCRIPTION Pin Names D0 – D7 CE O 0 – O7 CP Description Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input FUNCTION TABLE(1) Inputs CP CE D O Load “1” ↑ l h H Load “0” ↑ l l L Hold ↑ H h H X X No Change No Change Operating Mode NOTE: 1. H = h = L = l = X = ↑ = 2 Outputs HIGH Voltage Level HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition LOW Voltage Level LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition Don't Care LOW-to-HIGH Clock Transition IDT74FCT377AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial : TA = –40°C to +85°C, VCC = 5.0V ± 5% Symbol Test Conditions(1) Min. Typ.(2) Max. Unit Guaranteed Logic HIGH Level 2 — — V Guaranteed Logic LOW Level — — 0.8 V Parameter VIH Input HIGH Level VIL Input LOW Level (4) IIH Input HIGH Current IIL Input LOW Current(4) (4) II Input HIGH Current VIK Clamp Diode Voltage VCC = Max. VI = 2.7V — — ±1 µA VCC = Max. VI = 0.5V — — ±1 µA VCC = Max., VI = VCC (Max.) — — ±1 µA VCC = Min., IN = –18mA — –0.7 –1.2 V (3) IOS Short Circuit Current VCC = Max. , VO = GND –60 –120 –225 mA VOH Output HIGH Voltage VCC = Min. IOH = –8mA 2.4 3.3 — V VIN = VIH or VIL IOH = –12mA 2 3 — VCC = Min. IOL = 48mA — 0.3 0.5 V — — ±1 µA — 200 — mV — 0.01 1 mA VOL Output LOW Voltage VIN = VIH or VIL IOFF Input/Output Power Off VCC = 0V, VIN or VO - 4.5V (5) Leakage VH Input Hysteresis — ICC Quiescent Power VCC = Max. Supply Current VIN = GND or VCC NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = -55°C. 5. This parameter is guaranted but not tested. 3 IDT74FCT377AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol Test Conditions(1) Parameter Min. Typ.(2) Max. Unit — 0.5 2 mA ΔICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD Dynamic Power Supply Current(4) VCC = Max., Outputs Open CE = GND One Input Toggling 50% Duty Cycle VIN = VCC VIN = GND — 0.15 0.25 mA/ MHz IC Total Power Supply Current(6) VCC = Max., Outputs Open fCP = 10MHz VIN = VCC VIN = GND — 1.5 3.5 mA CE = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VIN = 3.4V VIN = GND — 2 5.5 VCC = Max., Outputs Open fCP = 10MHz, 50% Duty Cycle VIN = VCC VIN = GND — 3.8 7.3(5) CE = GND Eight Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = 3.4V VIN = GND — 6 16.3(5) NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol tPLH tPHL tSU tH tSU tH tW Parameter Propagation Delay CP to Qx Set-up Time HIGH or LOW Dx to CP Hold Time HIGH or LOW Dx to CP Set-up Time HIGH or LOW CE to CP Hold Time HIGH or LOW CE to CP CP Pulse Width HIGH or LOW (1) Condition CL = 50pF RL = 500Ω 74FCT377AT Min.(2) Max. 2 7.2 74FCT377CT Min.(2) Max. 2 5.2 74FCT377DT Min.(2) Max. 2 4.4 Unit ns 2 — 2 — 2 — ns 1.5 — 1.5 — 1 — ns 3.5 — 3.5 — 3 — ns 1.5 — 1.5 — 0 — ns 8 — 6 — 3 — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 4 IDT74FCT377AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500W V OUT VIN Pulse Generator D.U.T . 50pF RT 500W Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL Octal Link Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Octal Link Octal Link Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED tPLZ 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 3.5V 0.3V VOL tPHZ 0.3V 1.5V 0V Octal Link VOH 0V Octal Link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 5 IDT74FCT377AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XXXX XX FCT Device Type Temp. Range XX Package X Process Blank Industrial SOG QG Small Outline IC - Green Quarter-size Small Outline Package - Green 377AT 377CT 377DT Fast CMOS Octal D Flip-Flop with Clock Enable 74 40 C to +85 C Datasheet Document History 10/03/09 Pg. 6 Updated the ordering information by removing the "IDT" notation and non RoHS part. 6 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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