74LVC16827APAG8

IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O FEATURES: IDT74LVC16827A DESCRIPTION: • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range μ W typ. static) • CMOS power levels (0.4μ • All inputs, outputs, and I/O are 5V tolerant • Supports hot insertion • Available in TSSOP package This 20-bit buffer is built using advanced dual metal CMOS technology. The LVC16827A provides high-performance bus interface buffering for wide data/address paths or buses carrying parity. Two pairs of NAND-ed output enable controls offer maximum control flexibility and are organized to operate the device as two 10-bit buffers or one 20-bit buffer. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The LVC16827A buffer is ideally suited for driving high capacitance loads and low impedance backplanes. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V/5V supply system. The LVC16827A has been designed with a ±24mA output driver. The driver is capable of driving a moderate to heavy load while maintaining speed performance. DRIVE FEATURES: • High Output Drivers: ±24mA • Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM 1OE1 1OE2 1A1 1 2OE1 56 2OE2 55 2 1Y1 2A1 28 29 42 15 2Y1 TO NINE OTHER CHANNELS TO NINE OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE AUGUST 2015 1 © 2015 Integrated Device Technology, Inc. DSC-4489/6 IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol 1OE1 1 56 1OE2 1Y1 2 55 1A1 Description Max Unit VTERM Terminal Voltage with Respect to GND –0.5 to +6.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –50 to +50 mA IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 –50 mA ICC ISS Continuous Current through each VCC or GND ±100 mA 1Y2 3 54 1A2 GND 4 53 GND 1Y3 5 52 1A3 1Y4 6 51 1A4 VCC 7 50 VCC 1Y5 8 49 1A5 1Y6 9 48 1Y7 10 47 1A7 GND 11 46 GND Symbol Conditions Typ. Max. Unit 1Y8 12 45 1A8 CIN Input Capacitance VIN = 0V 4.5 6 pF 1Y9 13 44 1A9 COUT Output Capacitance VOUT = 0V 6.5 8 pF CI/O I/O Port Capacitance VIN = 0V 6.5 8 pF 1Y10 14 43 1A10 2Y1 15 42 2A1 2Y2 16 41 2A2 2Y3 17 40 2A3 GND 18 39 GND 2Y4 19 38 2A4 2Y5 20 37 2A5 2Y6 21 36 2A6 VCC 22 35 VCC 2Y7 23 34 2A7 2Y8 24 33 2A8 GND 25 32 GND 2Y9 26 31 2A9 2Y10 27 30 2A10 29 2OE2 2OE1 28 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1A6 CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) NOTE: 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description xOEx Output Enable Inputs (Active LOW) xAx Data Inputs xYx 3-State Outputs FUNCTION TABLE(1) Inputs TSSOP TOP VIEW xOE1 xOE2 xAx xYx L L L L L L H H H X X Z X H X Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2 Outputs IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 μA IOZH High Impedance Output Current VCC = 3.6V VO = 0 to 5.5V — — ±10 μA IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 5.5V — — ±50 μA VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ΔICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 — — 10 mV μA 3.6 ≤ VIN ≤ 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND — — — — 10 500 μA IIH IIL Quiescent Power Supply Current Variation NOTES: 1. Typical values are at VCC = 3.3V, +25°C ambient. 2. This applies in the disabled state only. OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit VCC – 0.2 — V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2.2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance per Buffer/Driver Outputs enabled CPD Power Dissipation Capacitance per Buffer/Driver Outputs disabled Test Conditions Typical CL = 0pF, f = 10Mhz Unit pF SWITCHING CHARACTERISTICS(1) VCC = 2.7V Symbol tPLH Parameter Propagation Delay tPHL xAx to xYx tPZH Output Enable Time tPZL xOEx to xYx tPHZ Output Disable Time tPLZ xOEx to xYx tSK(o) Output Skew(2) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 4 VCC = 3.3V ± 0.3V Min. 1.5 Max. 4.7 Min. 1.5 Max. 4.1 Unit ns 1.5 6.5 1.5 5.8 ns 1.5 6.4 1.5 5.7 ns — — — 500 ps IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF Pulse (1, 2) Generator VIN DISABLE tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500 CL DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Switch VLOAD TIMING INPUT Disable High Enable High GND ASYNCHRONOUS CONTROL All Other Tests Open SYNCHRONOUS CONTROL tSK (x) tPLH2 VOH VT VOL tH tREM tSU tH LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT LVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V Set-up, Hold, and Release Times VOH VT VOL OUTPUT 2 VOH VOH-VHZ 0V VT 0V LVC Link VIH VT 0V tSK (x) tPHZ Enable and Disable Times DATA INPUT tPHL1 VLOAD/2 VOL+VLZ VOL NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Open Drain Disable Low Enable Low tPLZ VLOAD/2 VT LVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. Test VIH VT 0V CONTROL INPUT Test Circuit for All Outputs OUTPUT 1 VIH VT 0V ENABLE GND VOUT tPLH1 tPHL Propagation Delay LVC Link INPUT tPLH LVC Link D.U.T. RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500 tPLH OUTPUT VLOAD VCC VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION LVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 IDT74LVC16827A 3.3V CMOS 20-BIT BUFFER WITH 5V TOLERANT I/O INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION X LVC XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package X Blank 8 Tube or Tray Tape and Reel PAG Thin Shrink Small Outline Package - Green 827A 20-Bit Buffer 16 Double-Density, ±24mA Blank No Bus-hold 74 -40°C to +85°C DATASHEET DOCUMENT HISTORY 08/20/2015 Pg. 6 Updated the ordering information by removing non RoHS parts and adding Tape and Reel information. 6 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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